1 /* $NetBSD: if_fxp_pci.c,v 1.22 2002/04/04 23:15:45 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.22 2002/04/04 23:15:45 thorpej Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <machine/bus.h> 72 #include <machine/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 void *psc_powerhook; /* power hook */ 90 91 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 92 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 93 }; 94 95 int fxp_pci_match __P((struct device *, struct cfdata *, void *)); 96 void fxp_pci_attach __P((struct device *, struct device *, void *)); 97 98 int fxp_pci_enable __P((struct fxp_softc *)); 99 void fxp_pci_disable __P((struct fxp_softc *)); 100 101 static void fxp_pci_confreg_restore __P((struct fxp_pci_softc *psc)); 102 static void fxp_pci_power __P((int why, void *arg)); 103 104 struct cfattach fxp_pci_ca = { 105 sizeof(struct fxp_pci_softc), fxp_pci_match, fxp_pci_attach 106 }; 107 108 const struct fxp_pci_product { 109 u_int32_t fpp_prodid; /* PCI product ID */ 110 const char *fpp_name; /* device name */ 111 } fxp_pci_products[] = { 112 { PCI_PRODUCT_INTEL_82557, 113 "Intel i82557 Ethernet" }, 114 { PCI_PRODUCT_INTEL_82559ER, 115 "Intel i82559ER Ethernet" }, 116 { PCI_PRODUCT_INTEL_IN_BUSINESS, 117 "Intel InBusiness Ethernet" }, 118 { PCI_PRODUCT_INTEL_82801BA_LAN, 119 "Intel i82562 Ethernet" }, 120 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 121 "Intel PRO/100 VE Network Controller" }, 122 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 123 "Intel PRO/100 VE Network Controller" }, 124 { 0, 125 NULL }, 126 }; 127 128 static const struct fxp_pci_product * 129 fxp_pci_lookup(const struct pci_attach_args *pa) 130 { 131 const struct fxp_pci_product *fpp; 132 133 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 134 return (NULL); 135 136 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 137 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 138 return (fpp); 139 140 return (NULL); 141 } 142 143 int 144 fxp_pci_match(parent, match, aux) 145 struct device *parent; 146 struct cfdata *match; 147 void *aux; 148 { 149 struct pci_attach_args *pa = aux; 150 151 if (fxp_pci_lookup(pa) != NULL) 152 return (1); 153 154 return (0); 155 } 156 157 /* 158 * Restore PCI configuration registers that may have been clobbered. 159 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 160 * ethernet, after an APM suspend/resume, as well as after an ACPI 161 * D3->D0 transition. We call this function from a power hook after 162 * APM resume events, as well as after the ACPI D3->D0 transition. 163 */ 164 static void 165 fxp_pci_confreg_restore(psc) 166 struct fxp_pci_softc *psc; 167 { 168 pcireg_t reg; 169 170 #if 0 171 /* 172 * Check to see if the command register is blank -- if so, then 173 * we'll assume that all the clobberable-registers have been 174 * clobbered. 175 */ 176 177 /* 178 * In general, the above metric is accurate. Unfortunately, 179 * it is inaccurate across a hibernation. Ideally APM/ACPI 180 * code should take note of hibernation events and execute 181 * a hibernation wakeup hook, but at present a hibernation wake 182 * is indistinguishable from a suspend wake. 183 */ 184 185 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 186 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 187 return; 188 #else 189 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 190 #endif 191 192 pci_conf_write(psc->psc_pc, psc->psc_tag, 193 PCI_COMMAND_STATUS_REG, 194 (reg & 0xffff0000) | 195 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 196 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 197 psc->psc_regs[PCI_BHLC_REG>>2]); 198 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 199 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 200 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 201 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 202 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 203 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 204 } 205 206 207 /* 208 * Power handler routine. Called when the system is transitioning into/out 209 * of power save modes. We restore the (bashed) PCI configuration registers 210 * on a resume. 211 */ 212 static void 213 fxp_pci_power(why, arg) 214 int why; 215 void *arg; 216 { 217 struct fxp_pci_softc *psc = arg; 218 219 if (why == PWR_RESUME) 220 fxp_pci_confreg_restore(psc); 221 } 222 223 void 224 fxp_pci_attach(parent, self, aux) 225 struct device *parent, *self; 226 void *aux; 227 { 228 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 229 struct fxp_softc *sc = (struct fxp_softc *)self; 230 struct pci_attach_args *pa = aux; 231 pci_chipset_tag_t pc = pa->pa_pc; 232 pci_intr_handle_t ih; 233 const struct fxp_pci_product *fpp; 234 const char *intrstr = NULL; 235 bus_space_tag_t iot, memt; 236 bus_space_handle_t ioh, memh; 237 int ioh_valid, memh_valid; 238 bus_addr_t addr; 239 bus_size_t size; 240 int flags; 241 int pci_pwrmgmt_cap_reg; 242 243 /* 244 * Map control/status registers. 245 */ 246 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 247 PCI_MAPREG_TYPE_IO, 0, 248 &iot, &ioh, NULL, NULL) == 0); 249 250 /* 251 * Version 2.1 of the PCI spec, page 196, "Address Maps": 252 * 253 * Prefetchable 254 * 255 * Set to one if there are no side effects on reads, the 256 * device returns all bytes regardless of the byte enables, 257 * and host bridges can merge processor writes into this 258 * range without causing errors. Bit must be set to zero 259 * otherwise. 260 * 261 * The 82557 incorrectly sets the "prefetchable" bit, resulting 262 * in errors on systems which will do merged reads and writes. 263 * These errors manifest themselves as all-bits-set when reading 264 * from the EEPROM or other < 4 byte registers. 265 * 266 * We must work around this problem by always forcing the mapping 267 * for memory space to be uncacheable. On systems which cannot 268 * create an uncacheable mapping (because the firmware mapped it 269 * into only cacheable/prefetchable space due to the "prefetchable" 270 * bit), we can fall back onto i/o mapped access. 271 */ 272 memh_valid = 0; 273 memt = pa->pa_memt; 274 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 275 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 276 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 277 &addr, &size, &flags) == 0) { 278 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 279 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 280 memh_valid = 1; 281 } 282 283 if (memh_valid) { 284 sc->sc_st = memt; 285 sc->sc_sh = memh; 286 } else if (ioh_valid) { 287 sc->sc_st = iot; 288 sc->sc_sh = ioh; 289 } else { 290 printf(": unable to map device registers\n"); 291 return; 292 } 293 294 sc->sc_dmat = pa->pa_dmat; 295 296 fpp = fxp_pci_lookup(pa); 297 if (fpp == NULL) { 298 printf("\n"); 299 panic("fxp_pci_attach: impossible"); 300 } 301 302 sc->sc_rev = PCI_REVISION(pa->pa_class); 303 304 switch (fpp->fpp_prodid) { 305 case PCI_PRODUCT_INTEL_82557: 306 case PCI_PRODUCT_INTEL_82559ER: 307 case PCI_PRODUCT_INTEL_IN_BUSINESS: 308 { 309 const char *chipname = NULL; 310 311 if (sc->sc_rev >= FXP_REV_82558_A4) { 312 chipname = "i82558 Ethernet"; 313 /* 314 * Enable the MWI command for memory writes. 315 */ 316 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 317 sc->sc_flags |= FXPF_MWI; 318 } 319 if (sc->sc_rev >= FXP_REV_82559_A0) 320 chipname = "i82559 Ethernet"; 321 if (sc->sc_rev >= FXP_REV_82559S_A) 322 chipname = "i82559S Ethernet"; 323 if (sc->sc_rev >= FXP_REV_82550) 324 chipname = "i82550 Ethernet"; 325 326 /* 327 * Mark all i82559 and i82550 revisions as having 328 * the "resume bug". See i82557.c for details. 329 */ 330 if (sc->sc_rev >= FXP_REV_82559_A0) 331 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 332 333 printf(": %s, rev %d\n", chipname != NULL ? chipname : 334 fpp->fpp_name, sc->sc_rev); 335 break; 336 } 337 338 case PCI_PRODUCT_INTEL_82801BA_LAN: 339 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 340 341 /* 342 * The 82801BA Ethernet has a bug which requires us to send a 343 * NOP before a CU_RESUME if we're in 10baseT mode. 344 */ 345 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 346 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 347 break; 348 349 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 350 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 351 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 352 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 353 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 354 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 355 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 356 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 357 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 358 359 /* 360 * ICH3 chips apparently have problems with the enhanced 361 * features, so just treat them as an i82557. It also 362 * has the resume bug that the ICH2 has. 363 */ 364 sc->sc_rev = 1; 365 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 366 break; 367 } 368 369 /* Make sure bus-mastering is enabled. */ 370 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 371 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 372 PCI_COMMAND_MASTER_ENABLE); 373 374 /* 375 * Under some circumstances (such as APM suspend/resume 376 * cycles, and across ACPI power state changes), the 377 * i82257-family can lose the contents of critical PCI 378 * configuration registers, causing the card to be 379 * non-responsive and useless. This occurs on the Sony VAIO 380 * Z505-series, among others. Preserve them here so they can 381 * be later restored (by fxp_pci_confreg_restore()). 382 */ 383 psc->psc_pc = pc; 384 psc->psc_tag = pa->pa_tag; 385 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 386 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 387 psc->psc_regs[PCI_BHLC_REG>>2] = 388 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 389 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 390 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 391 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 392 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 393 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 394 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 395 396 /* 397 * Work around BIOS ACPI bugs where the chip is inadvertantly 398 * left in ACPI D3 (lowest power state). First confirm the device 399 * supports ACPI power management, then move it to the D0 (fully 400 * functional) state if it is not already there. 401 */ 402 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 403 &pci_pwrmgmt_cap_reg, 0)) { 404 pcireg_t reg; 405 406 sc->sc_enable = fxp_pci_enable; 407 sc->sc_disable = fxp_pci_disable; 408 409 psc->psc_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 410 reg = pci_conf_read(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg); 411 psc->psc_pwrmgmt_csr = (reg & ~PCI_PMCSR_STATE_MASK) | 412 PCI_PMCSR_STATE_D0; 413 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) 414 pci_conf_write(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg, 415 psc->psc_pwrmgmt_csr); 416 } 417 /* Restore PCI configuration registers. */ 418 fxp_pci_confreg_restore(psc); 419 420 sc->sc_enabled = 1; 421 422 /* 423 * Map and establish our interrupt. 424 */ 425 if (pci_intr_map(pa, &ih)) { 426 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 427 return; 428 } 429 intrstr = pci_intr_string(pc, ih); 430 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 431 if (sc->sc_ih == NULL) { 432 printf("%s: couldn't establish interrupt", 433 sc->sc_dev.dv_xname); 434 if (intrstr != NULL) 435 printf(" at %s", intrstr); 436 printf("\n"); 437 return; 438 } 439 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 440 441 /* Finish off the attach. */ 442 fxp_attach(sc); 443 if (sc->sc_disable != NULL) 444 fxp_disable(sc); 445 446 /* Add a suspend hook to restore PCI config state */ 447 psc->psc_powerhook = powerhook_establish(fxp_pci_power, psc); 448 if (psc->psc_powerhook == NULL) 449 printf ("%s: WARNING: unable to establish pci power hook\n", 450 sc->sc_dev.dv_xname); 451 } 452 453 int 454 fxp_pci_enable(struct fxp_softc *sc) 455 { 456 struct fxp_pci_softc *psc = (void *) sc; 457 458 #if 0 459 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 460 #endif 461 462 /* Bring the device into D0 power state. */ 463 pci_conf_write(psc->psc_pc, psc->psc_tag, 464 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 465 466 /* Now restore the configuration registers. */ 467 fxp_pci_confreg_restore(psc); 468 469 return (0); 470 } 471 472 void 473 fxp_pci_disable(struct fxp_softc *sc) 474 { 475 struct fxp_pci_softc *psc = (void *) sc; 476 477 #if 0 478 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 479 #endif 480 481 /* Put the device into D3 state. */ 482 pci_conf_write(psc->psc_pc, psc->psc_tag, 483 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 484 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 485 } 486