1 /* $NetBSD: if_fxp_pci.c,v 1.29 2002/10/02 16:51:24 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.29 2002/10/02 16:51:24 thorpej Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <machine/bus.h> 72 #include <machine/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 void *psc_powerhook; /* power hook */ 90 91 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 92 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 93 }; 94 95 int fxp_pci_match __P((struct device *, struct cfdata *, void *)); 96 void fxp_pci_attach __P((struct device *, struct device *, void *)); 97 98 int fxp_pci_enable __P((struct fxp_softc *)); 99 void fxp_pci_disable __P((struct fxp_softc *)); 100 101 static void fxp_pci_confreg_restore __P((struct fxp_pci_softc *psc)); 102 static void fxp_pci_power __P((int why, void *arg)); 103 104 CFATTACH_DECL(fxp_pci, sizeof(struct fxp_pci_softc), 105 fxp_pci_match, fxp_pci_attach, NULL, NULL); 106 107 const struct fxp_pci_product { 108 u_int32_t fpp_prodid; /* PCI product ID */ 109 const char *fpp_name; /* device name */ 110 } fxp_pci_products[] = { 111 { PCI_PRODUCT_INTEL_82557, 112 "Intel i82557 Ethernet" }, 113 { PCI_PRODUCT_INTEL_82559ER, 114 "Intel i82559ER Ethernet" }, 115 { PCI_PRODUCT_INTEL_IN_BUSINESS, 116 "Intel InBusiness Ethernet" }, 117 { PCI_PRODUCT_INTEL_82801BA_LAN, 118 "Intel i82562 Ethernet" }, 119 { PCI_PRODUCT_INTEL_82801E_LAN_1, 120 "Intel i82559 Ethernet" }, 121 { PCI_PRODUCT_INTEL_82801E_LAN_2, 122 "Intel i82559 Ethernet" }, 123 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 124 "Intel PRO/100 VE Network Controller" }, 125 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 126 "Intel PRO/100 VE Network Controller" }, 127 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 128 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 129 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 130 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 131 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 132 "Intel PRO/100 VE (MOB) Network Controller" }, 133 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 134 "Intel PRO/100 VM Network Controller" }, 135 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 136 "Intel PRO/100 VM Network Controller" }, 137 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 138 "Intel PRO/100 VM Network Controller" }, 139 { 0, 140 NULL }, 141 }; 142 143 static const struct fxp_pci_product * 144 fxp_pci_lookup(const struct pci_attach_args *pa) 145 { 146 const struct fxp_pci_product *fpp; 147 148 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 149 return (NULL); 150 151 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 152 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 153 return (fpp); 154 155 return (NULL); 156 } 157 158 int 159 fxp_pci_match(parent, match, aux) 160 struct device *parent; 161 struct cfdata *match; 162 void *aux; 163 { 164 struct pci_attach_args *pa = aux; 165 166 if (fxp_pci_lookup(pa) != NULL) 167 return (1); 168 169 return (0); 170 } 171 172 /* 173 * Restore PCI configuration registers that may have been clobbered. 174 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 175 * ethernet, after an APM suspend/resume, as well as after an ACPI 176 * D3->D0 transition. We call this function from a power hook after 177 * APM resume events, as well as after the ACPI D3->D0 transition. 178 */ 179 static void 180 fxp_pci_confreg_restore(psc) 181 struct fxp_pci_softc *psc; 182 { 183 pcireg_t reg; 184 185 #if 0 186 /* 187 * Check to see if the command register is blank -- if so, then 188 * we'll assume that all the clobberable-registers have been 189 * clobbered. 190 */ 191 192 /* 193 * In general, the above metric is accurate. Unfortunately, 194 * it is inaccurate across a hibernation. Ideally APM/ACPI 195 * code should take note of hibernation events and execute 196 * a hibernation wakeup hook, but at present a hibernation wake 197 * is indistinguishable from a suspend wake. 198 */ 199 200 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 201 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 202 return; 203 #else 204 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 205 #endif 206 207 pci_conf_write(psc->psc_pc, psc->psc_tag, 208 PCI_COMMAND_STATUS_REG, 209 (reg & 0xffff0000) | 210 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 211 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 212 psc->psc_regs[PCI_BHLC_REG>>2]); 213 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 214 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 215 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 216 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 217 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 218 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 219 } 220 221 222 /* 223 * Power handler routine. Called when the system is transitioning into/out 224 * of power save modes. We restore the (bashed) PCI configuration registers 225 * on a resume. 226 */ 227 static void 228 fxp_pci_power(why, arg) 229 int why; 230 void *arg; 231 { 232 struct fxp_pci_softc *psc = arg; 233 234 if (why == PWR_RESUME) 235 fxp_pci_confreg_restore(psc); 236 } 237 238 void 239 fxp_pci_attach(parent, self, aux) 240 struct device *parent, *self; 241 void *aux; 242 { 243 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 244 struct fxp_softc *sc = (struct fxp_softc *)self; 245 struct pci_attach_args *pa = aux; 246 pci_chipset_tag_t pc = pa->pa_pc; 247 pci_intr_handle_t ih; 248 const struct fxp_pci_product *fpp; 249 const char *intrstr = NULL; 250 bus_space_tag_t iot, memt; 251 bus_space_handle_t ioh, memh; 252 int ioh_valid, memh_valid; 253 bus_addr_t addr; 254 bus_size_t size; 255 int flags; 256 int pci_pwrmgmt_cap_reg; 257 258 /* 259 * Map control/status registers. 260 */ 261 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 262 PCI_MAPREG_TYPE_IO, 0, 263 &iot, &ioh, NULL, NULL) == 0); 264 265 /* 266 * Version 2.1 of the PCI spec, page 196, "Address Maps": 267 * 268 * Prefetchable 269 * 270 * Set to one if there are no side effects on reads, the 271 * device returns all bytes regardless of the byte enables, 272 * and host bridges can merge processor writes into this 273 * range without causing errors. Bit must be set to zero 274 * otherwise. 275 * 276 * The 82557 incorrectly sets the "prefetchable" bit, resulting 277 * in errors on systems which will do merged reads and writes. 278 * These errors manifest themselves as all-bits-set when reading 279 * from the EEPROM or other < 4 byte registers. 280 * 281 * We must work around this problem by always forcing the mapping 282 * for memory space to be uncacheable. On systems which cannot 283 * create an uncacheable mapping (because the firmware mapped it 284 * into only cacheable/prefetchable space due to the "prefetchable" 285 * bit), we can fall back onto i/o mapped access. 286 */ 287 memh_valid = 0; 288 memt = pa->pa_memt; 289 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 290 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 291 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 292 &addr, &size, &flags) == 0) { 293 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 294 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 295 memh_valid = 1; 296 } 297 298 if (memh_valid) { 299 sc->sc_st = memt; 300 sc->sc_sh = memh; 301 } else if (ioh_valid) { 302 sc->sc_st = iot; 303 sc->sc_sh = ioh; 304 } else { 305 printf(": unable to map device registers\n"); 306 return; 307 } 308 309 sc->sc_dmat = pa->pa_dmat; 310 311 fpp = fxp_pci_lookup(pa); 312 if (fpp == NULL) { 313 printf("\n"); 314 panic("fxp_pci_attach: impossible"); 315 } 316 317 sc->sc_rev = PCI_REVISION(pa->pa_class); 318 319 switch (fpp->fpp_prodid) { 320 case PCI_PRODUCT_INTEL_82557: 321 case PCI_PRODUCT_INTEL_82559ER: 322 case PCI_PRODUCT_INTEL_IN_BUSINESS: 323 { 324 const char *chipname = NULL; 325 326 if (sc->sc_rev >= FXP_REV_82558_A4) { 327 chipname = "i82558 Ethernet"; 328 /* 329 * Enable the MWI command for memory writes. 330 */ 331 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 332 sc->sc_flags |= FXPF_MWI; 333 } 334 if (sc->sc_rev >= FXP_REV_82559_A0) 335 chipname = "i82559 Ethernet"; 336 if (sc->sc_rev >= FXP_REV_82559S_A) 337 chipname = "i82559S Ethernet"; 338 if (sc->sc_rev >= FXP_REV_82550) 339 chipname = "i82550 Ethernet"; 340 341 /* 342 * Mark all i82559 and i82550 revisions as having 343 * the "resume bug". See i82557.c for details. 344 */ 345 if (sc->sc_rev >= FXP_REV_82559_A0) 346 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 347 348 printf(": %s, rev %d\n", chipname != NULL ? chipname : 349 fpp->fpp_name, sc->sc_rev); 350 break; 351 } 352 353 case PCI_PRODUCT_INTEL_82801BA_LAN: 354 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 355 356 /* 357 * The 82801BA Ethernet has a bug which requires us to send a 358 * NOP before a CU_RESUME if we're in 10baseT mode. 359 */ 360 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 361 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 362 break; 363 364 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 365 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 366 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 367 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 368 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 369 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 370 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 371 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 372 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 373 374 /* 375 * ICH3 chips apparently have problems with the enhanced 376 * features, so just treat them as an i82557. It also 377 * has the resume bug that the ICH2 has. 378 */ 379 sc->sc_rev = 1; 380 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 381 break; 382 case PCI_PRODUCT_INTEL_82801E_LAN_1: 383 case PCI_PRODUCT_INTEL_82801E_LAN_2: 384 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 385 386 /* 387 * XXX We have to read the C-ICH's developer's manual 388 * in detail 389 */ 390 break; 391 } 392 393 /* Make sure bus-mastering is enabled. */ 394 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 395 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 396 PCI_COMMAND_MASTER_ENABLE); 397 398 /* 399 * Under some circumstances (such as APM suspend/resume 400 * cycles, and across ACPI power state changes), the 401 * i82257-family can lose the contents of critical PCI 402 * configuration registers, causing the card to be 403 * non-responsive and useless. This occurs on the Sony VAIO 404 * Z505-series, among others. Preserve them here so they can 405 * be later restored (by fxp_pci_confreg_restore()). 406 */ 407 psc->psc_pc = pc; 408 psc->psc_tag = pa->pa_tag; 409 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 410 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 411 psc->psc_regs[PCI_BHLC_REG>>2] = 412 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 413 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 414 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 415 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 416 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 417 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 418 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 419 420 /* 421 * Work around BIOS ACPI bugs where the chip is inadvertantly 422 * left in ACPI D3 (lowest power state). First confirm the device 423 * supports ACPI power management, then move it to the D0 (fully 424 * functional) state if it is not already there. 425 */ 426 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 427 &pci_pwrmgmt_cap_reg, 0)) { 428 pcireg_t reg; 429 430 sc->sc_enable = fxp_pci_enable; 431 sc->sc_disable = fxp_pci_disable; 432 433 psc->psc_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 434 reg = pci_conf_read(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg); 435 psc->psc_pwrmgmt_csr = (reg & ~PCI_PMCSR_STATE_MASK) | 436 PCI_PMCSR_STATE_D0; 437 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) 438 pci_conf_write(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg, 439 psc->psc_pwrmgmt_csr); 440 } 441 /* Restore PCI configuration registers. */ 442 fxp_pci_confreg_restore(psc); 443 444 sc->sc_enabled = 1; 445 446 /* 447 * Map and establish our interrupt. 448 */ 449 if (pci_intr_map(pa, &ih)) { 450 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 451 return; 452 } 453 intrstr = pci_intr_string(pc, ih); 454 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 455 if (sc->sc_ih == NULL) { 456 printf("%s: couldn't establish interrupt", 457 sc->sc_dev.dv_xname); 458 if (intrstr != NULL) 459 printf(" at %s", intrstr); 460 printf("\n"); 461 return; 462 } 463 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 464 465 /* Finish off the attach. */ 466 fxp_attach(sc); 467 if (sc->sc_disable != NULL) 468 fxp_disable(sc); 469 470 /* Add a suspend hook to restore PCI config state */ 471 psc->psc_powerhook = powerhook_establish(fxp_pci_power, psc); 472 if (psc->psc_powerhook == NULL) 473 printf ("%s: WARNING: unable to establish pci power hook\n", 474 sc->sc_dev.dv_xname); 475 } 476 477 int 478 fxp_pci_enable(struct fxp_softc *sc) 479 { 480 struct fxp_pci_softc *psc = (void *) sc; 481 482 #if 0 483 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 484 #endif 485 486 /* Bring the device into D0 power state. */ 487 pci_conf_write(psc->psc_pc, psc->psc_tag, 488 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 489 490 /* Now restore the configuration registers. */ 491 fxp_pci_confreg_restore(psc); 492 493 return (0); 494 } 495 496 void 497 fxp_pci_disable(struct fxp_softc *sc) 498 { 499 struct fxp_pci_softc *psc = (void *) sc; 500 501 /* 502 * for some 82558_A4 and 82558_B0, entering D3 state makes 503 * media detection disordered. 504 */ 505 if (sc->sc_rev <= FXP_REV_82558_B0) 506 return; 507 508 #if 0 509 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 510 #endif 511 512 /* Put the device into D3 state. */ 513 pci_conf_write(psc->psc_pc, psc->psc_tag, 514 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 515 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 516 } 517