1 /* $NetBSD: if_ipw.c,v 1.52 2010/11/15 05:57:07 uebayasi Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.52 2010/11/15 05:57:07 uebayasi Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 40 #include <sys/param.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/mbuf.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/conf.h> 49 #include <sys/proc.h> 50 51 #include <sys/bus.h> 52 #include <machine/endian.h> 53 #include <sys/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <net/bpf.h> 60 #include <net/if.h> 61 #include <net/if_arp.h> 62 #include <net/if_dl.h> 63 #include <net/if_ether.h> 64 #include <net/if_media.h> 65 #include <net/if_types.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 70 #include <netinet/in.h> 71 #include <netinet/in_systm.h> 72 #include <netinet/in_var.h> 73 #include <netinet/ip.h> 74 75 #include <dev/firmload.h> 76 77 #include <dev/pci/if_ipwreg.h> 78 #include <dev/pci/if_ipwvar.h> 79 80 #ifdef IPW_DEBUG 81 #define DPRINTF(x) if (ipw_debug > 0) printf x 82 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 83 int ipw_debug = 0; 84 #else 85 #define DPRINTF(x) 86 #define DPRINTFN(n, x) 87 #endif 88 89 /* Permit loading the Intel firmware */ 90 static int ipw_accept_eula; 91 92 static int ipw_dma_alloc(struct ipw_softc *); 93 static void ipw_release(struct ipw_softc *); 94 static int ipw_match(device_t, cfdata_t, void *); 95 static void ipw_attach(device_t, device_t, void *); 96 static int ipw_detach(device_t, int); 97 98 static int ipw_media_change(struct ifnet *); 99 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 100 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 101 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 102 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 103 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 104 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 105 struct ipw_soft_bd *, struct ipw_soft_buf *); 106 static void ipw_rx_intr(struct ipw_softc *); 107 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 108 static void ipw_tx_intr(struct ipw_softc *); 109 static int ipw_intr(void *); 110 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 111 static int ipw_tx_start(struct ifnet *, struct mbuf *, 112 struct ieee80211_node *); 113 static void ipw_start(struct ifnet *); 114 static void ipw_watchdog(struct ifnet *); 115 static int ipw_ioctl(struct ifnet *, u_long, void *); 116 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 117 static int ipw_get_radio(struct ipw_softc *, int *); 118 static void ipw_stop_master(struct ipw_softc *); 119 static int ipw_reset(struct ipw_softc *); 120 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 121 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 122 static int ipw_cache_firmware(struct ipw_softc *); 123 static void ipw_free_firmware(struct ipw_softc *); 124 static int ipw_config(struct ipw_softc *); 125 static int ipw_init(struct ifnet *); 126 static void ipw_stop(struct ifnet *, int); 127 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 128 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 129 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 130 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 131 bus_size_t); 132 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 133 bus_size_t); 134 135 /* 136 * Supported rates for 802.11b mode (in 500Kbps unit). 137 */ 138 static const struct ieee80211_rateset ipw_rateset_11b = 139 { 4, { 2, 4, 11, 22 } }; 140 141 static inline uint8_t 142 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 143 { 144 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 145 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 146 } 147 148 static inline uint32_t 149 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 150 { 151 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 152 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 153 } 154 155 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 156 ipw_detach, NULL); 157 158 static int 159 ipw_match(device_t parent, cfdata_t match, void *aux) 160 { 161 struct pci_attach_args *pa = aux; 162 163 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 164 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 165 return 1; 166 167 return 0; 168 } 169 170 /* Base Address Register */ 171 #define IPW_PCI_BAR0 0x10 172 173 static void 174 ipw_attach(device_t parent, device_t self, void *aux) 175 { 176 struct ipw_softc *sc = device_private(self); 177 struct ieee80211com *ic = &sc->sc_ic; 178 struct ifnet *ifp = &sc->sc_if; 179 struct pci_attach_args *pa = aux; 180 const char *intrstr; 181 char devinfo[256]; 182 bus_space_tag_t memt; 183 bus_space_handle_t memh; 184 bus_addr_t base; 185 pci_intr_handle_t ih; 186 uint32_t data; 187 uint16_t val; 188 int i, revision, error; 189 190 sc->sc_pct = pa->pa_pc; 191 sc->sc_pcitag = pa->pa_tag; 192 193 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 194 revision = PCI_REVISION(pa->pa_class); 195 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 196 197 /* enable bus-mastering */ 198 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 199 data |= PCI_COMMAND_MASTER_ENABLE; 200 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 201 202 /* map the register window */ 203 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 204 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 205 if (error != 0) { 206 aprint_error_dev(&sc->sc_dev, "could not map memory space\n"); 207 return; 208 } 209 210 sc->sc_st = memt; 211 sc->sc_sh = memh; 212 sc->sc_dmat = pa->pa_dmat; 213 sc->sc_fwname = "ipw2100-1.2.fw"; 214 215 /* disable interrupts */ 216 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 217 218 if (pci_intr_map(pa, &ih) != 0) { 219 aprint_error_dev(&sc->sc_dev, "could not map interrupt\n"); 220 return; 221 } 222 223 intrstr = pci_intr_string(sc->sc_pct, ih); 224 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 225 if (sc->sc_ih == NULL) { 226 aprint_error_dev(&sc->sc_dev, "could not establish interrupt"); 227 if (intrstr != NULL) 228 aprint_error(" at %s", intrstr); 229 aprint_error("\n"); 230 return; 231 } 232 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 233 234 if (ipw_reset(sc) != 0) { 235 aprint_error_dev(&sc->sc_dev, "could not reset adapter\n"); 236 goto fail; 237 } 238 239 if (ipw_dma_alloc(sc) != 0) { 240 aprint_error_dev(&sc->sc_dev, "could not allocate DMA resources\n"); 241 goto fail; 242 } 243 244 ifp->if_softc = sc; 245 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 246 ifp->if_init = ipw_init; 247 ifp->if_stop = ipw_stop; 248 ifp->if_ioctl = ipw_ioctl; 249 ifp->if_start = ipw_start; 250 ifp->if_watchdog = ipw_watchdog; 251 IFQ_SET_READY(&ifp->if_snd); 252 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 253 254 ic->ic_ifp = ifp; 255 ic->ic_phytype = IEEE80211_T_DS; 256 ic->ic_opmode = IEEE80211_M_STA; 257 ic->ic_state = IEEE80211_S_INIT; 258 259 /* set device capabilities */ 260 ic->ic_caps = 261 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 262 | IEEE80211_C_TXPMGT /* tx power management */ 263 | IEEE80211_C_IBSS /* ibss mode */ 264 | IEEE80211_C_MONITOR /* monitor mode */ 265 ; 266 267 /* read MAC address from EEPROM */ 268 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 269 ic->ic_myaddr[0] = val >> 8; 270 ic->ic_myaddr[1] = val & 0xff; 271 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 272 ic->ic_myaddr[2] = val >> 8; 273 ic->ic_myaddr[3] = val & 0xff; 274 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 275 ic->ic_myaddr[4] = val >> 8; 276 ic->ic_myaddr[5] = val & 0xff; 277 278 /* set supported .11b rates */ 279 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 280 281 /* set supported .11b channels (read from EEPROM) */ 282 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 283 val = 0x7ff; /* default to channels 1-11 */ 284 val <<= 1; 285 for (i = 1; i < 16; i++) { 286 if (val & (1 << i)) { 287 ic->ic_channels[i].ic_freq = 288 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 289 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 290 } 291 } 292 293 /* check support for radio transmitter switch in EEPROM */ 294 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 295 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 296 297 aprint_normal_dev(&sc->sc_dev, "802.11 address %s\n", 298 ether_sprintf(ic->ic_myaddr)); 299 300 if_attach(ifp); 301 ieee80211_ifattach(ic); 302 303 /* override state transition machine */ 304 sc->sc_newstate = ic->ic_newstate; 305 ic->ic_newstate = ipw_newstate; 306 307 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 308 309 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 310 sizeof(struct ieee80211_frame) + 64, &sc->sc_drvbpf); 311 312 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 313 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 314 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 315 316 sc->sc_txtap_len = sizeof sc->sc_txtapu; 317 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 318 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 319 320 /* 321 * Add a few sysctl knobs. 322 * XXX: Not yet 323 */ 324 sc->dwelltime = 100; 325 326 if (pmf_device_register(self, NULL, NULL)) 327 pmf_class_network_register(self, ifp); 328 else 329 aprint_error_dev(self, "couldn't establish power handler\n"); 330 331 ieee80211_announce(ic); 332 333 return; 334 335 fail: ipw_detach(self, 0); 336 } 337 338 static int 339 ipw_detach(struct device* self, int flags) 340 { 341 struct ipw_softc *sc = device_private(self); 342 struct ifnet *ifp = &sc->sc_if; 343 344 if (ifp->if_softc) { 345 ipw_stop(ifp, 1); 346 ipw_free_firmware(sc); 347 348 bpf_detach(ifp); 349 ieee80211_ifdetach(&sc->sc_ic); 350 if_detach(ifp); 351 352 ipw_release(sc); 353 } 354 355 if (sc->sc_ih != NULL) { 356 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 357 sc->sc_ih = NULL; 358 } 359 360 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 361 362 return 0; 363 } 364 365 static int 366 ipw_dma_alloc(struct ipw_softc *sc) 367 { 368 struct ipw_soft_bd *sbd; 369 struct ipw_soft_hdr *shdr; 370 struct ipw_soft_buf *sbuf; 371 int error, i, nsegs; 372 373 /* 374 * Allocate and map tx ring. 375 */ 376 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 377 BUS_DMA_NOWAIT, &sc->tbd_map); 378 if (error != 0) { 379 aprint_error_dev(&sc->sc_dev, "could not create tbd dma map\n"); 380 goto fail; 381 } 382 383 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 384 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 385 if (error != 0) { 386 aprint_error_dev(&sc->sc_dev, "could not allocate tbd dma memory\n"); 387 goto fail; 388 } 389 390 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 391 (void **)&sc->tbd_list, BUS_DMA_NOWAIT); 392 if (error != 0) { 393 aprint_error_dev(&sc->sc_dev, "could not map tbd dma memory\n"); 394 goto fail; 395 } 396 397 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 398 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 399 if (error != 0) { 400 aprint_error_dev(&sc->sc_dev, "could not load tbd dma memory\n"); 401 goto fail; 402 } 403 404 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 405 406 /* 407 * Allocate and map rx ring. 408 */ 409 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 410 BUS_DMA_NOWAIT, &sc->rbd_map); 411 if (error != 0) { 412 aprint_error_dev(&sc->sc_dev, "could not create rbd dma map\n"); 413 goto fail; 414 } 415 416 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 417 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 418 if (error != 0) { 419 aprint_error_dev(&sc->sc_dev, "could not allocate rbd dma memory\n"); 420 goto fail; 421 } 422 423 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 424 (void **)&sc->rbd_list, BUS_DMA_NOWAIT); 425 if (error != 0) { 426 aprint_error_dev(&sc->sc_dev, "could not map rbd dma memory\n"); 427 goto fail; 428 } 429 430 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 431 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 432 if (error != 0) { 433 aprint_error_dev(&sc->sc_dev, "could not load rbd dma memory\n"); 434 goto fail; 435 } 436 437 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 438 439 /* 440 * Allocate and map status ring. 441 */ 442 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 443 0, BUS_DMA_NOWAIT, &sc->status_map); 444 if (error != 0) { 445 aprint_error_dev(&sc->sc_dev, "could not create status dma map\n"); 446 goto fail; 447 } 448 449 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 450 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 451 if (error != 0) { 452 aprint_error_dev(&sc->sc_dev, "could not allocate status dma memory\n"); 453 goto fail; 454 } 455 456 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 457 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT); 458 if (error != 0) { 459 aprint_error_dev(&sc->sc_dev, "could not map status dma memory\n"); 460 goto fail; 461 } 462 463 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 464 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 465 if (error != 0) { 466 aprint_error_dev(&sc->sc_dev, "could not load status dma memory\n"); 467 goto fail; 468 } 469 470 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 471 472 /* 473 * Allocate command DMA map. 474 */ 475 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 476 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 477 if (error != 0) { 478 aprint_error_dev(&sc->sc_dev, "could not create cmd dma map\n"); 479 goto fail; 480 } 481 482 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 483 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 484 if (error != 0) { 485 aprint_error_dev(&sc->sc_dev, "could not allocate cmd dma memory\n"); 486 goto fail; 487 } 488 489 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 490 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT); 491 if (error != 0) { 492 aprint_error_dev(&sc->sc_dev, "could not map cmd dma memory\n"); 493 goto fail; 494 } 495 496 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 497 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 498 if (error != 0) { 499 aprint_error_dev(&sc->sc_dev, "could not map cmd dma memory\n"); 500 return error; 501 } 502 503 /* 504 * Allocate and map hdr list. 505 */ 506 507 error = bus_dmamap_create(sc->sc_dmat, 508 IPW_NDATA * sizeof(struct ipw_hdr), 1, 509 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 510 &sc->hdr_map); 511 if (error != 0) { 512 aprint_error_dev(&sc->sc_dev, "could not create hdr dma map\n"); 513 goto fail; 514 } 515 516 error = bus_dmamem_alloc(sc->sc_dmat, 517 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 518 1, &nsegs, BUS_DMA_NOWAIT); 519 if (error != 0) { 520 aprint_error_dev(&sc->sc_dev, "could not allocate hdr memory\n"); 521 goto fail; 522 } 523 524 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 525 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list, 526 BUS_DMA_NOWAIT); 527 if (error != 0) { 528 aprint_error_dev(&sc->sc_dev, "could not map hdr memory\n"); 529 goto fail; 530 } 531 532 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 533 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 534 if (error != 0) { 535 aprint_error_dev(&sc->sc_dev, "could not load hdr memory\n"); 536 goto fail; 537 } 538 539 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 540 541 /* 542 * Create DMA hdrs tailq. 543 */ 544 TAILQ_INIT(&sc->sc_free_shdr); 545 for (i = 0; i < IPW_NDATA; i++) { 546 shdr = &sc->shdr_list[i]; 547 shdr->hdr = sc->hdr_list + i; 548 shdr->offset = sizeof(struct ipw_hdr) * i; 549 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 550 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 551 } 552 553 /* 554 * Allocate tx buffers DMA maps. 555 */ 556 TAILQ_INIT(&sc->sc_free_sbuf); 557 for (i = 0; i < IPW_NDATA; i++) { 558 sbuf = &sc->tx_sbuf_list[i]; 559 560 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 561 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 562 if (error != 0) { 563 aprint_error_dev(&sc->sc_dev, "could not create txbuf dma map\n"); 564 goto fail; 565 } 566 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 567 } 568 569 /* 570 * Initialize tx ring. 571 */ 572 for (i = 0; i < IPW_NTBD; i++) { 573 sbd = &sc->stbd_list[i]; 574 sbd->bd = &sc->tbd_list[i]; 575 sbd->type = IPW_SBD_TYPE_NOASSOC; 576 } 577 578 /* 579 * Pre-allocate rx buffers and DMA maps 580 */ 581 for (i = 0; i < IPW_NRBD; i++) { 582 sbd = &sc->srbd_list[i]; 583 sbuf = &sc->rx_sbuf_list[i]; 584 sbd->bd = &sc->rbd_list[i]; 585 586 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 587 if (sbuf->m == NULL) { 588 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf\n"); 589 error = ENOMEM; 590 goto fail; 591 } 592 593 MCLGET(sbuf->m, M_DONTWAIT); 594 if (!(sbuf->m->m_flags & M_EXT)) { 595 m_freem(sbuf->m); 596 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf cluster\n"); 597 error = ENOMEM; 598 goto fail; 599 } 600 601 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 602 603 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 604 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 605 if (error != 0) { 606 aprint_error_dev(&sc->sc_dev, "could not create rxbuf dma map\n"); 607 m_freem(sbuf->m); 608 goto fail; 609 } 610 611 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 612 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 613 if (error != 0) { 614 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 615 m_freem(sbuf->m); 616 aprint_error_dev(&sc->sc_dev, "could not map rxbuf dma memory\n"); 617 goto fail; 618 } 619 620 sbd->type = IPW_SBD_TYPE_DATA; 621 sbd->priv = sbuf; 622 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 623 sbd->bd->len = htole32(MCLBYTES); 624 625 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 626 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 627 628 } 629 630 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 631 BUS_DMASYNC_PREREAD); 632 633 return 0; 634 635 fail: ipw_release(sc); 636 return error; 637 } 638 639 static void 640 ipw_release(struct ipw_softc *sc) 641 { 642 struct ipw_soft_buf *sbuf; 643 int i; 644 645 if (sc->tbd_map != NULL) { 646 if (sc->tbd_list != NULL) { 647 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 648 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list, 649 IPW_TBD_SZ); 650 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 651 } 652 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 653 } 654 655 if (sc->rbd_map != NULL) { 656 if (sc->rbd_list != NULL) { 657 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 658 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list, 659 IPW_RBD_SZ); 660 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 661 } 662 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 663 } 664 665 if (sc->status_map != NULL) { 666 if (sc->status_list != NULL) { 667 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 668 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list, 669 IPW_RBD_SZ); 670 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 671 } 672 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 673 } 674 675 for (i = 0; i < IPW_NTBD; i++) 676 ipw_release_sbd(sc, &sc->stbd_list[i]); 677 678 if (sc->cmd_map != NULL) 679 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 680 681 if (sc->hdr_list != NULL) { 682 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 683 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list, 684 IPW_NDATA * sizeof(struct ipw_hdr)); 685 } 686 if (sc->hdr_map != NULL) { 687 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 688 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 689 } 690 691 for (i = 0; i < IPW_NDATA; i++) 692 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 693 694 for (i = 0; i < IPW_NRBD; i++) { 695 sbuf = &sc->rx_sbuf_list[i]; 696 if (sbuf->map != NULL) { 697 if (sbuf->m != NULL) { 698 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 699 m_freem(sbuf->m); 700 } 701 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 702 } 703 } 704 705 } 706 707 static int 708 ipw_media_change(struct ifnet *ifp) 709 { 710 int error; 711 712 error = ieee80211_media_change(ifp); 713 if (error != ENETRESET) 714 return error; 715 716 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 717 ipw_init(ifp); 718 719 return 0; 720 } 721 722 /* 723 * The firmware automatically adapts the transmit speed. We report the current 724 * transmit speed here. 725 */ 726 static void 727 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 728 { 729 #define N(a) (sizeof (a) / sizeof (a[0])) 730 struct ipw_softc *sc = ifp->if_softc; 731 struct ieee80211com *ic = &sc->sc_ic; 732 static const struct { 733 uint32_t val; 734 int rate; 735 } rates[] = { 736 { IPW_RATE_DS1, 2 }, 737 { IPW_RATE_DS2, 4 }, 738 { IPW_RATE_DS5, 11 }, 739 { IPW_RATE_DS11, 22 }, 740 }; 741 uint32_t val; 742 int rate, i; 743 744 imr->ifm_status = IFM_AVALID; 745 imr->ifm_active = IFM_IEEE80211; 746 if (ic->ic_state == IEEE80211_S_RUN) 747 imr->ifm_status |= IFM_ACTIVE; 748 749 /* read current transmission rate from adapter */ 750 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 751 752 /* convert ipw rate to 802.11 rate */ 753 for (i = 0; i < N(rates) && rates[i].val != val; i++); 754 rate = (i < N(rates)) ? rates[i].rate : 0; 755 756 imr->ifm_active |= IFM_IEEE80211_11B; 757 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 758 switch (ic->ic_opmode) { 759 case IEEE80211_M_STA: 760 break; 761 762 case IEEE80211_M_IBSS: 763 imr->ifm_active |= IFM_IEEE80211_ADHOC; 764 break; 765 766 case IEEE80211_M_MONITOR: 767 imr->ifm_active |= IFM_IEEE80211_MONITOR; 768 break; 769 770 case IEEE80211_M_AHDEMO: 771 case IEEE80211_M_HOSTAP: 772 /* should not get there */ 773 break; 774 } 775 #undef N 776 } 777 778 static int 779 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 780 int arg) 781 { 782 struct ifnet *ifp = ic->ic_ifp; 783 struct ipw_softc *sc = ifp->if_softc; 784 struct ieee80211_node *ni; 785 uint8_t macaddr[IEEE80211_ADDR_LEN]; 786 uint32_t len; 787 struct ipw_rx_radiotap_header *wr = &sc->sc_rxtap; 788 struct ipw_tx_radiotap_header *wt = &sc->sc_txtap; 789 790 switch (nstate) { 791 case IEEE80211_S_INIT: 792 break; 793 default: 794 KASSERT(ic->ic_curchan != IEEE80211_CHAN_ANYC); 795 KASSERT(ic->ic_curchan != NULL); 796 wt->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 797 wt->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 798 wr->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 799 wr->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 800 break; 801 } 802 803 switch (nstate) { 804 case IEEE80211_S_RUN: 805 DELAY(200); /* firmware needs a short delay here */ 806 807 len = IEEE80211_ADDR_LEN; 808 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 809 810 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 811 if (ni == NULL) 812 break; 813 814 ieee80211_ref_node(ni); 815 ieee80211_sta_join(ic, ni); 816 ieee80211_node_authorize(ni); 817 818 if (ic->ic_opmode == IEEE80211_M_STA) 819 ieee80211_notify_node_join(ic, ni, 1); 820 break; 821 822 case IEEE80211_S_INIT: 823 case IEEE80211_S_SCAN: 824 case IEEE80211_S_AUTH: 825 case IEEE80211_S_ASSOC: 826 break; 827 } 828 829 ic->ic_state = nstate; 830 return 0; 831 } 832 833 /* 834 * Read 16 bits at address 'addr' from the serial EEPROM. 835 */ 836 static uint16_t 837 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 838 { 839 uint32_t tmp; 840 uint16_t val; 841 int n; 842 843 /* clock C once before the first command */ 844 IPW_EEPROM_CTL(sc, 0); 845 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 846 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 847 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 848 849 /* write start bit (1) */ 850 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 851 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 852 853 /* write READ opcode (10) */ 854 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 855 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 856 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 857 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 858 859 /* write address A7-A0 */ 860 for (n = 7; n >= 0; n--) { 861 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 862 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 863 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 864 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 865 } 866 867 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 868 869 /* read data Q15-Q0 */ 870 val = 0; 871 for (n = 15; n >= 0; n--) { 872 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 873 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 874 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 875 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 876 } 877 878 IPW_EEPROM_CTL(sc, 0); 879 880 /* clear Chip Select and clock C */ 881 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 882 IPW_EEPROM_CTL(sc, 0); 883 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 884 885 return le16toh(val); 886 } 887 888 static void 889 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 890 { 891 struct ipw_cmd *cmd; 892 893 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 894 BUS_DMASYNC_POSTREAD); 895 896 cmd = mtod(sbuf->m, struct ipw_cmd *); 897 898 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 899 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 900 le32toh(cmd->status))); 901 902 wakeup(&sc->cmd); 903 } 904 905 static void 906 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 907 { 908 struct ieee80211com *ic = &sc->sc_ic; 909 struct ifnet *ifp = sc->sc_ic.ic_ifp; 910 uint32_t state; 911 912 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 913 BUS_DMASYNC_POSTREAD); 914 915 state = le32toh(*mtod(sbuf->m, uint32_t *)); 916 917 DPRINTFN(2, ("entering state %u\n", state)); 918 919 switch (state) { 920 case IPW_STATE_ASSOCIATED: 921 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 922 break; 923 924 case IPW_STATE_SCANNING: 925 /* don't leave run state on background scan */ 926 if (ic->ic_state != IEEE80211_S_RUN) 927 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 928 929 ic->ic_flags |= IEEE80211_F_SCAN; 930 break; 931 932 case IPW_STATE_SCAN_COMPLETE: 933 ieee80211_notify_scan_done(ic); 934 ic->ic_flags &= ~IEEE80211_F_SCAN; 935 break; 936 937 case IPW_STATE_ASSOCIATION_LOST: 938 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 939 break; 940 941 case IPW_STATE_RADIO_DISABLED: 942 ic->ic_ifp->if_flags &= ~IFF_UP; 943 ipw_stop(ifp, 1); 944 break; 945 } 946 } 947 948 /* 949 * XXX: Hack to set the current channel to the value advertised in beacons or 950 * probe responses. Only used during AP detection. 951 */ 952 static void 953 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 954 { 955 struct ieee80211_frame *wh; 956 uint8_t subtype; 957 uint8_t *frm, *efrm; 958 959 wh = mtod(m, struct ieee80211_frame *); 960 961 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 962 return; 963 964 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 965 966 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 967 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 968 return; 969 970 frm = (uint8_t *)(wh + 1); 971 efrm = mtod(m, uint8_t *) + m->m_len; 972 973 frm += 12; /* skip tstamp, bintval and capinfo fields */ 974 while (frm < efrm) { 975 if (*frm == IEEE80211_ELEMID_DSPARMS) 976 #if IEEE80211_CHAN_MAX < 255 977 if (frm[2] <= IEEE80211_CHAN_MAX) 978 #endif 979 ic->ic_curchan = &ic->ic_channels[frm[2]]; 980 981 frm += frm[1] + 2; 982 } 983 } 984 985 static void 986 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 987 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 988 { 989 struct ieee80211com *ic = &sc->sc_ic; 990 struct ifnet *ifp = &sc->sc_if; 991 struct mbuf *mnew, *m; 992 struct ieee80211_frame *wh; 993 struct ieee80211_node *ni; 994 int error; 995 996 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 997 status->rssi)); 998 999 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1000 le32toh(status->len) > MCLBYTES) 1001 return; 1002 1003 /* 1004 * Try to allocate a new mbuf for this ring element and load it before 1005 * processing the current mbuf. If the ring element cannot be loaded, 1006 * drop the received packet and reuse the old mbuf. In the unlikely 1007 * case that the old mbuf can't be reloaded either, explicitly panic. 1008 */ 1009 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1010 if (mnew == NULL) { 1011 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf\n"); 1012 ifp->if_ierrors++; 1013 return; 1014 } 1015 1016 MCLGET(mnew, M_DONTWAIT); 1017 if (!(mnew->m_flags & M_EXT)) { 1018 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf cluster\n"); 1019 m_freem(mnew); 1020 ifp->if_ierrors++; 1021 return; 1022 } 1023 1024 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1025 1026 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1027 BUS_DMASYNC_POSTREAD); 1028 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1029 1030 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1031 BUS_DMA_READ | BUS_DMA_NOWAIT); 1032 if (error != 0) { 1033 aprint_error_dev(&sc->sc_dev, "could not load rx buf DMA map\n"); 1034 m_freem(mnew); 1035 1036 /* try to reload the old mbuf */ 1037 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1038 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1039 if (error != 0) { 1040 /* very unlikely that it will fail... */ 1041 panic("%s: unable to remap rx buf", 1042 device_xname(&sc->sc_dev)); 1043 } 1044 ifp->if_ierrors++; 1045 return; 1046 } 1047 1048 /* 1049 * New mbuf successfully loaded, update Rx ring and continue 1050 * processing. 1051 */ 1052 m = sbuf->m; 1053 sbuf->m = mnew; 1054 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1055 1056 /* finalize mbuf */ 1057 m->m_pkthdr.rcvif = ifp; 1058 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1059 1060 if (sc->sc_drvbpf != NULL) { 1061 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1062 1063 tap->wr_antsignal = status->rssi; 1064 1065 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1066 } 1067 1068 if (ic->ic_state == IEEE80211_S_SCAN) 1069 ipw_fix_channel(ic, m); 1070 1071 wh = mtod(m, struct ieee80211_frame *); 1072 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1073 1074 /* send the frame to the 802.11 layer */ 1075 ieee80211_input(ic, m, ni, status->rssi, 0); 1076 1077 /* node is no longer needed */ 1078 ieee80211_free_node(ni); 1079 1080 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1081 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1082 } 1083 1084 static void 1085 ipw_rx_intr(struct ipw_softc *sc) 1086 { 1087 struct ipw_status *status; 1088 struct ipw_soft_bd *sbd; 1089 struct ipw_soft_buf *sbuf; 1090 uint32_t r, i; 1091 1092 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1093 return; 1094 1095 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1096 1097 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1098 1099 /* firmware was killed, stop processing received frames */ 1100 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1101 return; 1102 1103 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1104 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1105 BUS_DMASYNC_POSTREAD); 1106 1107 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1108 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1109 BUS_DMASYNC_POSTREAD); 1110 1111 status = &sc->status_list[i]; 1112 sbd = &sc->srbd_list[i]; 1113 sbuf = sbd->priv; 1114 1115 switch (le16toh(status->code) & 0xf) { 1116 case IPW_STATUS_CODE_COMMAND: 1117 ipw_command_intr(sc, sbuf); 1118 break; 1119 1120 case IPW_STATUS_CODE_NEWSTATE: 1121 ipw_newstate_intr(sc, sbuf); 1122 break; 1123 1124 case IPW_STATUS_CODE_DATA_802_3: 1125 case IPW_STATUS_CODE_DATA_802_11: 1126 ipw_data_intr(sc, status, sbd, sbuf); 1127 break; 1128 1129 case IPW_STATUS_CODE_NOTIFICATION: 1130 DPRINTFN(2, ("received notification\n")); 1131 break; 1132 1133 default: 1134 aprint_error_dev(&sc->sc_dev, "unknown status code %u\n", 1135 le16toh(status->code)); 1136 } 1137 1138 sbd->bd->flags = 0; 1139 1140 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1141 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1142 BUS_DMASYNC_PREREAD); 1143 1144 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1145 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1146 BUS_DMASYNC_PREREAD); 1147 } 1148 1149 /* Tell the firmware what we have processed */ 1150 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1151 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1152 } 1153 1154 static void 1155 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1156 { 1157 struct ieee80211com *ic; 1158 struct ipw_soft_hdr *shdr; 1159 struct ipw_soft_buf *sbuf; 1160 1161 switch (sbd->type) { 1162 case IPW_SBD_TYPE_COMMAND: 1163 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1164 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1165 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1166 break; 1167 1168 case IPW_SBD_TYPE_HEADER: 1169 shdr = sbd->priv; 1170 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1171 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1172 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1173 break; 1174 1175 case IPW_SBD_TYPE_DATA: 1176 ic = &sc->sc_ic; 1177 sbuf = sbd->priv; 1178 1179 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1180 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1181 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1182 m_freem(sbuf->m); 1183 if (sbuf->ni != NULL) 1184 ieee80211_free_node(sbuf->ni); 1185 /* kill watchdog timer */ 1186 sc->sc_tx_timer = 0; 1187 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1188 break; 1189 } 1190 sbd->type = IPW_SBD_TYPE_NOASSOC; 1191 } 1192 1193 static void 1194 ipw_tx_intr(struct ipw_softc *sc) 1195 { 1196 struct ifnet *ifp = &sc->sc_if; 1197 struct ipw_soft_bd *sbd; 1198 uint32_t r, i; 1199 1200 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1201 return; 1202 1203 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1204 1205 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1206 sbd = &sc->stbd_list[i]; 1207 1208 if (sbd->type == IPW_SBD_TYPE_DATA) 1209 ifp->if_opackets++; 1210 1211 ipw_release_sbd(sc, sbd); 1212 sc->txfree++; 1213 } 1214 1215 /* remember what the firmware has processed */ 1216 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1217 1218 /* Call start() since some buffer descriptors have been released */ 1219 ifp->if_flags &= ~IFF_OACTIVE; 1220 (*ifp->if_start)(ifp); 1221 } 1222 1223 static int 1224 ipw_intr(void *arg) 1225 { 1226 struct ipw_softc *sc = arg; 1227 uint32_t r; 1228 1229 r = CSR_READ_4(sc, IPW_CSR_INTR); 1230 if (r == 0 || r == 0xffffffff) 1231 return 0; 1232 1233 /* Disable interrupts */ 1234 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1235 1236 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1237 aprint_error_dev(&sc->sc_dev, "fatal error\n"); 1238 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1239 ipw_stop(&sc->sc_if, 1); 1240 } 1241 1242 if (r & IPW_INTR_FW_INIT_DONE) { 1243 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1244 wakeup(sc); 1245 } 1246 1247 if (r & IPW_INTR_RX_TRANSFER) 1248 ipw_rx_intr(sc); 1249 1250 if (r & IPW_INTR_TX_TRANSFER) 1251 ipw_tx_intr(sc); 1252 1253 /* Acknowledge all interrupts */ 1254 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1255 1256 /* Re-enable interrupts */ 1257 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1258 1259 return 0; 1260 } 1261 1262 /* 1263 * Send a command to the firmware and wait for the acknowledgement. 1264 */ 1265 static int 1266 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1267 { 1268 struct ipw_soft_bd *sbd; 1269 1270 sbd = &sc->stbd_list[sc->txcur]; 1271 1272 sc->cmd.type = htole32(type); 1273 sc->cmd.subtype = 0; 1274 sc->cmd.len = htole32(len); 1275 sc->cmd.seq = 0; 1276 1277 (void)memcpy(sc->cmd.data, data, len); 1278 1279 sbd->type = IPW_SBD_TYPE_COMMAND; 1280 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1281 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1282 sbd->bd->nfrag = 1; 1283 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1284 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1285 1286 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1287 BUS_DMASYNC_PREWRITE); 1288 1289 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1290 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1291 BUS_DMASYNC_PREWRITE); 1292 1293 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1294 1295 /* kick firmware */ 1296 sc->txfree--; 1297 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1298 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1299 1300 /* Wait at most one second for command to complete */ 1301 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1302 } 1303 1304 static int 1305 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1306 { 1307 struct ipw_softc *sc = ifp->if_softc; 1308 struct ieee80211com *ic = &sc->sc_ic; 1309 struct ieee80211_frame *wh; 1310 struct ipw_soft_bd *sbd; 1311 struct ipw_soft_hdr *shdr; 1312 struct ipw_soft_buf *sbuf; 1313 struct ieee80211_key *k; 1314 struct mbuf *mnew; 1315 int error, i; 1316 1317 wh = mtod(m0, struct ieee80211_frame *); 1318 1319 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1320 k = ieee80211_crypto_encap(ic, ni, m0); 1321 if (k == NULL) { 1322 m_freem(m0); 1323 return ENOBUFS; 1324 } 1325 1326 /* packet header may have moved, reset our local pointer */ 1327 wh = mtod(m0, struct ieee80211_frame *); 1328 } 1329 1330 if (sc->sc_drvbpf != NULL) { 1331 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1332 1333 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1334 } 1335 1336 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1337 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1338 KASSERT(shdr != NULL && sbuf != NULL); 1339 1340 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1341 shdr->hdr->subtype = 0; 1342 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1343 shdr->hdr->encrypt = 0; 1344 shdr->hdr->keyidx = 0; 1345 shdr->hdr->keysz = 0; 1346 shdr->hdr->fragmentsz = 0; 1347 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1348 if (ic->ic_opmode == IEEE80211_M_STA) 1349 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1350 else 1351 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1352 1353 /* trim IEEE802.11 header */ 1354 m_adj(m0, sizeof (struct ieee80211_frame)); 1355 1356 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1357 if (error != 0 && error != EFBIG) { 1358 aprint_error_dev(&sc->sc_dev, "could not map mbuf (error %d)\n", 1359 error); 1360 m_freem(m0); 1361 return error; 1362 } 1363 1364 if (error != 0) { 1365 /* too many fragments, linearize */ 1366 1367 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1368 if (mnew == NULL) { 1369 m_freem(m0); 1370 return ENOMEM; 1371 } 1372 1373 M_COPY_PKTHDR(mnew, m0); 1374 1375 /* If the data won't fit in the header, get a cluster */ 1376 if (m0->m_pkthdr.len > MHLEN) { 1377 MCLGET(mnew, M_DONTWAIT); 1378 if (!(mnew->m_flags & M_EXT)) { 1379 m_freem(m0); 1380 m_freem(mnew); 1381 return ENOMEM; 1382 } 1383 } 1384 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1385 m_freem(m0); 1386 mnew->m_len = mnew->m_pkthdr.len; 1387 m0 = mnew; 1388 1389 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1390 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1391 if (error != 0) { 1392 aprint_error_dev(&sc->sc_dev, "could not map mbuf (error %d)\n", error); 1393 m_freem(m0); 1394 return error; 1395 } 1396 } 1397 1398 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1399 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1400 1401 sbd = &sc->stbd_list[sc->txcur]; 1402 sbd->type = IPW_SBD_TYPE_HEADER; 1403 sbd->priv = shdr; 1404 sbd->bd->physaddr = htole32(shdr->addr); 1405 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1406 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1407 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1408 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1409 1410 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1411 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1412 shdr->hdr->encrypt)); 1413 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1414 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1415 1416 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1417 sc->txcur * sizeof (struct ipw_bd), 1418 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1419 1420 sc->txfree--; 1421 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1422 1423 sbuf->m = m0; 1424 sbuf->ni = ni; 1425 1426 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1427 sbd = &sc->stbd_list[sc->txcur]; 1428 1429 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1430 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1431 sbd->bd->nfrag = 0; 1432 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1433 if (i == sbuf->map->dm_nsegs - 1) { 1434 sbd->type = IPW_SBD_TYPE_DATA; 1435 sbd->priv = sbuf; 1436 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1437 } else { 1438 sbd->type = IPW_SBD_TYPE_NOASSOC; 1439 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1440 } 1441 1442 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1443 (int)sbuf->map->dm_segs[i].ds_len)); 1444 1445 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1446 sc->txcur * sizeof (struct ipw_bd), 1447 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1448 1449 sc->txfree--; 1450 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1451 } 1452 1453 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1454 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1455 1456 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1457 BUS_DMASYNC_PREWRITE); 1458 1459 /* Inform firmware about this new packet */ 1460 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1461 1462 return 0; 1463 } 1464 1465 static void 1466 ipw_start(struct ifnet *ifp) 1467 { 1468 struct ipw_softc *sc = ifp->if_softc; 1469 struct ieee80211com *ic = &sc->sc_ic; 1470 struct mbuf *m0; 1471 struct ether_header *eh; 1472 struct ieee80211_node *ni; 1473 1474 1475 if (ic->ic_state != IEEE80211_S_RUN) 1476 return; 1477 1478 for (;;) { 1479 IF_DEQUEUE(&ifp->if_snd, m0); 1480 if (m0 == NULL) 1481 break; 1482 1483 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1484 IF_PREPEND(&ifp->if_snd, m0); 1485 ifp->if_flags |= IFF_OACTIVE; 1486 break; 1487 } 1488 1489 if (m0->m_len < sizeof (struct ether_header) && 1490 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1491 continue; 1492 1493 eh = mtod(m0, struct ether_header *); 1494 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1495 if (ni == NULL) { 1496 m_freem(m0); 1497 continue; 1498 } 1499 1500 bpf_mtap(ifp, m0); 1501 1502 m0 = ieee80211_encap(ic, m0, ni); 1503 if (m0 == NULL) { 1504 ieee80211_free_node(ni); 1505 continue; 1506 } 1507 1508 bpf_mtap3(ic->ic_rawbpf, m0); 1509 1510 if (ipw_tx_start(ifp, m0, ni) != 0) { 1511 ieee80211_free_node(ni); 1512 ifp->if_oerrors++; 1513 break; 1514 } 1515 1516 /* start watchdog timer */ 1517 sc->sc_tx_timer = 5; 1518 ifp->if_timer = 1; 1519 } 1520 } 1521 1522 static void 1523 ipw_watchdog(struct ifnet *ifp) 1524 { 1525 struct ipw_softc *sc = ifp->if_softc; 1526 1527 ifp->if_timer = 0; 1528 1529 if (sc->sc_tx_timer > 0) { 1530 if (--sc->sc_tx_timer == 0) { 1531 aprint_error_dev(&sc->sc_dev, "device timeout\n"); 1532 ifp->if_oerrors++; 1533 ifp->if_flags &= ~IFF_UP; 1534 ipw_stop(ifp, 1); 1535 return; 1536 } 1537 ifp->if_timer = 1; 1538 } 1539 1540 ieee80211_watchdog(&sc->sc_ic); 1541 } 1542 1543 static int 1544 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1545 { 1546 uint32_t addr, size, i; 1547 1548 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1549 return ENOTTY; 1550 1551 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1552 1553 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1554 if (suword(tbl, size) != 0) 1555 return EFAULT; 1556 1557 for (i = 1, ++tbl; i < size; i++, tbl++) { 1558 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1559 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 1560 return EFAULT; 1561 } 1562 return 0; 1563 } 1564 1565 static int 1566 ipw_get_radio(struct ipw_softc *sc, int *ret) 1567 { 1568 uint32_t addr; 1569 1570 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1571 return ENOTTY; 1572 1573 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1574 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 1575 suword(ret, -1); 1576 return 0; 1577 } 1578 1579 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1580 suword(ret, 0); 1581 else 1582 suword(ret, 1); 1583 1584 return 0; 1585 } 1586 1587 static int 1588 ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1589 { 1590 #define IS_RUNNING(ifp) \ 1591 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1592 1593 struct ipw_softc *sc = ifp->if_softc; 1594 struct ieee80211com *ic = &sc->sc_ic; 1595 struct ifreq *ifr = (struct ifreq *)data; 1596 int s, error = 0; 1597 1598 s = splnet(); 1599 1600 switch (cmd) { 1601 case SIOCSIFFLAGS: 1602 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1603 break; 1604 if (ifp->if_flags & IFF_UP) { 1605 if (!(ifp->if_flags & IFF_RUNNING)) 1606 ipw_init(ifp); 1607 } else { 1608 if (ifp->if_flags & IFF_RUNNING) 1609 ipw_stop(ifp, 1); 1610 } 1611 break; 1612 1613 case SIOCADDMULTI: 1614 case SIOCDELMULTI: 1615 /* XXX no h/w multicast filter? --dyoung */ 1616 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1617 /* setup multicast filter, etc */ 1618 error = 0; 1619 } 1620 break; 1621 1622 case SIOCGTABLE1: 1623 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1624 break; 1625 1626 case SIOCGRADIO: 1627 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1628 break; 1629 1630 case SIOCSIFMEDIA: 1631 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1632 sc->sc_fwname = "ipw2100-1.2-i.fw"; 1633 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1634 sc->sc_fwname = "ipw2100-1.2-p.fw"; 1635 else 1636 sc->sc_fwname = "ipw2100-1.2.fw"; 1637 1638 ipw_free_firmware(sc); 1639 /* FALLTRHOUGH */ 1640 default: 1641 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1642 if (error != ENETRESET) 1643 break; 1644 1645 if (error == ENETRESET) { 1646 if (IS_RUNNING(ifp) && 1647 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1648 ipw_init(ifp); 1649 error = 0; 1650 } 1651 1652 } 1653 1654 splx(s); 1655 return error; 1656 #undef IS_RUNNING 1657 } 1658 1659 static uint32_t 1660 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1661 { 1662 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1663 } 1664 1665 static void 1666 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1667 { 1668 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1669 } 1670 1671 static int 1672 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1673 { 1674 uint32_t addr, info; 1675 uint16_t count, size; 1676 uint32_t total; 1677 1678 /* addr[4] + count[2] + size[2] */ 1679 addr = MEM_READ_4(sc, sc->table2_base + off); 1680 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1681 1682 count = info >> 16; 1683 size = info & 0xffff; 1684 total = count * size; 1685 1686 if (total > *len) { 1687 *len = total; 1688 return EINVAL; 1689 } 1690 1691 *len = total; 1692 ipw_read_mem_1(sc, addr, buf, total); 1693 1694 return 0; 1695 } 1696 1697 static void 1698 ipw_stop_master(struct ipw_softc *sc) 1699 { 1700 int ntries; 1701 1702 /* disable interrupts */ 1703 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1704 1705 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1706 for (ntries = 0; ntries < 50; ntries++) { 1707 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1708 break; 1709 DELAY(10); 1710 } 1711 if (ntries == 50) 1712 aprint_error_dev(&sc->sc_dev, "timeout waiting for master\n"); 1713 1714 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1715 IPW_RST_PRINCETON_RESET); 1716 1717 sc->flags &= ~IPW_FLAG_FW_INITED; 1718 } 1719 1720 static int 1721 ipw_reset(struct ipw_softc *sc) 1722 { 1723 int ntries; 1724 1725 ipw_stop_master(sc); 1726 1727 /* move adapter to D0 state */ 1728 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1729 IPW_CTL_INIT); 1730 1731 /* wait for clock stabilization */ 1732 for (ntries = 0; ntries < 1000; ntries++) { 1733 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1734 break; 1735 DELAY(200); 1736 } 1737 if (ntries == 1000) 1738 return EIO; 1739 1740 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1741 IPW_RST_SW_RESET); 1742 1743 DELAY(10); 1744 1745 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1746 IPW_CTL_INIT); 1747 1748 return 0; 1749 } 1750 1751 /* 1752 * Upload the microcode to the device. 1753 */ 1754 static int 1755 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1756 { 1757 int ntries; 1758 1759 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1760 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1761 1762 MEM_WRITE_2(sc, 0x220000, 0x0703); 1763 MEM_WRITE_2(sc, 0x220000, 0x0707); 1764 1765 MEM_WRITE_1(sc, 0x210014, 0x72); 1766 MEM_WRITE_1(sc, 0x210014, 0x72); 1767 1768 MEM_WRITE_1(sc, 0x210000, 0x40); 1769 MEM_WRITE_1(sc, 0x210000, 0x00); 1770 MEM_WRITE_1(sc, 0x210000, 0x40); 1771 1772 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1773 1774 MEM_WRITE_1(sc, 0x210000, 0x00); 1775 MEM_WRITE_1(sc, 0x210000, 0x00); 1776 MEM_WRITE_1(sc, 0x210000, 0x80); 1777 1778 MEM_WRITE_2(sc, 0x220000, 0x0703); 1779 MEM_WRITE_2(sc, 0x220000, 0x0707); 1780 1781 MEM_WRITE_1(sc, 0x210014, 0x72); 1782 MEM_WRITE_1(sc, 0x210014, 0x72); 1783 1784 MEM_WRITE_1(sc, 0x210000, 0x00); 1785 MEM_WRITE_1(sc, 0x210000, 0x80); 1786 1787 for (ntries = 0; ntries < 10; ntries++) { 1788 if (MEM_READ_1(sc, 0x210000) & 1) 1789 break; 1790 DELAY(10); 1791 } 1792 if (ntries == 10) { 1793 aprint_error_dev(&sc->sc_dev, "timeout waiting for ucode to initialize\n"); 1794 return EIO; 1795 } 1796 1797 MEM_WRITE_4(sc, 0x3000e0, 0); 1798 1799 return 0; 1800 } 1801 1802 /* set of macros to handle unaligned little endian data in firmware image */ 1803 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1804 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1805 static int 1806 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1807 { 1808 u_char *p, *end; 1809 uint32_t dst; 1810 uint16_t len; 1811 int error; 1812 1813 p = fw; 1814 end = fw + size; 1815 while (p < end) { 1816 dst = GETLE32(p); p += 4; 1817 len = GETLE16(p); p += 2; 1818 1819 ipw_write_mem_1(sc, dst, p, len); 1820 p += len; 1821 } 1822 1823 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1824 IPW_IO_LED_OFF); 1825 1826 /* enable interrupts */ 1827 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1828 1829 /* kick the firmware */ 1830 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1831 1832 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1833 IPW_CTL_ALLOW_STANDBY); 1834 1835 /* wait at most one second for firmware initialization to complete */ 1836 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1837 aprint_error_dev(&sc->sc_dev, "timeout waiting for firmware initialization " 1838 "to complete\n"); 1839 return error; 1840 } 1841 1842 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1843 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1844 1845 return 0; 1846 } 1847 1848 /* 1849 * Store firmware into kernel memory so we can download it when we need to, 1850 * e.g when the adapter wakes up from suspend mode. 1851 */ 1852 static int 1853 ipw_cache_firmware(struct ipw_softc *sc) 1854 { 1855 struct ipw_firmware *fw = &sc->fw; 1856 struct ipw_firmware_hdr hdr; 1857 firmware_handle_t fwh; 1858 off_t fwsz, p; 1859 int error; 1860 1861 ipw_free_firmware(sc); 1862 1863 if (ipw_accept_eula == 0) { 1864 aprint_error_dev(&sc->sc_dev, 1865 "EULA not accepted; please see the ipw(4) man page.\n"); 1866 return EPERM; 1867 } 1868 1869 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1870 goto fail0; 1871 1872 fwsz = firmware_get_size(fwh); 1873 1874 if (fwsz < sizeof(hdr)) 1875 goto fail2; 1876 1877 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1878 goto fail2; 1879 1880 fw->main_size = le32toh(hdr.main_size); 1881 fw->ucode_size = le32toh(hdr.ucode_size); 1882 1883 fw->main = firmware_malloc(fw->main_size); 1884 if (fw->main == NULL) { 1885 error = ENOMEM; 1886 goto fail1; 1887 } 1888 1889 fw->ucode = firmware_malloc(fw->ucode_size); 1890 if (fw->ucode == NULL) { 1891 error = ENOMEM; 1892 goto fail2; 1893 } 1894 1895 p = sizeof(hdr); 1896 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 1897 goto fail3; 1898 1899 p += fw->main_size; 1900 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 1901 goto fail3; 1902 1903 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1904 fw->ucode_size)); 1905 1906 sc->flags |= IPW_FLAG_FW_CACHED; 1907 1908 firmware_close(fwh); 1909 1910 return 0; 1911 1912 fail3: firmware_free(fw->ucode, 0); 1913 fail2: firmware_free(fw->main, 0); 1914 fail1: firmware_close(fwh); 1915 fail0: 1916 return error; 1917 } 1918 1919 static void 1920 ipw_free_firmware(struct ipw_softc *sc) 1921 { 1922 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1923 return; 1924 1925 firmware_free(sc->fw.main, 0); 1926 firmware_free(sc->fw.ucode, 0); 1927 1928 sc->flags &= ~IPW_FLAG_FW_CACHED; 1929 } 1930 1931 static int 1932 ipw_config(struct ipw_softc *sc) 1933 { 1934 struct ieee80211com *ic = &sc->sc_ic; 1935 struct ifnet *ifp = &sc->sc_if; 1936 struct ipw_security security; 1937 struct ieee80211_key *k; 1938 struct ipw_wep_key wepkey; 1939 struct ipw_scan_options options; 1940 struct ipw_configuration config; 1941 uint32_t data; 1942 int error, i; 1943 1944 switch (ic->ic_opmode) { 1945 case IEEE80211_M_STA: 1946 case IEEE80211_M_HOSTAP: 1947 data = htole32(IPW_MODE_BSS); 1948 break; 1949 1950 case IEEE80211_M_IBSS: 1951 case IEEE80211_M_AHDEMO: 1952 data = htole32(IPW_MODE_IBSS); 1953 break; 1954 1955 case IEEE80211_M_MONITOR: 1956 data = htole32(IPW_MODE_MONITOR); 1957 break; 1958 } 1959 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1960 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1961 if (error != 0) 1962 return error; 1963 1964 if (ic->ic_opmode == IEEE80211_M_IBSS || 1965 ic->ic_opmode == IEEE80211_M_MONITOR) { 1966 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1967 DPRINTF(("Setting channel to %u\n", le32toh(data))); 1968 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1969 if (error != 0) 1970 return error; 1971 } 1972 1973 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1974 DPRINTF(("Enabling adapter\n")); 1975 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1976 } 1977 1978 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1979 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1980 IEEE80211_ADDR_LEN); 1981 if (error != 0) 1982 return error; 1983 1984 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1985 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1986 1987 if (ic->ic_opmode == IEEE80211_M_IBSS) 1988 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1989 if (ifp->if_flags & IFF_PROMISC) 1990 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1991 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1992 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1993 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 1994 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1995 if (error != 0) 1996 return error; 1997 1998 data = htole32(0x3); /* 1, 2 */ 1999 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2000 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2001 if (error != 0) 2002 return error; 2003 2004 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2005 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2006 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2007 if (error != 0) 2008 return error; 2009 2010 data = htole32(IPW_POWER_MODE_CAM); 2011 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2012 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2013 if (error != 0) 2014 return error; 2015 2016 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2017 data = htole32(32); /* default value */ 2018 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2019 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2020 sizeof data); 2021 if (error != 0) 2022 return error; 2023 } 2024 2025 data = htole32(ic->ic_rtsthreshold); 2026 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2027 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2028 if (error != 0) 2029 return error; 2030 2031 data = htole32(ic->ic_fragthreshold); 2032 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2033 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2034 if (error != 0) 2035 return error; 2036 2037 #ifdef IPW_DEBUG 2038 if (ipw_debug > 0) { 2039 printf("Setting ESSID to "); 2040 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2041 printf("\n"); 2042 } 2043 #endif 2044 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2045 ic->ic_des_esslen); 2046 if (error != 0) 2047 return error; 2048 2049 /* no mandatory BSSID */ 2050 DPRINTF(("Setting mandatory BSSID to null\n")); 2051 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2052 if (error != 0) 2053 return error; 2054 2055 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2056 DPRINTF(("Setting desired BSSID to %s\n", 2057 ether_sprintf(ic->ic_des_bssid))); 2058 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2059 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2060 if (error != 0) 2061 return error; 2062 } 2063 2064 (void)memset(&security, 0, sizeof(security)); 2065 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2066 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2067 security.ciphers = htole32(IPW_CIPHER_NONE); 2068 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2069 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2070 sizeof security); 2071 if (error != 0) 2072 return error; 2073 2074 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2075 k = ic->ic_crypto.cs_nw_keys; 2076 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2077 if (k->wk_keylen == 0) 2078 continue; 2079 2080 wepkey.idx = i; 2081 wepkey.len = k->wk_keylen; 2082 memset(wepkey.key, 0, sizeof(wepkey.key)); 2083 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2084 DPRINTF(("Setting wep key index %u len %u\n", 2085 wepkey.idx, wepkey.len)); 2086 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2087 sizeof wepkey); 2088 if (error != 0) 2089 return error; 2090 } 2091 2092 data = htole32(ic->ic_crypto.cs_def_txkey); 2093 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2094 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2095 sizeof data); 2096 if (error != 0) 2097 return error; 2098 } 2099 2100 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2101 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2102 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2103 if (error != 0) 2104 return error; 2105 2106 #if 0 2107 struct ipw_wpa_ie ie; 2108 2109 memset(&ie, 0 sizeof(ie)); 2110 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2111 DPRINTF(("Setting wpa ie\n")); 2112 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2113 if (error != 0) 2114 return error; 2115 #endif 2116 2117 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2118 data = htole32(ic->ic_bintval); 2119 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2120 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2121 sizeof data); 2122 if (error != 0) 2123 return error; 2124 } 2125 2126 options.flags = 0; 2127 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2128 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2129 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2130 if (error != 0) 2131 return error; 2132 2133 /* finally, enable adapter (start scanning for an access point) */ 2134 DPRINTF(("Enabling adapter\n")); 2135 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2136 } 2137 2138 static int 2139 ipw_init(struct ifnet *ifp) 2140 { 2141 struct ipw_softc *sc = ifp->if_softc; 2142 struct ipw_firmware *fw = &sc->fw; 2143 2144 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2145 if (ipw_cache_firmware(sc) != 0) { 2146 aprint_error_dev(&sc->sc_dev, "could not cache the firmware (%s)\n", 2147 sc->sc_fwname); 2148 goto fail; 2149 } 2150 } 2151 2152 ipw_stop(ifp, 0); 2153 2154 if (ipw_reset(sc) != 0) { 2155 aprint_error_dev(&sc->sc_dev, "could not reset adapter\n"); 2156 goto fail; 2157 } 2158 2159 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2160 aprint_error_dev(&sc->sc_dev, "could not load microcode\n"); 2161 goto fail; 2162 } 2163 2164 ipw_stop_master(sc); 2165 2166 /* 2167 * Setup tx, rx and status rings. 2168 */ 2169 sc->txold = IPW_NTBD - 1; 2170 sc->txcur = 0; 2171 sc->txfree = IPW_NTBD - 2; 2172 sc->rxcur = IPW_NRBD - 1; 2173 2174 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2175 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2176 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2177 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2178 2179 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2180 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2181 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2182 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2183 2184 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2185 2186 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2187 aprint_error_dev(&sc->sc_dev, "could not load firmware\n"); 2188 goto fail; 2189 } 2190 2191 sc->flags |= IPW_FLAG_FW_INITED; 2192 2193 /* retrieve information tables base addresses */ 2194 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2195 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2196 2197 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2198 2199 if (ipw_config(sc) != 0) { 2200 aprint_error_dev(&sc->sc_dev, "device configuration failed\n"); 2201 goto fail; 2202 } 2203 2204 ifp->if_flags &= ~IFF_OACTIVE; 2205 ifp->if_flags |= IFF_RUNNING; 2206 2207 return 0; 2208 2209 fail: ifp->if_flags &= ~IFF_UP; 2210 ipw_stop(ifp, 0); 2211 2212 return EIO; 2213 } 2214 2215 static void 2216 ipw_stop(struct ifnet *ifp, int disable) 2217 { 2218 struct ipw_softc *sc = ifp->if_softc; 2219 struct ieee80211com *ic = &sc->sc_ic; 2220 int i; 2221 2222 ipw_stop_master(sc); 2223 2224 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2225 2226 /* 2227 * Release tx buffers. 2228 */ 2229 for (i = 0; i < IPW_NTBD; i++) 2230 ipw_release_sbd(sc, &sc->stbd_list[i]); 2231 2232 sc->sc_tx_timer = 0; 2233 ifp->if_timer = 0; 2234 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2235 2236 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2237 } 2238 2239 static void 2240 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2241 bus_size_t count) 2242 { 2243 for (; count > 0; offset++, datap++, count--) { 2244 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2245 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2246 } 2247 } 2248 2249 static void 2250 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2251 bus_size_t count) 2252 { 2253 for (; count > 0; offset++, datap++, count--) { 2254 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2255 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2256 } 2257 } 2258 2259 SYSCTL_SETUP(sysctl_hw_ipw_accept_eula_setup, "sysctl hw.ipw.accept_eula") 2260 { 2261 const struct sysctlnode *rnode; 2262 const struct sysctlnode *cnode; 2263 2264 sysctl_createv(NULL, 0, NULL, &rnode, 2265 CTLFLAG_PERMANENT, 2266 CTLTYPE_NODE, "hw", 2267 NULL, 2268 NULL, 0, 2269 NULL, 0, 2270 CTL_HW, CTL_EOL); 2271 2272 sysctl_createv(NULL, 0, &rnode, &rnode, 2273 CTLFLAG_PERMANENT, 2274 CTLTYPE_NODE, "ipw", 2275 NULL, 2276 NULL, 0, 2277 NULL, 0, 2278 CTL_CREATE, CTL_EOL); 2279 2280 sysctl_createv(NULL, 0, &rnode, &cnode, 2281 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2282 CTLTYPE_INT, "accept_eula", 2283 SYSCTL_DESCR("Accept Intel EULA and permit use of ipw(4) firmware"), 2284 NULL, 0, 2285 &ipw_accept_eula, sizeof(ipw_accept_eula), 2286 CTL_CREATE, CTL_EOL); 2287 } 2288