1 /* $NetBSD: if_jme.c,v 1.16 2011/01/09 00:12:45 kochi Exp $ */ 2 3 /* 4 * Copyright (c) 2008 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice unmodified, this list of conditions, and the following 36 * disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 51 * SUCH DAMAGE. 52 */ 53 54 55 /* 56 * Driver for JMicron Technologies JMC250 (Giganbit) and JMC260 (Fast) 57 * Ethernet Controllers. 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: if_jme.c,v 1.16 2011/01/09 00:12:45 kochi Exp $"); 62 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/mbuf.h> 67 #include <sys/protosw.h> 68 #include <sys/socket.h> 69 #include <sys/ioctl.h> 70 #include <sys/errno.h> 71 #include <sys/malloc.h> 72 #include <sys/kernel.h> 73 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 74 #include <sys/device.h> 75 #include <sys/syslog.h> 76 #include <sys/sysctl.h> 77 78 #include <net/if.h> 79 #if defined(SIOCSIFMEDIA) 80 #include <net/if_media.h> 81 #endif 82 #include <net/if_types.h> 83 #include <net/if_dl.h> 84 #include <net/route.h> 85 #include <net/netisr.h> 86 87 #include <net/bpf.h> 88 #include <net/bpfdesc.h> 89 90 #include "rnd.h" 91 #if NRND > 0 92 #include <sys/rnd.h> 93 #endif 94 95 #include <netinet/in.h> 96 #include <netinet/in_systm.h> 97 #include <netinet/ip.h> 98 99 #ifdef INET 100 #include <netinet/in_var.h> 101 #endif 102 103 #include <netinet/tcp.h> 104 105 #include <net/if_ether.h> 106 #if defined(INET) 107 #include <netinet/if_inarp.h> 108 #endif 109 110 #include <sys/bus.h> 111 #include <sys/intr.h> 112 113 #include <dev/pci/pcireg.h> 114 #include <dev/pci/pcivar.h> 115 #include <dev/pci/pcidevs.h> 116 #include <dev/pci/if_jmereg.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 struct jme_product_desc { 122 u_int32_t jme_product; 123 const char *jme_desc; 124 }; 125 126 /* number of entries in transmit and receive rings */ 127 #define JME_NBUFS (PAGE_SIZE / sizeof(struct jme_desc)) 128 129 #define JME_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 130 131 /* Water mark to kick reclaiming Tx buffers. */ 132 #define JME_TX_DESC_HIWAT (JME_NBUFS - (((JME_NBUFS) * 3) / 10)) 133 134 135 struct jme_softc { 136 device_t jme_dev; /* base device */ 137 bus_space_tag_t jme_bt_mac; 138 bus_space_handle_t jme_bh_mac; /* Mac registers */ 139 bus_space_tag_t jme_bt_phy; 140 bus_space_handle_t jme_bh_phy; /* PHY registers */ 141 bus_space_tag_t jme_bt_misc; 142 bus_space_handle_t jme_bh_misc; /* Misc registers */ 143 bus_dma_tag_t jme_dmatag; 144 bus_dma_segment_t jme_txseg; /* transmit ring seg */ 145 bus_dmamap_t jme_txmap; /* transmit ring DMA map */ 146 struct jme_desc* jme_txring; /* transmit ring */ 147 bus_dmamap_t jme_txmbufm[JME_NBUFS]; /* transmit mbufs DMA map */ 148 struct mbuf *jme_txmbuf[JME_NBUFS]; /* mbufs being transmitted */ 149 int jme_tx_cons; /* transmit ring consumer */ 150 int jme_tx_prod; /* transmit ring producer */ 151 int jme_tx_cnt; /* transmit ring active count */ 152 bus_dma_segment_t jme_rxseg; /* receive ring seg */ 153 bus_dmamap_t jme_rxmap; /* receive ring DMA map */ 154 struct jme_desc* jme_rxring; /* receive ring */ 155 bus_dmamap_t jme_rxmbufm[JME_NBUFS]; /* receive mbufs DMA map */ 156 struct mbuf *jme_rxmbuf[JME_NBUFS]; /* mbufs being received */ 157 int jme_rx_cons; /* receive ring consumer */ 158 int jme_rx_prod; /* receive ring producer */ 159 void* jme_ih; /* our interrupt */ 160 struct ethercom jme_ec; 161 struct callout jme_tick_ch; /* tick callout */ 162 u_int8_t jme_enaddr[ETHER_ADDR_LEN];/* hardware address */ 163 u_int8_t jme_phyaddr; /* address of integrated phy */ 164 u_int8_t jme_chip_rev; /* chip revision */ 165 u_int8_t jme_rev; /* PCI revision */ 166 mii_data_t jme_mii; /* mii bus */ 167 u_int32_t jme_flags; /* device features, see below */ 168 uint32_t jme_txcsr; /* TX config register */ 169 uint32_t jme_rxcsr; /* RX config register */ 170 #if NRND > 0 171 rndsource_element_t rnd_source; 172 #endif 173 /* interrupt coalition parameters */ 174 struct sysctllog *jme_clog; 175 int jme_intrxto; /* interrupt RX timeout */ 176 int jme_intrxct; /* interrupt RX packets counter */ 177 int jme_inttxto; /* interrupt TX timeout */ 178 int jme_inttxct; /* interrupt TX packets counter */ 179 }; 180 181 #define JME_FLAG_FPGA 0x0001 /* FPGA version */ 182 #define JME_FLAG_GIGA 0x0002 /* giga Ethernet capable */ 183 184 185 #define jme_if jme_ec.ec_if 186 #define jme_bpf jme_if.if_bpf 187 188 typedef struct jme_softc jme_softc_t; 189 typedef u_long ioctl_cmd_t; 190 191 static int jme_pci_match(device_t, cfdata_t, void *); 192 static void jme_pci_attach(device_t, device_t, void *); 193 static void jme_intr_rx(jme_softc_t *); 194 static int jme_intr(void *); 195 196 static int jme_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 197 static int jme_mediachange(struct ifnet *); 198 static void jme_ifwatchdog(struct ifnet *); 199 static bool jme_shutdown(device_t, int); 200 201 static void jme_txeof(struct jme_softc *); 202 static void jme_ifstart(struct ifnet *); 203 static void jme_reset(jme_softc_t *); 204 static int jme_ifinit(struct ifnet *); 205 static int jme_init(struct ifnet *, int); 206 static void jme_stop(struct ifnet *, int); 207 // static void jme_restart(void *); 208 static void jme_ticks(void *); 209 static void jme_mac_config(jme_softc_t *); 210 static void jme_set_filter(jme_softc_t *); 211 212 int jme_mii_read(device_t, int, int); 213 void jme_mii_write(device_t, int, int, int); 214 void jme_statchg(device_t); 215 216 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 217 static int jme_eeprom_macaddr(struct jme_softc *); 218 static int jme_reg_macaddr(struct jme_softc *); 219 220 #define JME_TIMEOUT 1000 221 #define JME_PHY_TIMEOUT 1000 222 #define JME_EEPROM_TIMEOUT 1000 223 224 static int jme_sysctl_intrxto(SYSCTLFN_PROTO); 225 static int jme_sysctl_intrxct(SYSCTLFN_PROTO); 226 static int jme_sysctl_inttxto(SYSCTLFN_PROTO); 227 static int jme_sysctl_inttxct(SYSCTLFN_PROTO); 228 static int jme_root_num; 229 230 231 CFATTACH_DECL_NEW(jme, sizeof(jme_softc_t), 232 jme_pci_match, jme_pci_attach, NULL, NULL); 233 234 static const struct jme_product_desc jme_products[] = { 235 { PCI_PRODUCT_JMICRON_JMC250, 236 "JMicron JMC250 Gigabit Ethernet Controller" }, 237 { PCI_PRODUCT_JMICRON_JMC260, 238 "JMicron JMC260 Gigabit Ethernet Controller" }, 239 { 0, NULL }, 240 }; 241 242 static const struct jme_product_desc *jme_lookup_product(uint32_t); 243 244 static const struct jme_product_desc * 245 jme_lookup_product(uint32_t id) 246 { 247 const struct jme_product_desc *jp; 248 249 for (jp = jme_products ; jp->jme_desc != NULL; jp++) 250 if (PCI_PRODUCT(id) == jp->jme_product) 251 return jp; 252 253 return NULL; 254 } 255 256 static int 257 jme_pci_match(device_t parent, cfdata_t cf, void *aux) 258 { 259 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 260 261 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_JMICRON) 262 return 0; 263 264 if (jme_lookup_product(pa->pa_id) != NULL) 265 return 1; 266 267 return 0; 268 } 269 270 static void 271 jme_pci_attach(device_t parent, device_t self, void *aux) 272 { 273 jme_softc_t *sc = device_private(self); 274 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 275 const struct jme_product_desc *jp; 276 struct ifnet * const ifp = &sc->jme_if; 277 bus_space_tag_t iot1, iot2, memt; 278 bus_space_handle_t ioh1, ioh2, memh; 279 bus_size_t size, size2; 280 pci_intr_handle_t intrhandle; 281 const char *intrstr; 282 pcireg_t csr; 283 int nsegs, i; 284 const struct sysctlnode *node; 285 int jme_nodenum; 286 287 sc->jme_dev = self; 288 aprint_normal("\n"); 289 callout_init(&sc->jme_tick_ch, 0); 290 291 jp = jme_lookup_product(pa->pa_id); 292 if (jp == NULL) 293 panic("jme_pci_attach: impossible"); 294 295 if (jp->jme_product == PCI_PRODUCT_JMICRON_JMC250) 296 sc->jme_flags = JME_FLAG_GIGA; 297 298 /* 299 * Map the card space. Try Mem first. 300 */ 301 if (pci_mapreg_map(pa, JME_PCI_BAR0, 302 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 303 0, &memt, &memh, NULL, &size) == 0) { 304 sc->jme_bt_mac = memt; 305 sc->jme_bh_mac = memh; 306 sc->jme_bt_phy = memt; 307 if (bus_space_subregion(memt, memh, JME_PHY_EEPROM_BASE_MEMOFF, 308 JME_PHY_EEPROM_SIZE, &sc->jme_bh_phy) != 0) { 309 aprint_error_dev(self, "can't subregion PHY space\n"); 310 bus_space_unmap(memt, memh, size); 311 return; 312 } 313 sc->jme_bt_misc = memt; 314 if (bus_space_subregion(memt, memh, JME_MISC_BASE_MEMOFF, 315 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 316 aprint_error_dev(self, "can't subregion misc space\n"); 317 bus_space_unmap(memt, memh, size); 318 return; 319 } 320 } else { 321 if (pci_mapreg_map(pa, JME_PCI_BAR1, PCI_MAPREG_TYPE_IO, 322 0, &iot1, &ioh1, NULL, &size) != 0) { 323 aprint_error_dev(self, "can't map I/O space 1\n"); 324 return; 325 } 326 sc->jme_bt_mac = iot1; 327 sc->jme_bh_mac = ioh1; 328 if (pci_mapreg_map(pa, JME_PCI_BAR2, PCI_MAPREG_TYPE_IO, 329 0, &iot2, &ioh2, NULL, &size2) != 0) { 330 aprint_error_dev(self, "can't map I/O space 2\n"); 331 bus_space_unmap(iot1, ioh1, size); 332 return; 333 } 334 sc->jme_bt_phy = iot2; 335 sc->jme_bh_phy = ioh2; 336 sc->jme_bt_misc = iot2; 337 if (bus_space_subregion(iot2, ioh2, JME_MISC_BASE_IOOFF, 338 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 339 aprint_error_dev(self, "can't subregion misc space\n"); 340 bus_space_unmap(iot1, ioh1, size); 341 bus_space_unmap(iot2, ioh2, size2); 342 return; 343 } 344 } 345 346 if (pci_dma64_available(pa)) 347 sc->jme_dmatag = pa->pa_dmat64; 348 else 349 sc->jme_dmatag = pa->pa_dmat; 350 351 /* Enable the device. */ 352 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 353 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 354 csr | PCI_COMMAND_MASTER_ENABLE); 355 356 aprint_normal_dev(self, "%s\n", jp->jme_desc); 357 358 sc->jme_rev = PCI_REVISION(pa->pa_class); 359 360 csr = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_CHIPMODE); 361 if (((csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 362 CHIPMODE_NOT_FPGA) 363 sc->jme_flags |= JME_FLAG_FPGA; 364 sc->jme_chip_rev = (csr & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 365 aprint_verbose_dev(self, "PCI device revision : 0x%x, Chip revision: " 366 "0x%x", sc->jme_rev, sc->jme_chip_rev); 367 if (sc->jme_flags & JME_FLAG_FPGA) 368 aprint_verbose(" FPGA revision: 0x%x", 369 (csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT); 370 aprint_verbose("\n"); 371 372 /* 373 * Save PHY address. 374 * Integrated JR0211 has fixed PHY address whereas FPGA version 375 * requires PHY probing to get correct PHY address. 376 */ 377 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 378 sc->jme_phyaddr = 379 bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 380 JME_GPREG0) & GPREG0_PHY_ADDR_MASK; 381 } else 382 sc->jme_phyaddr = 0; 383 384 385 jme_reset(sc); 386 387 /* read mac addr */ 388 if (jme_eeprom_macaddr(sc) && jme_reg_macaddr(sc)) { 389 aprint_error_dev(self, "error reading Ethernet address\n"); 390 /* return; */ 391 } 392 aprint_normal_dev(self, "Ethernet address %s\n", 393 ether_sprintf(sc->jme_enaddr)); 394 395 /* Map and establish interrupts */ 396 if (pci_intr_map(pa, &intrhandle)) { 397 aprint_error_dev(self, "couldn't map interrupt\n"); 398 return; 399 } 400 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 401 sc->jme_if.if_softc = sc; 402 sc->jme_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 403 jme_intr, sc); 404 if (sc->jme_ih == NULL) { 405 aprint_error_dev(self, "couldn't establish interrupt"); 406 if (intrstr != NULL) 407 aprint_error(" at %s", intrstr); 408 aprint_error("\n"); 409 return; 410 } 411 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 412 413 /* allocate and map DMA-safe memory for transmit ring */ 414 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 415 &sc->jme_txseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 416 bus_dmamem_map(sc->jme_dmatag, &sc->jme_txseg, 417 nsegs, PAGE_SIZE, (void **)&sc->jme_txring, 418 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 419 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 420 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_txmap) != 0 || 421 bus_dmamap_load(sc->jme_dmatag, sc->jme_txmap, sc->jme_txring, 422 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 423 aprint_error_dev(self, "can't allocate DMA memory TX ring\n"); 424 return; 425 } 426 /* allocate and map DMA-safe memory for receive ring */ 427 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 428 &sc->jme_rxseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 429 bus_dmamem_map(sc->jme_dmatag, &sc->jme_rxseg, 430 nsegs, PAGE_SIZE, (void **)&sc->jme_rxring, 431 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 432 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 433 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_rxmap) != 0 || 434 bus_dmamap_load(sc->jme_dmatag, sc->jme_rxmap, sc->jme_rxring, 435 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 436 aprint_error_dev(self, "can't allocate DMA memory RX ring\n"); 437 return; 438 } 439 for (i = 0; i < JME_NBUFS; i++) { 440 sc->jme_txmbuf[i] = sc->jme_rxmbuf[i] = NULL; 441 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_TX_LEN, 442 JME_NBUFS, JME_MAX_TX_LEN, 0, BUS_DMA_NOWAIT, 443 &sc->jme_txmbufm[i]) != 0) { 444 aprint_error_dev(self, "can't allocate DMA TX map\n"); 445 return; 446 } 447 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_RX_LEN, 448 1, JME_MAX_RX_LEN, 0, BUS_DMA_NOWAIT, 449 &sc->jme_rxmbufm[i]) != 0) { 450 aprint_error_dev(self, "can't allocate DMA RX map\n"); 451 return; 452 } 453 } 454 /* 455 * Initialize our media structures and probe the MII. 456 * 457 * Note that we don't care about the media instance. We 458 * are expecting to have multiple PHYs on the 10/100 cards, 459 * and on those cards we exclude the internal PHY from providing 460 * 10baseT. By ignoring the instance, it allows us to not have 461 * to specify it on the command line when switching media. 462 */ 463 sc->jme_mii.mii_ifp = ifp; 464 sc->jme_mii.mii_readreg = jme_mii_read; 465 sc->jme_mii.mii_writereg = jme_mii_write; 466 sc->jme_mii.mii_statchg = jme_statchg; 467 sc->jme_ec.ec_mii = &sc->jme_mii; 468 ifmedia_init(&sc->jme_mii.mii_media, IFM_IMASK, jme_mediachange, 469 ether_mediastatus); 470 mii_attach(self, &sc->jme_mii, 0xffffffff, MII_PHY_ANY, 471 MII_OFFSET_ANY, 0); 472 if (LIST_FIRST(&sc->jme_mii.mii_phys) == NULL) { 473 ifmedia_add(&sc->jme_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 474 ifmedia_set(&sc->jme_mii.mii_media, IFM_ETHER|IFM_NONE); 475 } else 476 ifmedia_set(&sc->jme_mii.mii_media, IFM_ETHER|IFM_AUTO); 477 478 /* 479 * We can support 802.1Q VLAN-sized frames. 480 */ 481 sc->jme_ec.ec_capabilities |= 482 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 483 484 if (sc->jme_flags & JME_FLAG_GIGA) 485 sc->jme_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 486 487 488 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 489 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 490 ifp->if_ioctl = jme_ifioctl; 491 ifp->if_start = jme_ifstart; 492 ifp->if_watchdog = jme_ifwatchdog; 493 ifp->if_init = jme_ifinit; 494 ifp->if_stop = jme_stop; 495 ifp->if_timer = 0; 496 ifp->if_capabilities |= 497 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 498 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 499 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 500 IFCAP_CSUM_TCPv6_Tx | /* IFCAP_CSUM_TCPv6_Rx | hardware bug */ 501 IFCAP_CSUM_UDPv6_Tx | /* IFCAP_CSUM_UDPv6_Rx | hardware bug */ 502 IFCAP_TSOv4 | IFCAP_TSOv6; 503 IFQ_SET_READY(&ifp->if_snd); 504 if_attach(ifp); 505 ether_ifattach(&(sc)->jme_if, (sc)->jme_enaddr); 506 507 /* 508 * Add shutdown hook so that DMA is disabled prior to reboot. 509 */ 510 if (pmf_device_register1(self, NULL, NULL, jme_shutdown)) 511 pmf_class_network_register(self, ifp); 512 else 513 aprint_error_dev(self, "couldn't establish power handler\n"); 514 515 #if NRND > 0 516 rnd_attach_source(&sc->rnd_source, device_xname(self), 517 RND_TYPE_NET, 0); 518 #endif 519 sc->jme_intrxto = PCCRX_COAL_TO_DEFAULT; 520 sc->jme_intrxct = PCCRX_COAL_PKT_DEFAULT; 521 sc->jme_inttxto = PCCTX_COAL_TO_DEFAULT; 522 sc->jme_inttxct = PCCTX_COAL_PKT_DEFAULT; 523 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 524 0, CTLTYPE_NODE, device_xname(sc->jme_dev), 525 SYSCTL_DESCR("jme per-controller controls"), 526 NULL, 0, NULL, 0, CTL_HW, jme_root_num, CTL_CREATE, 527 CTL_EOL) != 0) { 528 aprint_normal_dev(sc->jme_dev, "couldn't create sysctl node\n"); 529 return; 530 } 531 jme_nodenum = node->sysctl_num; 532 533 /* interrupt moderation sysctls */ 534 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 535 CTLFLAG_READWRITE, 536 CTLTYPE_INT, "int_rxto", 537 SYSCTL_DESCR("jme RX interrupt moderation timer"), 538 jme_sysctl_intrxto, 0, sc, 539 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 540 CTL_EOL) != 0) { 541 aprint_normal_dev(sc->jme_dev, 542 "couldn't create int_rxto sysctl node\n"); 543 } 544 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 545 CTLFLAG_READWRITE, 546 CTLTYPE_INT, "int_rxct", 547 SYSCTL_DESCR("jme RX interrupt moderation packet counter"), 548 jme_sysctl_intrxct, 0, sc, 549 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 550 CTL_EOL) != 0) { 551 aprint_normal_dev(sc->jme_dev, 552 "couldn't create int_rxct sysctl node\n"); 553 } 554 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 555 CTLFLAG_READWRITE, 556 CTLTYPE_INT, "int_txto", 557 SYSCTL_DESCR("jme TX interrupt moderation timer"), 558 jme_sysctl_inttxto, 0, sc, 559 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 560 CTL_EOL) != 0) { 561 aprint_normal_dev(sc->jme_dev, 562 "couldn't create int_txto sysctl node\n"); 563 } 564 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 565 CTLFLAG_READWRITE, 566 CTLTYPE_INT, "int_txct", 567 SYSCTL_DESCR("jme TX interrupt moderation packet counter"), 568 jme_sysctl_inttxct, 0, sc, 569 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 570 CTL_EOL) != 0) { 571 aprint_normal_dev(sc->jme_dev, 572 "couldn't create int_txct sysctl node\n"); 573 } 574 } 575 576 static void 577 jme_stop_rx(jme_softc_t *sc) 578 { 579 uint32_t reg; 580 int i; 581 582 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR); 583 if ((reg & RXCSR_RX_ENB) == 0) 584 return; 585 reg &= ~RXCSR_RX_ENB; 586 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, reg); 587 for (i = JME_TIMEOUT / 10; i > 0; i--) { 588 DELAY(10); 589 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 590 JME_RXCSR) & RXCSR_RX_ENB) == 0) 591 break; 592 } 593 if (i == 0) 594 aprint_error_dev(sc->jme_dev, "stopping recevier timeout!\n"); 595 596 } 597 598 static void 599 jme_stop_tx(jme_softc_t *sc) 600 { 601 uint32_t reg; 602 int i; 603 604 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR); 605 if ((reg & TXCSR_TX_ENB) == 0) 606 return; 607 reg &= ~TXCSR_TX_ENB; 608 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, reg); 609 for (i = JME_TIMEOUT / 10; i > 0; i--) { 610 DELAY(10); 611 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 612 JME_TXCSR) & TXCSR_TX_ENB) == 0) 613 break; 614 } 615 if (i == 0) 616 aprint_error_dev(sc->jme_dev, 617 "stopping transmitter timeout!\n"); 618 } 619 620 static void 621 jme_reset(jme_softc_t *sc) 622 { 623 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, GHC_RESET); 624 DELAY(10); 625 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, 0); 626 } 627 628 static bool 629 jme_shutdown(device_t self, int howto) 630 { 631 jme_softc_t *sc; 632 struct ifnet *ifp; 633 634 sc = device_private(self); 635 ifp = &sc->jme_if; 636 jme_stop(ifp, 1); 637 638 return true; 639 } 640 641 static void 642 jme_stop(struct ifnet *ifp, int disable) 643 { 644 jme_softc_t *sc = ifp->if_softc; 645 int i; 646 /* Stop receiver, transmitter. */ 647 jme_stop_rx(sc); 648 jme_stop_tx(sc); 649 /* free receive mbufs */ 650 for (i = 0; i < JME_NBUFS; i++) { 651 if (sc->jme_rxmbuf[i]) { 652 bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]); 653 m_freem(sc->jme_rxmbuf[i]); 654 } 655 sc->jme_rxmbuf[i] = NULL; 656 } 657 /* process completed transmits */ 658 jme_txeof(sc); 659 /* free abort pending transmits */ 660 for (i = 0; i < JME_NBUFS; i++) { 661 if (sc->jme_txmbuf[i]) { 662 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[i]); 663 m_freem(sc->jme_txmbuf[i]); 664 sc->jme_txmbuf[i] = NULL; 665 } 666 } 667 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 668 ifp->if_timer = 0; 669 } 670 671 #if 0 672 static void 673 jme_restart(void *v) 674 { 675 676 jme_init(v); 677 } 678 #endif 679 680 static int 681 jme_add_rxbuf(jme_softc_t *sc, struct mbuf *m) 682 { 683 int error; 684 bus_dmamap_t map; 685 int i = sc->jme_rx_prod; 686 687 if (sc->jme_rxmbuf[i] != NULL) { 688 aprint_error_dev(sc->jme_dev, 689 "mbuf already here: rxprod %d rxcons %d\n", 690 sc->jme_rx_prod, sc->jme_rx_cons); 691 if (m) 692 m_freem(m); 693 return EINVAL; 694 } 695 696 if (m == NULL) { 697 sc->jme_rxmbuf[i] = NULL; 698 MGETHDR(m, M_DONTWAIT, MT_DATA); 699 if (m == NULL) 700 return (ENOBUFS); 701 MCLGET(m, M_DONTWAIT); 702 if ((m->m_flags & M_EXT) == 0) { 703 m_freem(m); 704 return (ENOBUFS); 705 } 706 } 707 map = sc->jme_rxmbufm[i]; 708 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 709 error = bus_dmamap_load_mbuf(sc->jme_dmatag, map, m, 710 BUS_DMA_READ|BUS_DMA_NOWAIT); 711 if (error) { 712 sc->jme_rxmbuf[i] = NULL; 713 aprint_error_dev(sc->jme_dev, 714 "unable to load rx DMA map %d, error = %d\n", 715 i, error); 716 m_freem(m); 717 return (error); 718 } 719 bus_dmamap_sync(sc->jme_dmatag, map, 0, map->dm_mapsize, 720 BUS_DMASYNC_PREREAD); 721 722 sc->jme_rxmbuf[i] = m; 723 724 sc->jme_rxring[i].buflen = htole32(map->dm_segs[0].ds_len); 725 sc->jme_rxring[i].addr_lo = 726 htole32(JME_ADDR_LO(map->dm_segs[0].ds_addr)); 727 sc->jme_rxring[i].addr_hi = 728 htole32(JME_ADDR_HI(map->dm_segs[0].ds_addr)); 729 sc->jme_rxring[i].flags = 730 htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 731 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 732 i * sizeof(struct jme_desc), sizeof(struct jme_desc), 733 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 734 JME_DESC_INC(sc->jme_rx_prod, JME_NBUFS); 735 return (0); 736 } 737 738 static int 739 jme_ifinit(struct ifnet *ifp) 740 { 741 return jme_init(ifp, 1); 742 } 743 744 static int 745 jme_init(struct ifnet *ifp, int do_ifinit) 746 { 747 jme_softc_t *sc = ifp->if_softc; 748 int i, s; 749 uint8_t eaddr[ETHER_ADDR_LEN]; 750 uint32_t reg; 751 752 s = splnet(); 753 /* cancel any pending IO */ 754 jme_stop(ifp, 1); 755 jme_reset(sc); 756 if ((sc->jme_if.if_flags & IFF_UP) == 0) { 757 splx(s); 758 return 0; 759 } 760 /* allocate receive ring */ 761 sc->jme_rx_prod = 0; 762 for (i = 0; i < JME_NBUFS; i++) { 763 if (jme_add_rxbuf(sc, NULL) < 0) { 764 aprint_error_dev(sc->jme_dev, 765 "can't allocate rx mbuf\n"); 766 for (i--; i >= 0; i--) { 767 bus_dmamap_unload(sc->jme_dmatag, 768 sc->jme_rxmbufm[i]); 769 m_freem(sc->jme_rxmbuf[i]); 770 sc->jme_rxmbuf[i] = NULL; 771 } 772 splx(s); 773 return ENOMEM; 774 } 775 } 776 /* init TX ring */ 777 memset(sc->jme_txring, 0, JME_NBUFS * sizeof(struct jme_desc)); 778 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 779 0, JME_NBUFS * sizeof(struct jme_desc), 780 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 781 for (i = 0; i < JME_NBUFS; i++) 782 sc->jme_txmbuf[i] = NULL; 783 sc->jme_tx_cons = sc->jme_tx_prod = sc->jme_tx_cnt = 0; 784 785 /* Reprogram the station address. */ 786 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 787 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0, 788 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 789 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 790 JME_PAR1, eaddr[5] << 8 | eaddr[4]); 791 792 /* 793 * Configure Tx queue. 794 * Tx priority queue weight value : 0 795 * Tx FIFO threshold for processing next packet : 16QW 796 * Maximum Tx DMA length : 512 797 * Allow Tx DMA burst. 798 */ 799 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 800 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 801 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 802 sc->jme_txcsr |= TXCSR_DMA_SIZE_512; 803 sc->jme_txcsr |= TXCSR_DMA_BURST; 804 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 805 JME_TXCSR, sc->jme_txcsr); 806 807 /* Set Tx descriptor counter. */ 808 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 809 JME_TXQDC, JME_NBUFS); 810 811 /* Set Tx ring address to the hardware. */ 812 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI, 813 JME_ADDR_HI(sc->jme_txmap->dm_segs[0].ds_addr)); 814 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO, 815 JME_ADDR_LO(sc->jme_txmap->dm_segs[0].ds_addr)); 816 817 /* Configure TxMAC parameters. */ 818 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, 819 TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB | 820 TXMAC_THRESH_1_PKT | TXMAC_CRC_ENB | TXMAC_PAD_ENB); 821 822 /* 823 * Configure Rx queue. 824 * FIFO full threshold for transmitting Tx pause packet : 128T 825 * FIFO threshold for processing next packet : 128QW 826 * Rx queue 0 select 827 * Max Rx DMA length : 128 828 * Rx descriptor retry : 32 829 * Rx descriptor retry time gap : 256ns 830 * Don't receive runt/bad frame. 831 */ 832 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 833 /* 834 * Since Rx FIFO size is 4K bytes, receiving frames larger 835 * than 4K bytes will suffer from Rx FIFO overruns. So 836 * decrease FIFO threshold to reduce the FIFO overruns for 837 * frames larger than 4000 bytes. 838 * For best performance of standard MTU sized frames use 839 * maximum allowable FIFO threshold, 128QW. 840 */ 841 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 842 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 843 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 844 else 845 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 846 sc->jme_rxcsr |= RXCSR_DMA_SIZE_128 | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 847 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 848 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 849 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 850 JME_RXCSR, sc->jme_rxcsr); 851 852 /* Set Rx descriptor counter. */ 853 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 854 JME_RXQDC, JME_NBUFS); 855 856 /* Set Rx ring address to the hardware. */ 857 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI, 858 JME_ADDR_HI(sc->jme_rxmap->dm_segs[0].ds_addr)); 859 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO, 860 JME_ADDR_LO(sc->jme_rxmap->dm_segs[0].ds_addr)); 861 862 /* Clear receive filter. */ 863 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, 0); 864 /* Set up the receive filter. */ 865 jme_set_filter(sc); 866 867 /* 868 * Disable all WOL bits as WOL can interfere normal Rx 869 * operation. Also clear WOL detection status bits. 870 */ 871 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS); 872 reg &= ~PMCS_WOL_ENB_MASK; 873 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS, reg); 874 875 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 876 /* 877 * Pad 10bytes right before received frame. This will greatly 878 * help Rx performance on strict-alignment architectures as 879 * it does not need to copy the frame to align the payload. 880 */ 881 reg |= RXMAC_PAD_10BYTES; 882 if ((ifp->if_capenable & 883 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx| 884 IFCAP_CSUM_TCPv6_Rx|IFCAP_CSUM_UDPv6_Rx)) != 0) 885 reg |= RXMAC_CSUM_ENB; 886 reg |= RXMAC_VLAN_ENB; /* enable hardware vlan */ 887 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, reg); 888 889 /* Configure general purpose reg0 */ 890 reg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0); 891 reg &= ~GPREG0_PCC_UNIT_MASK; 892 /* Set PCC timer resolution to micro-seconds unit. */ 893 reg |= GPREG0_PCC_UNIT_US; 894 /* 895 * Disable all shadow register posting as we have to read 896 * JME_INTR_STATUS register in jme_int_task. Also it seems 897 * that it's hard to synchronize interrupt status between 898 * hardware and software with shadow posting due to 899 * requirements of bus_dmamap_sync(9). 900 */ 901 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 902 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 903 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 904 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 905 /* Disable posting of DW0. */ 906 reg &= ~GPREG0_POST_DW0_ENB; 907 /* Clear PME message. */ 908 reg &= ~GPREG0_PME_ENB; 909 /* Set PHY address. */ 910 reg &= ~GPREG0_PHY_ADDR_MASK; 911 reg |= sc->jme_phyaddr; 912 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0, reg); 913 914 /* Configure Tx queue 0 packet completion coalescing. */ 915 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 916 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 917 reg |= PCCTX_COAL_TXQ0; 918 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 919 920 /* Configure Rx queue 0 packet completion coalescing. */ 921 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 922 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 923 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 924 925 /* Disable Timers */ 926 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TMCSR, 0); 927 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER1, 0); 928 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER2, 0); 929 930 /* Configure retry transmit period, retry limit value. */ 931 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 932 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 933 TXTRHD_RT_PERIOD_MASK) | 934 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 935 TXTRHD_RT_LIMIT_SHIFT)); 936 937 /* Disable RSS. */ 938 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 939 JME_RSSC, RSSC_DIS_RSS); 940 941 /* Initialize the interrupt mask. */ 942 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 943 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 944 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 945 JME_INTR_STATUS, 0xFFFFFFFF); 946 947 /* set media, if not already handling a media change */ 948 if (do_ifinit) { 949 int error; 950 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 951 error = 0; 952 else if (error != 0) { 953 aprint_error_dev(sc->jme_dev, "could not set media\n"); 954 return error; 955 } 956 } 957 958 /* Program MAC with resolved speed/duplex/flow-control. */ 959 jme_mac_config(sc); 960 961 /* Start receiver/transmitter. */ 962 sc->jme_rx_cons = 0; 963 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, 964 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 965 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 966 sc->jme_txcsr | TXCSR_TX_ENB); 967 968 /* start ticks calls */ 969 callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc); 970 sc->jme_if.if_flags |= IFF_RUNNING; 971 sc->jme_if.if_flags &= ~IFF_OACTIVE; 972 splx(s); 973 return 0; 974 } 975 976 977 int 978 jme_mii_read(device_t self, int phy, int reg) 979 { 980 struct jme_softc *sc = device_private(self); 981 int val, i; 982 983 /* For FPGA version, PHY address 0 should be ignored. */ 984 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 985 if (phy == 0) 986 return (0); 987 } else { 988 if (sc->jme_phyaddr != phy) 989 return (0); 990 } 991 992 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 993 SMI_OP_READ | SMI_OP_EXECUTE | 994 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 995 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 996 delay(10); 997 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 998 JME_SMI)) & SMI_OP_EXECUTE) == 0) 999 break; 1000 } 1001 1002 if (i == 0) { 1003 aprint_error_dev(sc->jme_dev, "phy read timeout : %d\n", reg); 1004 return (0); 1005 } 1006 1007 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 1008 } 1009 1010 void 1011 jme_mii_write(device_t self, int phy, int reg, int val) 1012 { 1013 struct jme_softc *sc = device_private(self); 1014 int i; 1015 1016 /* For FPGA version, PHY address 0 should be ignored. */ 1017 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 1018 if (phy == 0) 1019 return; 1020 } else { 1021 if (sc->jme_phyaddr != phy) 1022 return; 1023 } 1024 1025 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 1026 SMI_OP_WRITE | SMI_OP_EXECUTE | 1027 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 1028 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 1029 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 1030 delay(10); 1031 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 1032 JME_SMI)) & SMI_OP_EXECUTE) == 0) 1033 break; 1034 } 1035 1036 if (i == 0) 1037 aprint_error_dev(sc->jme_dev, "phy write timeout : %d\n", reg); 1038 1039 return; 1040 } 1041 1042 void 1043 jme_statchg(device_t self) 1044 { 1045 jme_softc_t *sc = device_private(self); 1046 struct ifnet *ifp = &sc->jme_if; 1047 if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == (IFF_UP|IFF_RUNNING)) 1048 jme_init(ifp, 0); 1049 } 1050 1051 static void 1052 jme_intr_rx(jme_softc_t *sc) { 1053 struct mbuf *m, *mhead; 1054 struct ifnet *ifp = &sc->jme_if; 1055 uint32_t flags, buflen; 1056 int i, ipackets, nsegs, seg, error; 1057 struct jme_desc *desc; 1058 1059 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 0, 1060 sizeof(struct jme_desc) * JME_NBUFS, 1061 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1062 #ifdef JMEDEBUG_RX 1063 printf("rxintr sc->jme_rx_cons %d flags 0x%x\n", 1064 sc->jme_rx_cons, le32toh(sc->jme_rxring[sc->jme_rx_cons].flags)); 1065 #endif 1066 ipackets = 0; 1067 while((le32toh(sc->jme_rxring[ sc->jme_rx_cons].flags) & JME_RD_OWN) 1068 == 0) { 1069 i = sc->jme_rx_cons; 1070 desc = &sc->jme_rxring[i]; 1071 #ifdef JMEDEBUG_RX 1072 printf("rxintr i %d flags 0x%x buflen 0x%x\n", 1073 i, le32toh(desc->flags), le32toh(desc->buflen)); 1074 #endif 1075 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 1076 break; 1077 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmbufm[i], 0, 1078 sc->jme_rxmbufm[i]->dm_mapsize, BUS_DMASYNC_POSTREAD); 1079 bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]); 1080 1081 buflen = le32toh(desc->buflen); 1082 nsegs = JME_RX_NSEGS(buflen); 1083 flags = le32toh(desc->flags); 1084 if ((buflen & JME_RX_ERR_STAT) != 0 || 1085 JME_RX_BYTES(buflen) < sizeof(struct ether_header) || 1086 JME_RX_BYTES(buflen) > 1087 (ifp->if_mtu + ETHER_HDR_LEN + JME_RX_PAD_BYTES)) { 1088 #ifdef JMEDEBUG_RX 1089 printf("rx error flags 0x%x buflen 0x%x\n", 1090 flags, buflen); 1091 #endif 1092 ifp->if_ierrors++; 1093 /* reuse the mbufs */ 1094 for (seg = 0; seg < nsegs; seg++) { 1095 m = sc->jme_rxmbuf[i]; 1096 sc->jme_rxmbuf[i] = NULL; 1097 if ((error = jme_add_rxbuf(sc, m)) != 0) 1098 aprint_error_dev(sc->jme_dev, 1099 "can't reuse mbuf: %d\n", error); 1100 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1101 i = sc->jme_rx_cons; 1102 } 1103 continue; 1104 } 1105 /* receive this packet */ 1106 mhead = m = sc->jme_rxmbuf[i]; 1107 sc->jme_rxmbuf[i] = NULL; 1108 /* add a new buffer to chain */ 1109 if (jme_add_rxbuf(sc, NULL) == ENOBUFS) { 1110 for (seg = 0; seg < nsegs; seg++) { 1111 m = sc->jme_rxmbuf[i]; 1112 sc->jme_rxmbuf[i] = NULL; 1113 if ((error = jme_add_rxbuf(sc, m)) != 0) 1114 aprint_error_dev(sc->jme_dev, 1115 "can't reuse mbuf: %d\n", error); 1116 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1117 i = sc->jme_rx_cons; 1118 } 1119 ifp->if_ierrors++; 1120 continue; 1121 } 1122 1123 /* build mbuf chain: head, then remaining segments */ 1124 m->m_pkthdr.rcvif = ifp; 1125 m->m_pkthdr.len = JME_RX_BYTES(buflen) - JME_RX_PAD_BYTES; 1126 m->m_len = (nsegs > 1) ? (MCLBYTES - JME_RX_PAD_BYTES) : 1127 m->m_pkthdr.len; 1128 m->m_data = m->m_ext.ext_buf + JME_RX_PAD_BYTES; 1129 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1130 for (seg = 1; seg < nsegs; seg++) { 1131 i = sc->jme_rx_cons; 1132 m = sc->jme_rxmbuf[i]; 1133 sc->jme_rxmbuf[i] = NULL; 1134 (void)jme_add_rxbuf(sc, NULL); 1135 m->m_flags &= ~M_PKTHDR; 1136 m_cat(mhead, m); 1137 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1138 } 1139 /* and adjust last mbuf's size */ 1140 if (nsegs > 1) { 1141 m->m_len = 1142 JME_RX_BYTES(buflen) - (MCLBYTES * (nsegs - 1)); 1143 } 1144 ifp->if_ipackets++; 1145 ipackets++; 1146 bpf_mtap(ifp, mhead); 1147 1148 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) && 1149 (flags & JME_RD_IPV4)) { 1150 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1151 if (!(flags & JME_RD_IPCSUM)) 1152 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1153 } 1154 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) && 1155 (flags & JME_RD_TCPV4) == JME_RD_TCPV4) { 1156 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1157 if (!(flags & JME_RD_TCPCSUM)) 1158 mhead->m_pkthdr.csum_flags |= 1159 M_CSUM_TCP_UDP_BAD; 1160 } 1161 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) && 1162 (flags & JME_RD_UDPV4) == JME_RD_UDPV4) { 1163 mhead->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1164 if (!(flags & JME_RD_UDPCSUM)) 1165 mhead->m_pkthdr.csum_flags |= 1166 M_CSUM_TCP_UDP_BAD; 1167 } 1168 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) && 1169 (flags & JME_RD_TCPV6) == JME_RD_TCPV6) { 1170 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv6; 1171 if (!(flags & JME_RD_TCPCSUM)) 1172 mhead->m_pkthdr.csum_flags |= 1173 M_CSUM_TCP_UDP_BAD; 1174 } 1175 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) && 1176 (flags & JME_RD_UDPV6) == JME_RD_UDPV6) { 1177 m->m_pkthdr.csum_flags |= M_CSUM_UDPv6; 1178 if (!(flags & JME_RD_UDPCSUM)) 1179 mhead->m_pkthdr.csum_flags |= 1180 M_CSUM_TCP_UDP_BAD; 1181 } 1182 if (flags & JME_RD_VLAN_TAG) { 1183 /* pass to vlan_input() */ 1184 VLAN_INPUT_TAG(ifp, mhead, 1185 (flags & JME_RD_VLAN_MASK), continue); 1186 } 1187 (*ifp->if_input)(ifp, mhead); 1188 } 1189 #if NRND > 0 1190 if (ipackets && RND_ENABLED(&sc->rnd_source)) 1191 rnd_add_uint32(&sc->rnd_source, ipackets); 1192 #endif /* NRND > 0 */ 1193 1194 } 1195 1196 static int 1197 jme_intr(void *v) 1198 { 1199 jme_softc_t *sc = v; 1200 uint32_t istatus; 1201 1202 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1203 JME_INTR_STATUS); 1204 if (istatus == 0 || istatus == 0xFFFFFFFF) 1205 return 0; 1206 /* Disable interrupts. */ 1207 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1208 JME_INTR_MASK_CLR, 0xFFFFFFFF); 1209 again: 1210 /* and update istatus */ 1211 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1212 JME_INTR_STATUS); 1213 if ((istatus & JME_INTRS_CHECK) == 0) 1214 goto done; 1215 /* Reset PCC counter/timer and Ack interrupts. */ 1216 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1217 istatus |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 1218 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1219 istatus |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 1220 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1221 JME_INTR_STATUS, istatus); 1222 1223 if ((sc->jme_if.if_flags & IFF_RUNNING) == 0) 1224 goto done; 1225 #ifdef JMEDEBUG_RX 1226 printf("jme_intr 0x%x RXCS 0x%x RXDBA 0x%x 0x%x RXQDC 0x%x RXNDA 0x%x RXMCS 0x%x\n", istatus, 1227 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR), 1228 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO), 1229 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI), 1230 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXQDC), 1231 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXNDA), 1232 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC)); 1233 printf("jme_intr RXUMA 0x%x 0x%x RXMCHT 0x%x 0x%x GHC 0x%x\n", 1234 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0), 1235 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1), 1236 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0), 1237 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1), 1238 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC)); 1239 #endif 1240 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1241 jme_intr_rx(sc); 1242 if ((istatus & INTR_RXQ_DESC_EMPTY) != 0) { 1243 /* 1244 * Notify hardware availability of new Rx 1245 * buffers. 1246 * Reading RXCSR takes very long time under 1247 * heavy load so cache RXCSR value and writes 1248 * the ORed value with the kick command to 1249 * the RXCSR. This saves one register access 1250 * cycle. 1251 */ 1252 sc->jme_rx_cons = 0; 1253 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1254 JME_RXCSR, 1255 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 1256 } 1257 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1258 jme_ifstart(&sc->jme_if); 1259 1260 goto again; 1261 1262 done: 1263 /* enable interrupts. */ 1264 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1265 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 1266 return 1; 1267 } 1268 1269 1270 static int 1271 jme_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1272 { 1273 struct jme_softc *sc = ifp->if_softc; 1274 int s, error; 1275 struct ifreq *ifr; 1276 struct ifcapreq *ifcr; 1277 1278 s = splnet(); 1279 /* 1280 * we can't support at the same time jumbo frames and 1281 * TX checksums offload/TSO 1282 */ 1283 switch(cmd) { 1284 case SIOCSIFMTU: 1285 ifr = data; 1286 if (ifr->ifr_mtu > JME_TX_FIFO_SIZE && 1287 (ifp->if_capenable & ( 1288 IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx| 1289 IFCAP_CSUM_TCPv6_Tx|IFCAP_CSUM_UDPv6_Tx| 1290 IFCAP_TSOv4|IFCAP_TSOv6)) != 0) { 1291 splx(s); 1292 return EINVAL; 1293 } 1294 break; 1295 case SIOCSIFCAP: 1296 ifcr = data; 1297 if (ifp->if_mtu > JME_TX_FIFO_SIZE && 1298 (ifcr->ifcr_capenable & ( 1299 IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx| 1300 IFCAP_CSUM_TCPv6_Tx|IFCAP_CSUM_UDPv6_Tx| 1301 IFCAP_TSOv4|IFCAP_TSOv6)) != 0) { 1302 splx(s); 1303 return EINVAL; 1304 } 1305 break; 1306 } 1307 1308 error = ether_ioctl(ifp, cmd, data); 1309 if (error == ENETRESET && (ifp->if_flags & IFF_RUNNING)) { 1310 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1311 jme_set_filter(sc); 1312 error = 0; 1313 } else { 1314 error = jme_init(ifp, 0); 1315 } 1316 } 1317 splx(s); 1318 return error; 1319 } 1320 1321 static int 1322 jme_encap(struct jme_softc *sc, struct mbuf **m_head) 1323 { 1324 struct jme_desc *txd; 1325 struct jme_desc *desc; 1326 struct mbuf *m; 1327 struct m_tag *mtag; 1328 int error, i, prod, headdsc, nsegs; 1329 uint32_t cflags, tso_segsz; 1330 1331 if (((*m_head)->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6)) != 0){ 1332 /* 1333 * Due to the adherence to NDIS specification JMC250 1334 * assumes upper stack computed TCP pseudo checksum 1335 * without including payload length. This breaks 1336 * checksum offload for TSO case so recompute TCP 1337 * pseudo checksum for JMC250. Hopefully this wouldn't 1338 * be much burden on modern CPUs. 1339 */ 1340 bool v4 = ((*m_head)->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1341 int iphl = v4 ? 1342 M_CSUM_DATA_IPv4_IPHL((*m_head)->m_pkthdr.csum_data) : 1343 M_CSUM_DATA_IPv6_HL((*m_head)->m_pkthdr.csum_data); 1344 /* 1345 * note: we support vlan offloading, so we should never have 1346 * a ETHERTYPE_VLAN packet here - so ETHER_HDR_LEN is always 1347 * right. 1348 */ 1349 int hlen = ETHER_HDR_LEN + iphl; 1350 1351 if (__predict_false((*m_head)->m_len < 1352 (hlen + sizeof(struct tcphdr)))) { 1353 /* 1354 * TCP/IP headers are not in the first mbuf; we need 1355 * to do this the slow and painful way. Let's just 1356 * hope this doesn't happen very often. 1357 */ 1358 struct tcphdr th; 1359 1360 m_copydata((*m_head), hlen, sizeof(th), &th); 1361 if (v4) { 1362 struct ip ip; 1363 1364 m_copydata((*m_head), ETHER_HDR_LEN, 1365 sizeof(ip), &ip); 1366 ip.ip_len = 0; 1367 m_copyback((*m_head), 1368 ETHER_HDR_LEN + offsetof(struct ip, ip_len), 1369 sizeof(ip.ip_len), &ip.ip_len); 1370 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1371 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1372 } else { 1373 #if INET6 1374 struct ip6_hdr ip6; 1375 1376 m_copydata((*m_head), ETHER_HDR_LEN, 1377 sizeof(ip6), &ip6); 1378 ip6.ip6_plen = 0; 1379 m_copyback((*m_head), ETHER_HDR_LEN + 1380 offsetof(struct ip6_hdr, ip6_plen), 1381 sizeof(ip6.ip6_plen), &ip6.ip6_plen); 1382 th.th_sum = in6_cksum_phdr(&ip6.ip6_src, 1383 &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); 1384 #endif /* INET6 */ 1385 } 1386 m_copyback((*m_head), 1387 hlen + offsetof(struct tcphdr, th_sum), 1388 sizeof(th.th_sum), &th.th_sum); 1389 1390 hlen += th.th_off << 2; 1391 } else { 1392 /* 1393 * TCP/IP headers are in the first mbuf; we can do 1394 * this the easy way. 1395 */ 1396 struct tcphdr *th; 1397 1398 if (v4) { 1399 struct ip *ip = 1400 (void *)(mtod((*m_head), char *) + 1401 ETHER_HDR_LEN); 1402 th = (void *)(mtod((*m_head), char *) + hlen); 1403 1404 ip->ip_len = 0; 1405 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1406 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1407 } else { 1408 #if INET6 1409 struct ip6_hdr *ip6 = 1410 (void *)(mtod((*m_head), char *) + 1411 ETHER_HDR_LEN); 1412 th = (void *)(mtod((*m_head), char *) + hlen); 1413 1414 ip6->ip6_plen = 0; 1415 th->th_sum = in6_cksum_phdr(&ip6->ip6_src, 1416 &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); 1417 #endif /* INET6 */ 1418 } 1419 hlen += th->th_off << 2; 1420 } 1421 1422 } 1423 1424 prod = sc->jme_tx_prod; 1425 txd = &sc->jme_txring[prod]; 1426 1427 error = bus_dmamap_load_mbuf(sc->jme_dmatag, sc->jme_txmbufm[prod], 1428 *m_head, BUS_DMA_WRITE); 1429 if (error) { 1430 if (error == EFBIG) { 1431 log(LOG_ERR, "%s: Tx packet consumes too many " 1432 "DMA segments, dropping...\n", 1433 device_xname(sc->jme_dev)); 1434 m_freem(*m_head); 1435 m_head = NULL; 1436 } 1437 return (error); 1438 } 1439 /* 1440 * Check descriptor overrun. Leave one free descriptor. 1441 * Since we always use 64bit address mode for transmitting, 1442 * each Tx request requires one more dummy descriptor. 1443 */ 1444 nsegs = sc->jme_txmbufm[prod]->dm_nsegs; 1445 #ifdef JMEDEBUG_TX 1446 printf("jme_encap prod %d nsegs %d jme_tx_cnt %d\n", prod, nsegs, sc->jme_tx_cnt); 1447 #endif 1448 if (sc->jme_tx_cnt + nsegs + 1 > JME_NBUFS - 1) { 1449 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[prod]); 1450 return (ENOBUFS); 1451 } 1452 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[prod], 1453 0, sc->jme_txmbufm[prod]->dm_mapsize, BUS_DMASYNC_PREWRITE); 1454 1455 m = *m_head; 1456 cflags = 0; 1457 tso_segsz = 0; 1458 /* Configure checksum offload and TSO. */ 1459 if ((m->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6)) != 0) { 1460 tso_segsz = (uint32_t)m->m_pkthdr.segsz << JME_TD_MSS_SHIFT; 1461 cflags |= JME_TD_TSO; 1462 } else { 1463 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) 1464 cflags |= JME_TD_IPCSUM; 1465 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_TCPv6)) != 0) 1466 cflags |= JME_TD_TCPCSUM; 1467 if ((m->m_pkthdr.csum_flags & (M_CSUM_UDPv4|M_CSUM_UDPv6)) != 0) 1468 cflags |= JME_TD_UDPCSUM; 1469 } 1470 /* Configure VLAN. */ 1471 if ((mtag = VLAN_OUTPUT_TAG(&sc->jme_ec, m)) != NULL) { 1472 cflags |= (VLAN_TAG_VALUE(mtag) & JME_TD_VLAN_MASK); 1473 cflags |= JME_TD_VLAN_TAG; 1474 } 1475 1476 desc = &sc->jme_txring[prod]; 1477 desc->flags = htole32(cflags); 1478 desc->buflen = htole32(tso_segsz); 1479 desc->addr_hi = htole32(m->m_pkthdr.len); 1480 desc->addr_lo = 0; 1481 headdsc = prod; 1482 sc->jme_tx_cnt++; 1483 JME_DESC_INC(prod, JME_NBUFS); 1484 for (i = 0; i < nsegs; i++) { 1485 desc = &sc->jme_txring[prod]; 1486 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1487 desc->buflen = 1488 htole32(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_len); 1489 desc->addr_hi = htole32( 1490 JME_ADDR_HI(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1491 desc->addr_lo = htole32( 1492 JME_ADDR_LO(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1493 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1494 prod * sizeof(struct jme_desc), sizeof(struct jme_desc), 1495 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1496 sc->jme_txmbuf[prod] = NULL; 1497 sc->jme_tx_cnt++; 1498 JME_DESC_INC(prod, JME_NBUFS); 1499 } 1500 1501 /* Update producer index. */ 1502 sc->jme_tx_prod = prod; 1503 #ifdef JMEDEBUG_TX 1504 printf("jme_encap prod now %d\n", sc->jme_tx_prod); 1505 #endif 1506 /* 1507 * Finally request interrupt and give the first descriptor 1508 * owenership to hardware. 1509 */ 1510 desc = &sc->jme_txring[headdsc]; 1511 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1512 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1513 headdsc * sizeof(struct jme_desc), sizeof(struct jme_desc), 1514 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1515 1516 sc->jme_txmbuf[headdsc] = m; 1517 return (0); 1518 } 1519 1520 static void 1521 jme_txeof(struct jme_softc *sc) 1522 { 1523 struct ifnet *ifp; 1524 struct jme_desc *desc; 1525 uint32_t status; 1526 int cons, cons0, nsegs, seg; 1527 1528 ifp = &sc->jme_if; 1529 1530 #ifdef JMEDEBUG_TX 1531 printf("jme_txeof cons %d prod %d\n", 1532 sc->jme_tx_cons, sc->jme_tx_prod); 1533 printf("jme_txeof JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1534 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1535 "JME_TXTRHD 0x%x\n", 1536 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1537 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1538 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1539 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1540 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1541 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1542 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1543 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1544 for (cons = sc->jme_tx_cons; cons != sc->jme_tx_prod; ) { 1545 desc = &sc->jme_txring[cons]; 1546 printf("ring[%d] 0x%x 0x%x 0x%x 0x%x\n", cons, 1547 desc->flags, desc->buflen, desc->addr_hi, desc->addr_lo); 1548 JME_DESC_INC(cons, JME_NBUFS); 1549 } 1550 #endif 1551 1552 cons = sc->jme_tx_cons; 1553 if (cons == sc->jme_tx_prod) 1554 return; 1555 1556 /* 1557 * Go through our Tx list and free mbufs for those 1558 * frames which have been transmitted. 1559 */ 1560 for (; cons != sc->jme_tx_prod;) { 1561 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1562 cons * sizeof(struct jme_desc), sizeof(struct jme_desc), 1563 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1564 1565 desc = &sc->jme_txring[cons]; 1566 status = le32toh(desc->flags); 1567 #ifdef JMEDEBUG_TX 1568 printf("jme_txeof %i status 0x%x nsegs %d\n", cons, status, 1569 sc->jme_txmbufm[cons]->dm_nsegs); 1570 #endif 1571 if (status & JME_TD_OWN) 1572 break; 1573 1574 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 1575 ifp->if_oerrors++; 1576 else { 1577 ifp->if_opackets++; 1578 if ((status & JME_TD_COLLISION) != 0) 1579 ifp->if_collisions += 1580 le32toh(desc->buflen) & 1581 JME_TD_BUF_LEN_MASK; 1582 } 1583 /* 1584 * Only the first descriptor of multi-descriptor 1585 * transmission is updated so driver have to skip entire 1586 * chained buffers for the transmiited frame. In other 1587 * words, JME_TD_OWN bit is valid only at the first 1588 * descriptor of a multi-descriptor transmission. 1589 */ 1590 nsegs = sc->jme_txmbufm[cons]->dm_nsegs; 1591 cons0 = cons; 1592 JME_DESC_INC(cons, JME_NBUFS); 1593 for (seg = 1; seg < nsegs + 1; seg++) { 1594 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1595 cons * sizeof(struct jme_desc), 1596 sizeof(struct jme_desc), 1597 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1598 sc->jme_txring[cons].flags = 0; 1599 JME_DESC_INC(cons, JME_NBUFS); 1600 } 1601 /* Reclaim transferred mbufs. */ 1602 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[cons0], 1603 0, sc->jme_txmbufm[cons0]->dm_mapsize, 1604 BUS_DMASYNC_POSTWRITE); 1605 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[cons0]); 1606 1607 KASSERT(sc->jme_txmbuf[cons0] != NULL); 1608 m_freem(sc->jme_txmbuf[cons0]); 1609 sc->jme_txmbuf[cons0] = NULL; 1610 sc->jme_tx_cnt -= nsegs + 1; 1611 KASSERT(sc->jme_tx_cnt >= 0); 1612 sc->jme_if.if_flags &= ~IFF_OACTIVE; 1613 } 1614 sc->jme_tx_cons = cons; 1615 /* Unarm watchog timer when there is no pending descriptors in queue. */ 1616 if (sc->jme_tx_cnt == 0) 1617 ifp->if_timer = 0; 1618 #ifdef JMEDEBUG_TX 1619 printf("jme_txeof jme_tx_cnt %d\n", sc->jme_tx_cnt); 1620 #endif 1621 } 1622 1623 static void 1624 jme_ifstart(struct ifnet *ifp) 1625 { 1626 jme_softc_t *sc = ifp->if_softc; 1627 struct mbuf *mb_head; 1628 int enq; 1629 1630 /* 1631 * check if we can free some desc. 1632 * Clear TX interrupt status to reset TX coalescing counters. 1633 */ 1634 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1635 JME_INTR_STATUS, INTR_TXQ_COMP); 1636 jme_txeof(sc); 1637 1638 if ((sc->jme_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1639 return; 1640 for (enq = 0;; enq++) { 1641 nexttx: 1642 /* Grab a paquet for output */ 1643 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1644 if (mb_head == NULL) { 1645 #ifdef JMEDEBUG_TX 1646 printf("%s: nothing to send\n", __func__); 1647 #endif 1648 break; 1649 } 1650 /* try to add this mbuf to the TX ring */ 1651 if (jme_encap(sc, &mb_head)) { 1652 if (mb_head == NULL) { 1653 ifp->if_oerrors++; 1654 /* packet dropped, try next one */ 1655 goto nexttx; 1656 } 1657 /* resource shortage, try again later */ 1658 IF_PREPEND(&ifp->if_snd, mb_head); 1659 ifp->if_flags |= IFF_OACTIVE; 1660 break; 1661 } 1662 /* Pass packet to bpf if there is a listener */ 1663 bpf_mtap(ifp, mb_head); 1664 } 1665 #ifdef JMEDEBUG_TX 1666 printf("jme_ifstart enq %d\n", enq); 1667 #endif 1668 if (enq) { 1669 /* 1670 * Set a 5 second timer just in case we don't hear from 1671 * the card again. 1672 */ 1673 ifp->if_timer = 5; 1674 /* 1675 * Reading TXCSR takes very long time under heavy load 1676 * so cache TXCSR value and writes the ORed value with 1677 * the kick command to the TXCSR. This saves one register 1678 * access cycle. 1679 */ 1680 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 1681 sc->jme_txcsr | TXCSR_TX_ENB | TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1682 #ifdef JMEDEBUG_TX 1683 printf("jme_ifstart JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1684 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1685 "JME_TXTRHD 0x%x\n", 1686 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1687 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1688 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1689 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1690 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1691 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1692 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1693 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1694 #endif 1695 } 1696 } 1697 1698 static void 1699 jme_ifwatchdog(struct ifnet *ifp) 1700 { 1701 jme_softc_t *sc = ifp->if_softc; 1702 1703 if ((ifp->if_flags & IFF_RUNNING) == 0) 1704 return; 1705 printf("%s: device timeout\n", device_xname(sc->jme_dev)); 1706 ifp->if_oerrors++; 1707 jme_init(ifp, 0); 1708 } 1709 1710 static int 1711 jme_mediachange(struct ifnet *ifp) 1712 { 1713 int error; 1714 jme_softc_t *sc = ifp->if_softc; 1715 1716 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 1717 error = 0; 1718 else if (error != 0) { 1719 aprint_error_dev(sc->jme_dev, "could not set media\n"); 1720 return error; 1721 } 1722 return 0; 1723 } 1724 1725 static void 1726 jme_ticks(void *v) 1727 { 1728 jme_softc_t *sc = v; 1729 int s = splnet(); 1730 1731 /* Tick the MII. */ 1732 mii_tick(&sc->jme_mii); 1733 1734 /* every seconds */ 1735 callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc); 1736 splx(s); 1737 } 1738 1739 static void 1740 jme_mac_config(jme_softc_t *sc) 1741 { 1742 uint32_t ghc, gpreg, rxmac, txmac, txpause; 1743 struct mii_data *mii = &sc->jme_mii; 1744 1745 ghc = 0; 1746 rxmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1747 rxmac &= ~RXMAC_FC_ENB; 1748 txmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC); 1749 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 1750 txpause = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC); 1751 txpause &= ~TXPFC_PAUSE_ENB; 1752 1753 if (mii->mii_media_active & IFM_FDX) { 1754 ghc |= GHC_FULL_DUPLEX; 1755 rxmac &= ~RXMAC_COLL_DET_ENB; 1756 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 1757 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 1758 TXMAC_FRAME_BURST); 1759 /* Disable retry transmit timer/retry limit. */ 1760 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1761 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) 1762 & ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 1763 } else { 1764 rxmac |= RXMAC_COLL_DET_ENB; 1765 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 1766 /* Enable retry transmit timer/retry limit. */ 1767 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1768 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) | TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 1769 } 1770 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 1771 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1772 case IFM_10_T: 1773 ghc |= GHC_SPEED_10 | GHC_CLKSRC_10_100; 1774 break; 1775 case IFM_100_TX: 1776 ghc |= GHC_SPEED_100 | GHC_CLKSRC_10_100; 1777 break; 1778 case IFM_1000_T: 1779 ghc |= GHC_SPEED_1000 | GHC_CLKSRC_1000; 1780 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 1781 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 1782 break; 1783 default: 1784 break; 1785 } 1786 if ((sc->jme_flags & JME_FLAG_GIGA) && 1787 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 1788 /* 1789 * Workaround occasional packet loss issue of JMC250 A2 1790 * when it runs on half-duplex media. 1791 */ 1792 #ifdef JMEDEBUG 1793 printf("JME250 A2 workaround\n"); 1794 #endif 1795 gpreg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1796 JME_GPREG1); 1797 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1798 gpreg &= ~GPREG1_HDPX_FIX; 1799 else 1800 gpreg |= GPREG1_HDPX_FIX; 1801 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1802 JME_GPREG1, gpreg); 1803 /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 1804 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 1805 /* Extend interface FIFO depth. */ 1806 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1807 0x1B, 0x0000); 1808 } else { 1809 /* Select default interface FIFO depth. */ 1810 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1811 0x1B, 0x0004); 1812 } 1813 } 1814 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, ghc); 1815 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxmac); 1816 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, txmac); 1817 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC, txpause); 1818 } 1819 1820 static void 1821 jme_set_filter(jme_softc_t *sc) 1822 { 1823 struct ifnet *ifp = &sc->jme_if; 1824 struct ether_multistep step; 1825 struct ether_multi *enm; 1826 uint32_t hash[2] = {0, 0}; 1827 int i; 1828 uint32_t rxcfg; 1829 1830 rxcfg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1831 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 1832 RXMAC_ALLMULTI); 1833 /* Always accept frames destined to our station address. */ 1834 rxcfg |= RXMAC_UNICAST; 1835 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1836 rxcfg |= RXMAC_BROADCAST; 1837 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1838 if ((ifp->if_flags & IFF_PROMISC) != 0) 1839 rxcfg |= RXMAC_PROMISC; 1840 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1841 rxcfg |= RXMAC_ALLMULTI; 1842 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1843 JME_MAR0, 0xFFFFFFFF); 1844 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1845 JME_MAR1, 0xFFFFFFFF); 1846 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1847 JME_RXMAC, rxcfg); 1848 return; 1849 } 1850 /* 1851 * Set up the multicast address filter by passing all multicast 1852 * addresses through a CRC generator, and then using the low-order 1853 * 6 bits as an index into the 64 bit multicast hash table. The 1854 * high order bits select the register, while the rest of the bits 1855 * select the bit within the register. 1856 */ 1857 rxcfg |= RXMAC_MULTICAST; 1858 memset(hash, 0, sizeof(hash)); 1859 1860 ETHER_FIRST_MULTI(step, &sc->jme_ec, enm); 1861 while (enm != NULL) { 1862 #ifdef JEMDBUG 1863 printf("%s: addrs %s %s\n", __func__, 1864 ether_sprintf(enm->enm_addrlo), 1865 ether_sprintf(enm->enm_addrhi)); 1866 #endif 1867 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1868 i = ether_crc32_be(enm->enm_addrlo, 6); 1869 /* Just want the 6 least significant bits. */ 1870 i &= 0x3f; 1871 hash[i / 32] |= 1 << (i%32); 1872 } else { 1873 hash[0] = hash[1] = 0xffffffff; 1874 sc->jme_if.if_flags |= IFF_ALLMULTI; 1875 break; 1876 } 1877 ETHER_NEXT_MULTI(step, enm); 1878 } 1879 #ifdef JMEDEBUG 1880 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]); 1881 #endif 1882 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0, hash[0]); 1883 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1, hash[1]); 1884 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxcfg); 1885 } 1886 1887 #if 0 1888 static int 1889 jme_multicast_hash(uint8_t *a) 1890 { 1891 int hash; 1892 1893 #define DA(addr,bit) (addr[5 - (bit / 8)] & (1 << (bit % 8))) 1894 #define xor8(a,b,c,d,e,f,g,h) \ 1895 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \ 1896 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1897 1898 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1899 DA(a,36), DA(a,42)); 1900 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1901 DA(a,37), DA(a,43)) << 1; 1902 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1903 DA(a,38), DA(a,44)) << 2; 1904 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1905 DA(a,39), DA(a,45)) << 3; 1906 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1907 DA(a,40), DA(a,46)) << 4; 1908 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1909 DA(a,41), DA(a,47)) << 5; 1910 1911 return hash; 1912 } 1913 #endif 1914 1915 static int 1916 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 1917 { 1918 uint32_t reg; 1919 int i; 1920 1921 *val = 0; 1922 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1923 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1924 JME_SMBCSR); 1925 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 1926 break; 1927 delay(10); 1928 } 1929 1930 if (i == 0) { 1931 aprint_error_dev(sc->jme_dev, "EEPROM idle timeout!\n"); 1932 return (ETIMEDOUT); 1933 } 1934 1935 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 1936 bus_space_write_4(sc->jme_bt_phy, sc->jme_bh_phy, 1937 JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 1938 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1939 delay(10); 1940 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1941 JME_SMBINTF); 1942 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 1943 break; 1944 } 1945 1946 if (i == 0) { 1947 aprint_error_dev(sc->jme_dev, "EEPROM read timeout!\n"); 1948 return (ETIMEDOUT); 1949 } 1950 1951 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, JME_SMBINTF); 1952 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 1953 return (0); 1954 } 1955 1956 1957 static int 1958 jme_eeprom_macaddr(struct jme_softc *sc) 1959 { 1960 uint8_t eaddr[ETHER_ADDR_LEN]; 1961 uint8_t fup, reg, val; 1962 uint32_t offset; 1963 int match; 1964 1965 offset = 0; 1966 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1967 fup != JME_EEPROM_SIG0) 1968 return (ENOENT); 1969 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1970 fup != JME_EEPROM_SIG1) 1971 return (ENOENT); 1972 match = 0; 1973 do { 1974 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 1975 break; 1976 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) 1977 == (fup & (JME_EEPROM_FUNC_MASK|JME_EEPROM_PAGE_MASK))) { 1978 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 1979 break; 1980 if (reg >= JME_PAR0 && 1981 reg < JME_PAR0 + ETHER_ADDR_LEN) { 1982 if (jme_eeprom_read_byte(sc, offset + 2, 1983 &val) != 0) 1984 break; 1985 eaddr[reg - JME_PAR0] = val; 1986 match++; 1987 } 1988 } 1989 if (fup & JME_EEPROM_DESC_END) 1990 break; 1991 1992 /* Try next eeprom descriptor. */ 1993 offset += JME_EEPROM_DESC_BYTES; 1994 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 1995 1996 if (match == ETHER_ADDR_LEN) { 1997 memcpy(sc->jme_enaddr, eaddr, ETHER_ADDR_LEN); 1998 return (0); 1999 } 2000 2001 return (ENOENT); 2002 } 2003 2004 static int 2005 jme_reg_macaddr(struct jme_softc *sc) 2006 { 2007 uint32_t par0, par1; 2008 2009 par0 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0); 2010 par1 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1); 2011 par1 &= 0xffff; 2012 if ((par0 == 0 && par1 == 0) || 2013 (par0 == 0xffffffff && par1 == 0xffff)) { 2014 return (ENOENT); 2015 } else { 2016 sc->jme_enaddr[0] = (par0 >> 0) & 0xff; 2017 sc->jme_enaddr[1] = (par0 >> 8) & 0xff; 2018 sc->jme_enaddr[2] = (par0 >> 16) & 0xff; 2019 sc->jme_enaddr[3] = (par0 >> 24) & 0xff; 2020 sc->jme_enaddr[4] = (par1 >> 0) & 0xff; 2021 sc->jme_enaddr[5] = (par1 >> 8) & 0xff; 2022 } 2023 return (0); 2024 } 2025 2026 /* 2027 * Set up sysctl(3) MIB, hw.jme.* - Individual controllers will be 2028 * set up in jme_pci_attach() 2029 */ 2030 SYSCTL_SETUP(sysctl_jme, "sysctl jme subtree setup") 2031 { 2032 int rc; 2033 const struct sysctlnode *node; 2034 2035 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2036 0, CTLTYPE_NODE, "hw", NULL, 2037 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2038 goto err; 2039 } 2040 2041 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2042 0, CTLTYPE_NODE, "jme", 2043 SYSCTL_DESCR("jme interface controls"), 2044 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2045 goto err; 2046 } 2047 2048 jme_root_num = node->sysctl_num; 2049 return; 2050 2051 err: 2052 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2053 } 2054 2055 static int 2056 jme_sysctl_intrxto(SYSCTLFN_ARGS) 2057 { 2058 int error, t; 2059 struct sysctlnode node; 2060 struct jme_softc *sc; 2061 uint32_t reg; 2062 2063 node = *rnode; 2064 sc = node.sysctl_data; 2065 t = sc->jme_intrxto; 2066 node.sysctl_data = &t; 2067 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2068 if (error || newp == NULL) 2069 return error; 2070 2071 if (t < PCCRX_COAL_TO_MIN || t > PCCRX_COAL_TO_MAX) 2072 return EINVAL; 2073 2074 /* 2075 * update the softc with sysctl-changed value, and mark 2076 * for hardware update 2077 */ 2078 sc->jme_intrxto = t; 2079 /* Configure Rx queue 0 packet completion coalescing. */ 2080 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2081 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2082 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2083 return 0; 2084 } 2085 2086 static int 2087 jme_sysctl_intrxct(SYSCTLFN_ARGS) 2088 { 2089 int error, t; 2090 struct sysctlnode node; 2091 struct jme_softc *sc; 2092 uint32_t reg; 2093 2094 node = *rnode; 2095 sc = node.sysctl_data; 2096 t = sc->jme_intrxct; 2097 node.sysctl_data = &t; 2098 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2099 if (error || newp == NULL) 2100 return error; 2101 2102 if (t < PCCRX_COAL_PKT_MIN || t > PCCRX_COAL_PKT_MAX) 2103 return EINVAL; 2104 2105 /* 2106 * update the softc with sysctl-changed value, and mark 2107 * for hardware update 2108 */ 2109 sc->jme_intrxct = t; 2110 /* Configure Rx queue 0 packet completion coalescing. */ 2111 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2112 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2113 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2114 return 0; 2115 } 2116 2117 static int 2118 jme_sysctl_inttxto(SYSCTLFN_ARGS) 2119 { 2120 int error, t; 2121 struct sysctlnode node; 2122 struct jme_softc *sc; 2123 uint32_t reg; 2124 2125 node = *rnode; 2126 sc = node.sysctl_data; 2127 t = sc->jme_inttxto; 2128 node.sysctl_data = &t; 2129 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2130 if (error || newp == NULL) 2131 return error; 2132 2133 if (t < PCCTX_COAL_TO_MIN || t > PCCTX_COAL_TO_MAX) 2134 return EINVAL; 2135 2136 /* 2137 * update the softc with sysctl-changed value, and mark 2138 * for hardware update 2139 */ 2140 sc->jme_inttxto = t; 2141 /* Configure Tx queue 0 packet completion coalescing. */ 2142 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2143 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2144 reg |= PCCTX_COAL_TXQ0; 2145 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2146 return 0; 2147 } 2148 2149 static int 2150 jme_sysctl_inttxct(SYSCTLFN_ARGS) 2151 { 2152 int error, t; 2153 struct sysctlnode node; 2154 struct jme_softc *sc; 2155 uint32_t reg; 2156 2157 node = *rnode; 2158 sc = node.sysctl_data; 2159 t = sc->jme_inttxct; 2160 node.sysctl_data = &t; 2161 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2162 if (error || newp == NULL) 2163 return error; 2164 2165 if (t < PCCTX_COAL_PKT_MIN || t > PCCTX_COAL_PKT_MAX) 2166 return EINVAL; 2167 2168 /* 2169 * update the softc with sysctl-changed value, and mark 2170 * for hardware update 2171 */ 2172 sc->jme_inttxct = t; 2173 /* Configure Tx queue 0 packet completion coalescing. */ 2174 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2175 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2176 reg |= PCCTX_COAL_TXQ0; 2177 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2178 return 0; 2179 } 2180