1 /* $NetBSD: if_msk.c,v 1.35 2010/04/05 07:20:26 joerg Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.35 2010/04/05 07:20:26 joerg Exp $"); 56 57 #include "rnd.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/sockio.h> 62 #include <sys/mbuf.h> 63 #include <sys/malloc.h> 64 #include <sys/mutex.h> 65 #include <sys/kernel.h> 66 #include <sys/socket.h> 67 #include <sys/device.h> 68 #include <sys/queue.h> 69 #include <sys/callout.h> 70 #include <sys/sysctl.h> 71 #include <sys/endian.h> 72 #ifdef __NetBSD__ 73 #define letoh16 htole16 74 #define letoh32 htole32 75 #endif 76 77 #include <net/if.h> 78 #include <net/if_dl.h> 79 #include <net/if_types.h> 80 81 #include <net/if_media.h> 82 83 #include <net/bpf.h> 84 #if NRND > 0 85 #include <sys/rnd.h> 86 #endif 87 88 #include <dev/mii/mii.h> 89 #include <dev/mii/miivar.h> 90 #include <dev/mii/brgphyreg.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcidevs.h> 95 96 #include <dev/pci/if_skreg.h> 97 #include <dev/pci/if_mskvar.h> 98 99 int mskc_probe(device_t, cfdata_t, void *); 100 void mskc_attach(device_t, device_t, void *); 101 static bool mskc_suspend(device_t, const pmf_qual_t *); 102 static bool mskc_resume(device_t, const pmf_qual_t *); 103 int msk_probe(device_t, cfdata_t, void *); 104 void msk_attach(device_t, device_t, void *); 105 int mskcprint(void *, const char *); 106 int msk_intr(void *); 107 void msk_intr_yukon(struct sk_if_softc *); 108 __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 109 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 110 void msk_txeof(struct sk_if_softc *, int); 111 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 112 void msk_start(struct ifnet *); 113 int msk_ioctl(struct ifnet *, u_long, void *); 114 int msk_init(struct ifnet *); 115 void msk_init_yukon(struct sk_if_softc *); 116 void msk_stop(struct ifnet *, int); 117 void msk_watchdog(struct ifnet *); 118 void msk_reset(struct sk_softc *); 119 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 120 int msk_alloc_jumbo_mem(struct sk_if_softc *); 121 void *msk_jalloc(struct sk_if_softc *); 122 void msk_jfree(struct mbuf *, void *, size_t, void *); 123 int msk_init_rx_ring(struct sk_if_softc *); 124 int msk_init_tx_ring(struct sk_if_softc *); 125 126 void msk_update_int_mod(struct sk_softc *, int); 127 128 int msk_miibus_readreg(device_t, int, int); 129 void msk_miibus_writereg(device_t, int, int, int); 130 void msk_miibus_statchg(device_t); 131 132 void msk_setfilt(struct sk_if_softc *, void *, int); 133 void msk_setmulti(struct sk_if_softc *); 134 void msk_setpromisc(struct sk_if_softc *); 135 void msk_tick(void *); 136 137 /* #define MSK_DEBUG 1 */ 138 #ifdef MSK_DEBUG 139 #define DPRINTF(x) if (mskdebug) printf x 140 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 141 int mskdebug = MSK_DEBUG; 142 143 void msk_dump_txdesc(struct msk_tx_desc *, int); 144 void msk_dump_mbuf(struct mbuf *); 145 void msk_dump_bytes(const char *, int); 146 #else 147 #define DPRINTF(x) 148 #define DPRINTFN(n,x) 149 #endif 150 151 static int msk_sysctl_handler(SYSCTLFN_PROTO); 152 static int msk_root_num; 153 154 /* supported device vendors */ 155 static const struct msk_product { 156 pci_vendor_id_t msk_vendor; 157 pci_product_id_t msk_product; 158 } msk_products[] = { 159 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 160 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 162 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 }, 163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C055 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 186 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 187 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 188 }; 189 190 static inline u_int32_t 191 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 192 { 193 return CSR_READ_4(sc, reg); 194 } 195 196 static inline u_int16_t 197 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 198 { 199 return CSR_READ_2(sc, reg); 200 } 201 202 static inline u_int8_t 203 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 204 { 205 return CSR_READ_1(sc, reg); 206 } 207 208 static inline void 209 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 210 { 211 CSR_WRITE_4(sc, reg, x); 212 } 213 214 static inline void 215 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 216 { 217 CSR_WRITE_2(sc, reg, x); 218 } 219 220 static inline void 221 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 222 { 223 CSR_WRITE_1(sc, reg, x); 224 } 225 226 int 227 msk_miibus_readreg(device_t dev, int phy, int reg) 228 { 229 struct sk_if_softc *sc_if = device_private(dev); 230 u_int16_t val; 231 int i; 232 233 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 234 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 235 236 for (i = 0; i < SK_TIMEOUT; i++) { 237 DELAY(1); 238 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 239 if (val & YU_SMICR_READ_VALID) 240 break; 241 } 242 243 if (i == SK_TIMEOUT) { 244 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 245 return (0); 246 } 247 248 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 249 SK_TIMEOUT)); 250 251 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 252 253 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 254 phy, reg, val)); 255 256 return (val); 257 } 258 259 void 260 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 261 { 262 struct sk_if_softc *sc_if = device_private(dev); 263 int i; 264 265 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 266 phy, reg, val)); 267 268 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 269 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 270 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 271 272 for (i = 0; i < SK_TIMEOUT; i++) { 273 DELAY(1); 274 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 275 break; 276 } 277 278 if (i == SK_TIMEOUT) 279 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 280 } 281 282 void 283 msk_miibus_statchg(device_t dev) 284 { 285 struct sk_if_softc *sc_if = device_private(dev); 286 struct mii_data *mii = &sc_if->sk_mii; 287 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 288 int gpcr; 289 290 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 291 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 292 293 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 294 /* Set speed. */ 295 gpcr |= YU_GPCR_SPEED_DIS; 296 switch (IFM_SUBTYPE(mii->mii_media_active)) { 297 case IFM_1000_SX: 298 case IFM_1000_LX: 299 case IFM_1000_CX: 300 case IFM_1000_T: 301 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 302 break; 303 case IFM_100_TX: 304 gpcr |= YU_GPCR_SPEED; 305 break; 306 } 307 308 /* Set duplex. */ 309 gpcr |= YU_GPCR_DPLX_DIS; 310 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 311 gpcr |= YU_GPCR_DUPLEX; 312 313 /* Disable flow control. */ 314 gpcr |= YU_GPCR_FCTL_DIS; 315 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 316 } 317 318 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 319 320 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 321 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 322 } 323 324 #define HASH_BITS 6 325 326 void 327 msk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 328 { 329 char *addr = addrv; 330 int base = XM_RXFILT_ENTRY(slot); 331 332 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 333 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 334 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 335 } 336 337 void 338 msk_setmulti(struct sk_if_softc *sc_if) 339 { 340 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 341 u_int32_t hashes[2] = { 0, 0 }; 342 int h; 343 struct ethercom *ec = &sc_if->sk_ethercom; 344 struct ether_multi *enm; 345 struct ether_multistep step; 346 u_int16_t reg; 347 348 /* First, zot all the existing filters. */ 349 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 350 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 351 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 352 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 353 354 355 /* Now program new ones. */ 356 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 357 reg |= YU_RCR_UFLEN; 358 allmulti: 359 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 360 if ((ifp->if_flags & IFF_PROMISC) != 0) 361 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 362 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 363 hashes[0] = 0xFFFFFFFF; 364 hashes[1] = 0xFFFFFFFF; 365 } 366 } else { 367 /* First find the tail of the list. */ 368 ETHER_FIRST_MULTI(step, ec, enm); 369 while (enm != NULL) { 370 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 371 ETHER_ADDR_LEN)) { 372 ifp->if_flags |= IFF_ALLMULTI; 373 goto allmulti; 374 } 375 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 376 ((1 << HASH_BITS) - 1); 377 if (h < 32) 378 hashes[0] |= (1 << h); 379 else 380 hashes[1] |= (1 << (h - 32)); 381 382 ETHER_NEXT_MULTI(step, enm); 383 } 384 reg |= YU_RCR_MUFLEN; 385 } 386 387 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 388 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 389 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 390 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 391 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 392 } 393 394 void 395 msk_setpromisc(struct sk_if_softc *sc_if) 396 { 397 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 398 399 if (ifp->if_flags & IFF_PROMISC) 400 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 401 YU_RCR_UFLEN | YU_RCR_MUFLEN); 402 else 403 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 404 YU_RCR_UFLEN | YU_RCR_MUFLEN); 405 } 406 407 int 408 msk_init_rx_ring(struct sk_if_softc *sc_if) 409 { 410 struct msk_chain_data *cd = &sc_if->sk_cdata; 411 struct msk_ring_data *rd = sc_if->sk_rdata; 412 int i, nexti; 413 414 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 415 416 for (i = 0; i < MSK_RX_RING_CNT; i++) { 417 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 418 if (i == (MSK_RX_RING_CNT - 1)) 419 nexti = 0; 420 else 421 nexti = i + 1; 422 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 423 } 424 425 for (i = 0; i < MSK_RX_RING_CNT; i++) { 426 if (msk_newbuf(sc_if, i, NULL, 427 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 428 aprint_error_dev(sc_if->sk_dev, "failed alloc of %dth mbuf\n", i); 429 return (ENOBUFS); 430 } 431 } 432 433 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 434 sc_if->sk_cdata.sk_rx_cons = 0; 435 436 return (0); 437 } 438 439 int 440 msk_init_tx_ring(struct sk_if_softc *sc_if) 441 { 442 struct sk_softc *sc = sc_if->sk_softc; 443 struct msk_chain_data *cd = &sc_if->sk_cdata; 444 struct msk_ring_data *rd = sc_if->sk_rdata; 445 bus_dmamap_t dmamap; 446 struct sk_txmap_entry *entry; 447 int i, nexti; 448 449 memset(sc_if->sk_rdata->sk_tx_ring, 0, 450 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 451 452 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 453 for (i = 0; i < MSK_TX_RING_CNT; i++) { 454 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 455 if (i == (MSK_TX_RING_CNT - 1)) 456 nexti = 0; 457 else 458 nexti = i + 1; 459 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 460 461 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 462 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 463 return (ENOBUFS); 464 465 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 466 if (!entry) { 467 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 468 return (ENOBUFS); 469 } 470 entry->dmamap = dmamap; 471 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 472 } 473 474 sc_if->sk_cdata.sk_tx_prod = 0; 475 sc_if->sk_cdata.sk_tx_cons = 0; 476 sc_if->sk_cdata.sk_tx_cnt = 0; 477 478 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 479 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 480 481 return (0); 482 } 483 484 int 485 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 486 bus_dmamap_t dmamap) 487 { 488 struct mbuf *m_new = NULL; 489 struct sk_chain *c; 490 struct msk_rx_desc *r; 491 492 if (m == NULL) { 493 void *buf = NULL; 494 495 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 496 if (m_new == NULL) 497 return (ENOBUFS); 498 499 /* Allocate the jumbo buffer */ 500 buf = msk_jalloc(sc_if); 501 if (buf == NULL) { 502 m_freem(m_new); 503 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 504 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 505 return (ENOBUFS); 506 } 507 508 /* Attach the buffer to the mbuf */ 509 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 510 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 511 } else { 512 /* 513 * We're re-using a previously allocated mbuf; 514 * be sure to re-init pointers and lengths to 515 * default values. 516 */ 517 m_new = m; 518 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 519 m_new->m_data = m_new->m_ext.ext_buf; 520 } 521 m_adj(m_new, ETHER_ALIGN); 522 523 c = &sc_if->sk_cdata.sk_rx_chain[i]; 524 r = c->sk_le; 525 c->sk_mbuf = m_new; 526 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 527 (((vaddr_t)m_new->m_data 528 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 529 r->sk_len = htole16(SK_JLEN); 530 r->sk_ctl = 0; 531 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 532 533 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 534 535 return (0); 536 } 537 538 /* 539 * Memory management for jumbo frames. 540 */ 541 542 int 543 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 544 { 545 struct sk_softc *sc = sc_if->sk_softc; 546 char *ptr, *kva; 547 bus_dma_segment_t seg; 548 int i, rseg, state, error; 549 struct sk_jpool_entry *entry; 550 551 state = error = 0; 552 553 /* Grab a big chunk o' storage. */ 554 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 555 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 556 aprint_error(": can't alloc rx buffers"); 557 return (ENOBUFS); 558 } 559 560 state = 1; 561 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, (void **)&kva, 562 BUS_DMA_NOWAIT)) { 563 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 564 error = ENOBUFS; 565 goto out; 566 } 567 568 state = 2; 569 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 570 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 571 aprint_error(": can't create dma map"); 572 error = ENOBUFS; 573 goto out; 574 } 575 576 state = 3; 577 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 578 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 579 aprint_error(": can't load dma map"); 580 error = ENOBUFS; 581 goto out; 582 } 583 584 state = 4; 585 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 586 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 587 588 LIST_INIT(&sc_if->sk_jfree_listhead); 589 LIST_INIT(&sc_if->sk_jinuse_listhead); 590 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 591 592 /* 593 * Now divide it up into 9K pieces and save the addresses 594 * in an array. 595 */ 596 ptr = sc_if->sk_cdata.sk_jumbo_buf; 597 for (i = 0; i < MSK_JSLOTS; i++) { 598 sc_if->sk_cdata.sk_jslots[i] = ptr; 599 ptr += SK_JLEN; 600 entry = malloc(sizeof(struct sk_jpool_entry), 601 M_DEVBUF, M_NOWAIT); 602 if (entry == NULL) { 603 sc_if->sk_cdata.sk_jumbo_buf = NULL; 604 aprint_error(": no memory for jumbo buffer queue!"); 605 error = ENOBUFS; 606 goto out; 607 } 608 entry->slot = i; 609 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 610 entry, jpool_entries); 611 } 612 out: 613 if (error != 0) { 614 switch (state) { 615 case 4: 616 bus_dmamap_unload(sc->sc_dmatag, 617 sc_if->sk_cdata.sk_rx_jumbo_map); 618 case 3: 619 bus_dmamap_destroy(sc->sc_dmatag, 620 sc_if->sk_cdata.sk_rx_jumbo_map); 621 case 2: 622 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 623 case 1: 624 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 625 break; 626 default: 627 break; 628 } 629 } 630 631 return (error); 632 } 633 634 /* 635 * Allocate a jumbo buffer. 636 */ 637 void * 638 msk_jalloc(struct sk_if_softc *sc_if) 639 { 640 struct sk_jpool_entry *entry; 641 642 mutex_enter(&sc_if->sk_jpool_mtx); 643 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 644 645 if (entry == NULL) { 646 mutex_exit(&sc_if->sk_jpool_mtx); 647 return NULL; 648 } 649 650 LIST_REMOVE(entry, jpool_entries); 651 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 652 mutex_exit(&sc_if->sk_jpool_mtx); 653 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 654 } 655 656 /* 657 * Release a jumbo buffer. 658 */ 659 void 660 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 661 { 662 struct sk_jpool_entry *entry; 663 struct sk_if_softc *sc; 664 int i; 665 666 /* Extract the softc struct pointer. */ 667 sc = (struct sk_if_softc *)arg; 668 669 if (sc == NULL) 670 panic("msk_jfree: can't find softc pointer!"); 671 672 /* calculate the slot this buffer belongs to */ 673 i = ((vaddr_t)buf 674 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 675 676 if ((i < 0) || (i >= MSK_JSLOTS)) 677 panic("msk_jfree: asked to free buffer that we don't manage!"); 678 679 mutex_enter(&sc->sk_jpool_mtx); 680 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 681 if (entry == NULL) 682 panic("msk_jfree: buffer not in use!"); 683 entry->slot = i; 684 LIST_REMOVE(entry, jpool_entries); 685 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 686 mutex_exit(&sc->sk_jpool_mtx); 687 688 if (__predict_true(m != NULL)) 689 pool_cache_put(mb_cache, m); 690 } 691 692 int 693 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 694 { 695 struct sk_if_softc *sc_if = ifp->if_softc; 696 int s, error = 0; 697 698 s = splnet(); 699 700 DPRINTFN(2, ("msk_ioctl ETHER\n")); 701 error = ether_ioctl(ifp, cmd, data); 702 703 if (error == ENETRESET) { 704 error = 0; 705 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 706 ; 707 else if (ifp->if_flags & IFF_RUNNING) { 708 /* 709 * Multicast list has changed; set the hardware 710 * filter accordingly. 711 */ 712 msk_setmulti(sc_if); 713 } 714 } 715 716 splx(s); 717 return (error); 718 } 719 720 void 721 msk_update_int_mod(struct sk_softc *sc, int verbose) 722 { 723 u_int32_t imtimer_ticks; 724 725 /* 726 * Configure interrupt moderation. The moderation timer 727 * defers interrupts specified in the interrupt moderation 728 * timer mask based on the timeout specified in the interrupt 729 * moderation timer init register. Each bit in the timer 730 * register represents one tick, so to specify a timeout in 731 * microseconds, we have to multiply by the correct number of 732 * ticks-per-microsecond. 733 */ 734 switch (sc->sk_type) { 735 case SK_YUKON_EC: 736 case SK_YUKON_EC_U: 737 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 738 break; 739 case SK_YUKON_FE: 740 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 741 break; 742 case SK_YUKON_XL: 743 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 744 break; 745 default: 746 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 747 } 748 if (verbose) 749 aprint_verbose_dev(sc->sk_dev, 750 "interrupt moderation is %d us\n", sc->sk_int_mod); 751 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 752 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 753 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 754 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 755 sc->sk_int_mod_pending = 0; 756 } 757 758 static int 759 msk_lookup(const struct pci_attach_args *pa) 760 { 761 const struct msk_product *pmsk; 762 763 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 764 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 765 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 766 return 1; 767 } 768 return 0; 769 } 770 771 /* 772 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 773 * IDs against our list and return a device name if we find a match. 774 */ 775 int 776 mskc_probe(device_t parent, cfdata_t match, void *aux) 777 { 778 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 779 780 return msk_lookup(pa); 781 } 782 783 /* 784 * Force the GEnesis into reset, then bring it out of reset. 785 */ 786 void msk_reset(struct sk_softc *sc) 787 { 788 u_int32_t imtimer_ticks, reg1; 789 int reg; 790 791 DPRINTFN(2, ("msk_reset\n")); 792 793 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 794 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 795 796 DELAY(1000); 797 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 798 DELAY(2); 799 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 800 sk_win_write_1(sc, SK_TESTCTL1, 2); 801 802 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 803 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 804 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 805 else 806 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 807 808 if (sc->sk_type == SK_YUKON_EC_U) { 809 uint32_t our; 810 811 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 812 813 /* enable all clocks. */ 814 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 815 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 816 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 817 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 818 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 819 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 820 /* Set all bits to 0 except bits 15..12 */ 821 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 822 /* Set to default value */ 823 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 824 } 825 826 /* release PHY from PowerDown/Coma mode. */ 827 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 828 829 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 830 sk_win_write_1(sc, SK_Y2_CLKGATE, 831 SK_Y2_CLKGATE_LINK1_GATE_DIS | 832 SK_Y2_CLKGATE_LINK2_GATE_DIS | 833 SK_Y2_CLKGATE_LINK1_CORE_DIS | 834 SK_Y2_CLKGATE_LINK2_CORE_DIS | 835 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 836 else 837 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 838 839 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 840 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 841 DELAY(1000); 842 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 843 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 844 845 sk_win_write_1(sc, SK_TESTCTL1, 1); 846 847 DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 848 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n", 849 CSR_READ_2(sc, SK_LINK_CTRL))); 850 851 /* Disable ASF */ 852 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 853 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 854 855 /* Clear I2C IRQ noise */ 856 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 857 858 /* Disable hardware timer */ 859 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 860 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 861 862 /* Disable descriptor polling */ 863 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 864 865 /* Disable time stamps */ 866 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 867 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 868 869 /* Enable RAM interface */ 870 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 871 for (reg = SK_TO0;reg <= SK_TO11; reg++) 872 sk_win_write_1(sc, reg, 36); 873 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 874 for (reg = SK_TO0;reg <= SK_TO11; reg++) 875 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 876 877 /* 878 * Configure interrupt moderation. The moderation timer 879 * defers interrupts specified in the interrupt moderation 880 * timer mask based on the timeout specified in the interrupt 881 * moderation timer init register. Each bit in the timer 882 * register represents one tick, so to specify a timeout in 883 * microseconds, we have to multiply by the correct number of 884 * ticks-per-microsecond. 885 */ 886 switch (sc->sk_type) { 887 case SK_YUKON_EC: 888 case SK_YUKON_EC_U: 889 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 890 break; 891 case SK_YUKON_FE: 892 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 893 break; 894 case SK_YUKON_XL: 895 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 896 break; 897 default: 898 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 899 } 900 901 /* Reset status ring. */ 902 memset(sc->sk_status_ring, 0, 903 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 904 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 905 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 906 sc->sk_status_idx = 0; 907 sc->sk_status_own_idx = 0; 908 909 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 910 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 911 912 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 913 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 914 sc->sk_status_map->dm_segs[0].ds_addr); 915 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 916 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 917 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { 918 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 919 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 920 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 921 } else { 922 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 923 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 924 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 925 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); 926 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 927 } 928 929 #if 0 930 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 931 #endif 932 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 933 934 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 935 936 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 937 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 938 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 939 940 msk_update_int_mod(sc, 0); 941 } 942 943 int 944 msk_probe(device_t parent, cfdata_t match, void *aux) 945 { 946 struct skc_attach_args *sa = aux; 947 948 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 949 return (0); 950 951 switch (sa->skc_type) { 952 case SK_YUKON_XL: 953 case SK_YUKON_EC_U: 954 case SK_YUKON_EC: 955 case SK_YUKON_FE: 956 return (1); 957 } 958 959 return (0); 960 } 961 962 static bool 963 msk_resume(device_t dv, const pmf_qual_t *qual) 964 { 965 struct sk_if_softc *sc_if = device_private(dv); 966 967 msk_init_yukon(sc_if); 968 return true; 969 } 970 971 /* 972 * Each XMAC chip is attached as a separate logical IP interface. 973 * Single port cards will have only one logical interface of course. 974 */ 975 void 976 msk_attach(device_t parent, device_t self, void *aux) 977 { 978 struct sk_if_softc *sc_if = device_private(self); 979 struct sk_softc *sc = device_private(parent); 980 struct skc_attach_args *sa = aux; 981 struct ifnet *ifp; 982 void *kva; 983 bus_dma_segment_t seg; 984 int i, rseg; 985 u_int32_t chunk, val; 986 987 sc_if->sk_dev = self; 988 sc_if->sk_port = sa->skc_port; 989 sc_if->sk_softc = sc; 990 sc->sk_if[sa->skc_port] = sc_if; 991 992 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 993 994 /* 995 * Get station address for this interface. Note that 996 * dual port cards actually come with three station 997 * addresses: one for each port, plus an extra. The 998 * extra one is used by the SysKonnect driver software 999 * as a 'virtual' station address for when both ports 1000 * are operating in failover mode. Currently we don't 1001 * use this extra address. 1002 */ 1003 for (i = 0; i < ETHER_ADDR_LEN; i++) 1004 sc_if->sk_enaddr[i] = 1005 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1006 1007 aprint_normal(": Ethernet address %s\n", 1008 ether_sprintf(sc_if->sk_enaddr)); 1009 1010 /* 1011 * Set up RAM buffer addresses. The NIC will have a certain 1012 * amount of SRAM on it, somewhere between 512K and 2MB. We 1013 * need to divide this up a) between the transmitter and 1014 * receiver and b) between the two XMACs, if this is a 1015 * dual port NIC. Our algorithm is to divide up the memory 1016 * evenly so that everyone gets a fair share. 1017 * 1018 * Just to be contrary, Yukon2 appears to have separate memory 1019 * for each MAC. 1020 */ 1021 chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3; 1022 val = sc->sk_rboff / sizeof(u_int64_t); 1023 sc_if->sk_rx_ramstart = val; 1024 val += (chunk / sizeof(u_int64_t)); 1025 sc_if->sk_rx_ramend = val - 1; 1026 chunk = sc->sk_ramsize - chunk; 1027 sc_if->sk_tx_ramstart = val; 1028 val += (chunk / sizeof(u_int64_t)); 1029 sc_if->sk_tx_ramend = val - 1; 1030 1031 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1032 " tx_ramstart=%#x tx_ramend=%#x\n", 1033 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1034 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1035 1036 /* Allocate the descriptor queues. */ 1037 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1038 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1039 aprint_error(": can't alloc rx buffers\n"); 1040 goto fail; 1041 } 1042 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1043 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1044 aprint_error(": can't map dma buffers (%zu bytes)\n", 1045 sizeof(struct msk_ring_data)); 1046 goto fail_1; 1047 } 1048 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1049 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1050 &sc_if->sk_ring_map)) { 1051 aprint_error(": can't create dma map\n"); 1052 goto fail_2; 1053 } 1054 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1055 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1056 aprint_error(": can't load dma map\n"); 1057 goto fail_3; 1058 } 1059 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1060 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1061 1062 ifp = &sc_if->sk_ethercom.ec_if; 1063 /* Try to allocate memory for jumbo buffers. */ 1064 if (msk_alloc_jumbo_mem(sc_if)) { 1065 aprint_error(": jumbo buffer allocation failed\n"); 1066 goto fail_3; 1067 } 1068 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1069 if (sc->sk_type != SK_YUKON_FE) 1070 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1071 1072 ifp->if_softc = sc_if; 1073 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1074 ifp->if_ioctl = msk_ioctl; 1075 ifp->if_start = msk_start; 1076 ifp->if_stop = msk_stop; 1077 ifp->if_init = msk_init; 1078 ifp->if_watchdog = msk_watchdog; 1079 ifp->if_baudrate = 1000000000; 1080 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1081 IFQ_SET_READY(&ifp->if_snd); 1082 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1083 1084 /* 1085 * Do miibus setup. 1086 */ 1087 msk_init_yukon(sc_if); 1088 1089 DPRINTFN(2, ("msk_attach: 1\n")); 1090 1091 sc_if->sk_mii.mii_ifp = ifp; 1092 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1093 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1094 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1095 1096 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1097 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1098 ether_mediachange, ether_mediastatus); 1099 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1100 MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG); 1101 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1102 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1103 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1104 0, NULL); 1105 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1106 } else 1107 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1108 1109 callout_init(&sc_if->sk_tick_ch, 0); 1110 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1111 callout_schedule(&sc_if->sk_tick_ch, hz); 1112 1113 /* 1114 * Call MI attach routines. 1115 */ 1116 if_attach(ifp); 1117 ether_ifattach(ifp, sc_if->sk_enaddr); 1118 1119 if (pmf_device_register(self, NULL, msk_resume)) 1120 pmf_class_network_register(self, ifp); 1121 else 1122 aprint_error_dev(self, "couldn't establish power handler\n"); 1123 1124 #if NRND > 0 1125 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1126 RND_TYPE_NET, 0); 1127 #endif 1128 1129 DPRINTFN(2, ("msk_attach: end\n")); 1130 return; 1131 1132 fail_3: 1133 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1134 fail_2: 1135 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1136 fail_1: 1137 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1138 fail: 1139 sc->sk_if[sa->skc_port] = NULL; 1140 } 1141 1142 int 1143 mskcprint(void *aux, const char *pnp) 1144 { 1145 struct skc_attach_args *sa = aux; 1146 1147 if (pnp) 1148 aprint_normal("sk port %c at %s", 1149 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1150 else 1151 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1152 return (UNCONF); 1153 } 1154 1155 /* 1156 * Attach the interface. Allocate softc structures, do ifmedia 1157 * setup and ethernet/BPF attach. 1158 */ 1159 void 1160 mskc_attach(device_t parent, device_t self, void *aux) 1161 { 1162 struct sk_softc *sc = device_private(self); 1163 struct pci_attach_args *pa = aux; 1164 struct skc_attach_args skca; 1165 pci_chipset_tag_t pc = pa->pa_pc; 1166 pcireg_t command, memtype; 1167 pci_intr_handle_t ih; 1168 const char *intrstr = NULL; 1169 bus_size_t size; 1170 int rc, sk_nodenum; 1171 u_int8_t hw, skrs; 1172 const char *revstr = NULL; 1173 const struct sysctlnode *node; 1174 void *kva; 1175 bus_dma_segment_t seg; 1176 int rseg; 1177 1178 DPRINTFN(2, ("begin mskc_attach\n")); 1179 1180 sc->sk_dev = self; 1181 /* 1182 * Handle power management nonsense. 1183 */ 1184 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1185 1186 if (command == 0x01) { 1187 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1188 if (command & SK_PSTATE_MASK) { 1189 u_int32_t iobase, membase, irq; 1190 1191 /* Save important PCI config data. */ 1192 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1193 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1194 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1195 1196 /* Reset the power state. */ 1197 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1198 "mode -- setting to D0\n", 1199 command & SK_PSTATE_MASK); 1200 command &= 0xFFFFFFFC; 1201 pci_conf_write(pc, pa->pa_tag, 1202 SK_PCI_PWRMGMTCTRL, command); 1203 1204 /* Restore PCI config data. */ 1205 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1206 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1207 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1208 } 1209 } 1210 1211 /* 1212 * Map control/status registers. 1213 */ 1214 1215 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1216 switch (memtype) { 1217 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1218 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1219 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1220 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1221 NULL, &size) == 0) { 1222 break; 1223 } 1224 default: 1225 aprint_error(": can't map mem space\n"); 1226 return; 1227 } 1228 1229 sc->sc_dmatag = pa->pa_dmat; 1230 1231 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1232 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1233 1234 /* bail out here if chip is not recognized */ 1235 if (!(SK_IS_YUKON2(sc))) { 1236 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1237 goto fail_1; 1238 } 1239 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1240 1241 /* Allocate interrupt */ 1242 if (pci_intr_map(pa, &ih)) { 1243 aprint_error(": couldn't map interrupt\n"); 1244 goto fail_1; 1245 } 1246 1247 intrstr = pci_intr_string(pc, ih); 1248 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1249 if (sc->sk_intrhand == NULL) { 1250 aprint_error(": couldn't establish interrupt"); 1251 if (intrstr != NULL) 1252 aprint_error(" at %s", intrstr); 1253 aprint_error("\n"); 1254 goto fail_1; 1255 } 1256 1257 if (bus_dmamem_alloc(sc->sc_dmatag, 1258 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1259 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1260 aprint_error(": can't alloc status buffers\n"); 1261 goto fail_2; 1262 } 1263 1264 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1265 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1266 &kva, BUS_DMA_NOWAIT)) { 1267 aprint_error(": can't map dma buffers (%zu bytes)\n", 1268 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1269 goto fail_3; 1270 } 1271 if (bus_dmamap_create(sc->sc_dmatag, 1272 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1273 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1274 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1275 aprint_error(": can't create dma map\n"); 1276 goto fail_4; 1277 } 1278 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1279 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1280 NULL, BUS_DMA_NOWAIT)) { 1281 aprint_error(": can't load dma map\n"); 1282 goto fail_5; 1283 } 1284 sc->sk_status_ring = (struct msk_status_desc *)kva; 1285 1286 1287 sc->sk_int_mod = SK_IM_DEFAULT; 1288 sc->sk_int_mod_pending = 0; 1289 1290 /* Reset the adapter. */ 1291 msk_reset(sc); 1292 1293 skrs = sk_win_read_1(sc, SK_EPROM0); 1294 if (skrs == 0x00) 1295 sc->sk_ramsize = 0x20000; 1296 else 1297 sc->sk_ramsize = skrs * (1<<12); 1298 sc->sk_rboff = SK_RBOFF_0; 1299 1300 DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n", 1301 sc->sk_ramsize, sc->sk_ramsize / 1024, 1302 sc->sk_rboff)); 1303 1304 switch (sc->sk_type) { 1305 case SK_YUKON_XL: 1306 sc->sk_name = "Yukon-2 XL"; 1307 break; 1308 case SK_YUKON_EC_U: 1309 sc->sk_name = "Yukon-2 EC Ultra"; 1310 break; 1311 case SK_YUKON_EC: 1312 sc->sk_name = "Yukon-2 EC"; 1313 break; 1314 case SK_YUKON_FE: 1315 sc->sk_name = "Yukon-2 FE"; 1316 break; 1317 default: 1318 sc->sk_name = "Yukon (Unknown)"; 1319 } 1320 1321 if (sc->sk_type == SK_YUKON_XL) { 1322 switch (sc->sk_rev) { 1323 case SK_YUKON_XL_REV_A0: 1324 sc->sk_workaround = 0; 1325 revstr = "A0"; 1326 break; 1327 case SK_YUKON_XL_REV_A1: 1328 sc->sk_workaround = SK_WA_4109; 1329 revstr = "A1"; 1330 break; 1331 case SK_YUKON_XL_REV_A2: 1332 sc->sk_workaround = SK_WA_4109; 1333 revstr = "A2"; 1334 break; 1335 case SK_YUKON_XL_REV_A3: 1336 sc->sk_workaround = SK_WA_4109; 1337 revstr = "A3"; 1338 break; 1339 default: 1340 sc->sk_workaround = 0; 1341 break; 1342 } 1343 } 1344 1345 if (sc->sk_type == SK_YUKON_EC) { 1346 switch (sc->sk_rev) { 1347 case SK_YUKON_EC_REV_A1: 1348 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; 1349 revstr = "A1"; 1350 break; 1351 case SK_YUKON_EC_REV_A2: 1352 sc->sk_workaround = SK_WA_4109; 1353 revstr = "A2"; 1354 break; 1355 case SK_YUKON_EC_REV_A3: 1356 sc->sk_workaround = SK_WA_4109; 1357 revstr = "A3"; 1358 break; 1359 default: 1360 sc->sk_workaround = 0; 1361 break; 1362 } 1363 } 1364 1365 if (sc->sk_type == SK_YUKON_FE) { 1366 sc->sk_workaround = SK_WA_4109; 1367 switch (sc->sk_rev) { 1368 case SK_YUKON_FE_REV_A1: 1369 revstr = "A1"; 1370 break; 1371 case SK_YUKON_FE_REV_A2: 1372 revstr = "A2"; 1373 break; 1374 default: 1375 sc->sk_workaround = 0; 1376 break; 1377 } 1378 } 1379 1380 if (sc->sk_type == SK_YUKON_EC_U) { 1381 sc->sk_workaround = SK_WA_4109; 1382 switch (sc->sk_rev) { 1383 case SK_YUKON_EC_U_REV_A0: 1384 revstr = "A0"; 1385 break; 1386 case SK_YUKON_EC_U_REV_A1: 1387 revstr = "A1"; 1388 break; 1389 case SK_YUKON_EC_U_REV_B0: 1390 revstr = "B0"; 1391 break; 1392 default: 1393 sc->sk_workaround = 0; 1394 break; 1395 } 1396 } 1397 1398 /* Announce the product name. */ 1399 aprint_normal(", %s", sc->sk_name); 1400 if (revstr != NULL) 1401 aprint_normal(" rev. %s", revstr); 1402 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1403 1404 sc->sk_macs = 1; 1405 1406 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1407 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1408 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1409 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1410 sc->sk_macs++; 1411 } 1412 1413 skca.skc_port = SK_PORT_A; 1414 skca.skc_type = sc->sk_type; 1415 skca.skc_rev = sc->sk_rev; 1416 (void)config_found(sc->sk_dev, &skca, mskcprint); 1417 1418 if (sc->sk_macs > 1) { 1419 skca.skc_port = SK_PORT_B; 1420 skca.skc_type = sc->sk_type; 1421 skca.skc_rev = sc->sk_rev; 1422 (void)config_found(sc->sk_dev, &skca, mskcprint); 1423 } 1424 1425 /* Turn on the 'driver is loaded' LED. */ 1426 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1427 1428 /* skc sysctl setup */ 1429 1430 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1431 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1432 SYSCTL_DESCR("mskc per-controller controls"), 1433 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1434 CTL_EOL)) != 0) { 1435 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1436 goto fail_6; 1437 } 1438 1439 sk_nodenum = node->sysctl_num; 1440 1441 /* interrupt moderation time in usecs */ 1442 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1443 CTLFLAG_READWRITE, 1444 CTLTYPE_INT, "int_mod", 1445 SYSCTL_DESCR("msk interrupt moderation timer"), 1446 msk_sysctl_handler, 0, sc, 1447 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1448 CTL_EOL)) != 0) { 1449 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1450 goto fail_6; 1451 } 1452 1453 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1454 aprint_error_dev(self, "couldn't establish power handler\n"); 1455 1456 return; 1457 1458 fail_6: 1459 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1460 fail_5: 1461 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1462 fail_4: 1463 bus_dmamem_unmap(sc->sc_dmatag, kva, 1464 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1465 fail_3: 1466 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1467 fail_2: 1468 pci_intr_disestablish(pc, sc->sk_intrhand); 1469 fail_1: 1470 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1471 } 1472 1473 int 1474 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1475 { 1476 struct sk_softc *sc = sc_if->sk_softc; 1477 struct msk_tx_desc *f = NULL; 1478 u_int32_t frag, cur; 1479 int i; 1480 struct sk_txmap_entry *entry; 1481 bus_dmamap_t txmap; 1482 1483 DPRINTFN(2, ("msk_encap\n")); 1484 1485 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1486 if (entry == NULL) { 1487 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1488 return (ENOBUFS); 1489 } 1490 txmap = entry->dmamap; 1491 1492 cur = frag = *txidx; 1493 1494 #ifdef MSK_DEBUG 1495 if (mskdebug >= 2) 1496 msk_dump_mbuf(m_head); 1497 #endif 1498 1499 /* 1500 * Start packing the mbufs in this chain into 1501 * the fragment pointers. Stop when we run out 1502 * of fragments or hit the end of the mbuf chain. 1503 */ 1504 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1505 BUS_DMA_NOWAIT)) { 1506 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1507 return (ENOBUFS); 1508 } 1509 1510 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1511 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1512 bus_dmamap_unload(sc->sc_dmatag, txmap); 1513 return (ENOBUFS); 1514 } 1515 1516 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1517 1518 /* Sync the DMA map. */ 1519 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1520 BUS_DMASYNC_PREWRITE); 1521 1522 for (i = 0; i < txmap->dm_nsegs; i++) { 1523 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1524 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1525 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1526 f->sk_ctl = 0; 1527 if (i == 0) 1528 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1529 else 1530 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1531 cur = frag; 1532 SK_INC(frag, MSK_TX_RING_CNT); 1533 } 1534 1535 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1536 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1537 1538 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1539 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1540 1541 /* Sync descriptors before handing to chip */ 1542 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1543 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1544 1545 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1546 1547 /* Sync first descriptor to hand it off */ 1548 MSK_CDTXSYNC(sc_if, *txidx, 1, 1549 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1550 1551 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1552 1553 #ifdef MSK_DEBUG 1554 if (mskdebug >= 2) { 1555 struct msk_tx_desc *le; 1556 u_int32_t idx; 1557 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1558 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1559 msk_dump_txdesc(le, idx); 1560 } 1561 } 1562 #endif 1563 1564 *txidx = frag; 1565 1566 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1567 1568 return (0); 1569 } 1570 1571 void 1572 msk_start(struct ifnet *ifp) 1573 { 1574 struct sk_if_softc *sc_if = ifp->if_softc; 1575 struct mbuf *m_head = NULL; 1576 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1577 int pkts = 0; 1578 1579 DPRINTFN(2, ("msk_start\n")); 1580 1581 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1582 IFQ_POLL(&ifp->if_snd, m_head); 1583 if (m_head == NULL) 1584 break; 1585 1586 /* 1587 * Pack the data into the transmit ring. If we 1588 * don't have room, set the OACTIVE flag and wait 1589 * for the NIC to drain the ring. 1590 */ 1591 if (msk_encap(sc_if, m_head, &idx)) { 1592 ifp->if_flags |= IFF_OACTIVE; 1593 break; 1594 } 1595 1596 /* now we are committed to transmit the packet */ 1597 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1598 pkts++; 1599 1600 /* 1601 * If there's a BPF listener, bounce a copy of this frame 1602 * to him. 1603 */ 1604 bpf_mtap(ifp, m_head); 1605 } 1606 if (pkts == 0) 1607 return; 1608 1609 /* Transmit */ 1610 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1611 sc_if->sk_cdata.sk_tx_prod = idx; 1612 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1613 1614 /* Set a timeout in case the chip goes out to lunch. */ 1615 ifp->if_timer = 5; 1616 } 1617 } 1618 1619 void 1620 msk_watchdog(struct ifnet *ifp) 1621 { 1622 struct sk_if_softc *sc_if = ifp->if_softc; 1623 u_int32_t reg; 1624 int idx; 1625 1626 /* 1627 * Reclaim first as there is a possibility of losing Tx completion 1628 * interrupts. 1629 */ 1630 if (sc_if->sk_port == SK_PORT_A) 1631 reg = SK_STAT_BMU_TXA1_RIDX; 1632 else 1633 reg = SK_STAT_BMU_TXA2_RIDX; 1634 1635 idx = sk_win_read_2(sc_if->sk_softc, reg); 1636 if (sc_if->sk_cdata.sk_tx_cons != idx) { 1637 msk_txeof(sc_if, idx); 1638 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1639 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1640 1641 ifp->if_oerrors++; 1642 1643 /* XXX Resets both ports; we shouldn't do that. */ 1644 msk_reset(sc_if->sk_softc); 1645 msk_init(ifp); 1646 } 1647 } 1648 } 1649 1650 static bool 1651 mskc_suspend(device_t dv, const pmf_qual_t *qual) 1652 { 1653 struct sk_softc *sc = device_private(dv); 1654 1655 DPRINTFN(2, ("mskc_suspend\n")); 1656 1657 /* Turn off the 'driver is loaded' LED. */ 1658 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1659 1660 return true; 1661 } 1662 1663 static bool 1664 mskc_resume(device_t dv, const pmf_qual_t *qual) 1665 { 1666 struct sk_softc *sc = device_private(dv); 1667 1668 DPRINTFN(2, ("mskc_resume\n")); 1669 1670 msk_reset(sc); 1671 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1672 1673 return true; 1674 } 1675 1676 __inline int 1677 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1678 { 1679 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1680 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1681 YU_RXSTAT_JABBER)) != 0 || 1682 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1683 YU_RXSTAT_BYTES(stat) != len) 1684 return (0); 1685 1686 return (1); 1687 } 1688 1689 void 1690 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1691 { 1692 struct sk_softc *sc = sc_if->sk_softc; 1693 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1694 struct mbuf *m; 1695 struct sk_chain *cur_rx; 1696 int cur, total_len = len; 1697 bus_dmamap_t dmamap; 1698 1699 DPRINTFN(2, ("msk_rxeof\n")); 1700 1701 cur = sc_if->sk_cdata.sk_rx_cons; 1702 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1703 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1704 1705 /* Sync the descriptor */ 1706 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1707 1708 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1709 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1710 1711 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1712 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1713 1714 m = cur_rx->sk_mbuf; 1715 cur_rx->sk_mbuf = NULL; 1716 1717 if (total_len < SK_MIN_FRAMELEN || 1718 total_len > ETHER_MAX_LEN_JUMBO || 1719 msk_rxvalid(sc, rxstat, total_len) == 0) { 1720 ifp->if_ierrors++; 1721 msk_newbuf(sc_if, cur, m, dmamap); 1722 return; 1723 } 1724 1725 /* 1726 * Try to allocate a new jumbo buffer. If that fails, copy the 1727 * packet to mbufs and put the jumbo buffer back in the ring 1728 * so it can be re-used. If allocating mbufs fails, then we 1729 * have to drop the packet. 1730 */ 1731 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1732 struct mbuf *m0; 1733 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1734 total_len + ETHER_ALIGN, 0, ifp, NULL); 1735 msk_newbuf(sc_if, cur, m, dmamap); 1736 if (m0 == NULL) { 1737 ifp->if_ierrors++; 1738 return; 1739 } 1740 m_adj(m0, ETHER_ALIGN); 1741 m = m0; 1742 } else { 1743 m->m_pkthdr.rcvif = ifp; 1744 m->m_pkthdr.len = m->m_len = total_len; 1745 } 1746 1747 ifp->if_ipackets++; 1748 1749 bpf_mtap(ifp, m); 1750 1751 /* pass it on. */ 1752 (*ifp->if_input)(ifp, m); 1753 } 1754 1755 void 1756 msk_txeof(struct sk_if_softc *sc_if, int idx) 1757 { 1758 struct sk_softc *sc = sc_if->sk_softc; 1759 struct msk_tx_desc *cur_tx; 1760 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1761 u_int32_t sk_ctl; 1762 struct sk_txmap_entry *entry; 1763 int cons, prog; 1764 1765 DPRINTFN(2, ("msk_txeof\n")); 1766 1767 /* 1768 * Go through our tx ring and free mbufs for those 1769 * frames that have been sent. 1770 */ 1771 cons = sc_if->sk_cdata.sk_tx_cons; 1772 prog = 0; 1773 while (cons != idx) { 1774 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 1775 break; 1776 prog++; 1777 cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons]; 1778 1779 MSK_CDTXSYNC(sc_if, cons, 1, 1780 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1781 sk_ctl = cur_tx->sk_ctl; 1782 MSK_CDTXSYNC(sc_if, cons, 1, BUS_DMASYNC_PREREAD); 1783 #ifdef MSK_DEBUG 1784 if (mskdebug >= 2) 1785 msk_dump_txdesc(cur_tx, cons); 1786 #endif 1787 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1788 ifp->if_opackets++; 1789 if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) { 1790 entry = sc_if->sk_cdata.sk_tx_map[cons]; 1791 1792 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1793 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1794 1795 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1796 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1797 link); 1798 sc_if->sk_cdata.sk_tx_map[cons] = NULL; 1799 m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf); 1800 sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL; 1801 } 1802 sc_if->sk_cdata.sk_tx_cnt--; 1803 SK_INC(cons, MSK_TX_RING_CNT); 1804 } 1805 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1806 1807 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1808 ifp->if_flags &= ~IFF_OACTIVE; 1809 1810 if (prog > 0) 1811 sc_if->sk_cdata.sk_tx_cons = cons; 1812 } 1813 1814 void 1815 msk_tick(void *xsc_if) 1816 { 1817 struct sk_if_softc *sc_if = xsc_if; 1818 struct mii_data *mii = &sc_if->sk_mii; 1819 uint16_t gpsr; 1820 int s; 1821 1822 s = splnet(); 1823 gpsr = SK_YU_READ_2(sc_if, YUKON_GPSR); 1824 if ((gpsr & YU_GPSR_MII_PHY_STC) != 0) { 1825 SK_YU_WRITE_2(sc_if, YUKON_GPSR, YU_GPSR_MII_PHY_STC); 1826 mii_tick(mii); 1827 } 1828 splx(s); 1829 1830 callout_schedule(&sc_if->sk_tick_ch, hz); 1831 } 1832 1833 void 1834 msk_intr_yukon(struct sk_if_softc *sc_if) 1835 { 1836 u_int8_t status; 1837 1838 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1839 /* RX overrun */ 1840 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1841 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1842 SK_RFCTL_RX_FIFO_OVER); 1843 } 1844 /* TX underrun */ 1845 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1846 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1847 SK_TFCTL_TX_FIFO_UNDER); 1848 } 1849 1850 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1851 } 1852 1853 int 1854 msk_intr(void *xsc) 1855 { 1856 struct sk_softc *sc = xsc; 1857 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1858 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1859 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1860 int claimed = 0; 1861 u_int32_t status; 1862 uint32_t st_status; 1863 uint16_t st_len; 1864 uint8_t st_opcode, st_link; 1865 struct msk_status_desc *cur_st; 1866 1867 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1868 if (status == 0) { 1869 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1870 return (0); 1871 } 1872 1873 status = CSR_READ_4(sc, SK_ISR); 1874 1875 if (sc_if0 != NULL) 1876 ifp0 = &sc_if0->sk_ethercom.ec_if; 1877 if (sc_if1 != NULL) 1878 ifp1 = &sc_if1->sk_ethercom.ec_if; 1879 1880 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1881 (ifp0->if_flags & IFF_RUNNING)) { 1882 msk_intr_yukon(sc_if0); 1883 } 1884 1885 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1886 (ifp1->if_flags & IFF_RUNNING)) { 1887 msk_intr_yukon(sc_if1); 1888 } 1889 1890 for (;;) { 1891 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1892 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1893 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1894 st_opcode = cur_st->sk_opcode; 1895 if ((st_opcode & SK_Y2_STOPC_OWN) == 0) { 1896 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1897 BUS_DMASYNC_PREREAD); 1898 break; 1899 } 1900 st_status = le32toh(cur_st->sk_status); 1901 st_len = le16toh(cur_st->sk_len); 1902 st_link = cur_st->sk_link; 1903 st_opcode &= ~SK_Y2_STOPC_OWN; 1904 1905 switch (st_opcode) { 1906 case SK_Y2_STOPC_RXSTAT: 1907 msk_rxeof(sc->sk_if[st_link], st_len, st_status); 1908 SK_IF_WRITE_2(sc->sk_if[st_link], 0, 1909 SK_RXQ1_Y2_PREF_PUTIDX, 1910 sc->sk_if[st_link]->sk_cdata.sk_rx_prod); 1911 break; 1912 case SK_Y2_STOPC_TXSTAT: 1913 if (sc_if0) 1914 msk_txeof(sc_if0, st_status 1915 & SK_Y2_ST_TXA1_MSKL); 1916 if (sc_if1) 1917 msk_txeof(sc_if1, 1918 ((st_status & SK_Y2_ST_TXA2_MSKL) 1919 >> SK_Y2_ST_TXA2_SHIFTL) 1920 | ((st_len & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH)); 1921 break; 1922 default: 1923 aprint_error("opcode=0x%x\n", st_opcode); 1924 break; 1925 } 1926 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1927 } 1928 1929 #define MSK_STATUS_RING_OWN_CNT(sc) \ 1930 (((sc)->sk_status_idx + MSK_STATUS_RING_CNT - \ 1931 (sc)->sk_status_own_idx) % MSK_STATUS_RING_CNT) 1932 1933 while (MSK_STATUS_RING_OWN_CNT(sc) > MSK_STATUS_RING_CNT / 2) { 1934 cur_st = &sc->sk_status_ring[sc->sk_status_own_idx]; 1935 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1936 MSK_CDSTSYNC(sc, sc->sk_status_own_idx, 1937 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1938 1939 SK_INC(sc->sk_status_own_idx, MSK_STATUS_RING_CNT); 1940 } 1941 1942 if (status & SK_Y2_IMR_BMU) { 1943 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1944 claimed = 1; 1945 } 1946 1947 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1948 1949 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1950 msk_start(ifp0); 1951 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1952 msk_start(ifp1); 1953 1954 #if NRND > 0 1955 if (RND_ENABLED(&sc->rnd_source)) 1956 rnd_add_uint32(&sc->rnd_source, status); 1957 #endif 1958 1959 if (sc->sk_int_mod_pending) 1960 msk_update_int_mod(sc, 1); 1961 1962 return claimed; 1963 } 1964 1965 void 1966 msk_init_yukon(struct sk_if_softc *sc_if) 1967 { 1968 u_int32_t v; 1969 u_int16_t reg; 1970 struct sk_softc *sc; 1971 int i; 1972 1973 sc = sc_if->sk_softc; 1974 1975 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1976 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1977 1978 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1979 1980 /* GMAC and GPHY Reset */ 1981 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1982 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1983 DELAY(1000); 1984 1985 DPRINTFN(6, ("msk_init_yukon: 2\n")); 1986 1987 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1988 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1989 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1990 1991 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1992 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1993 1994 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1995 1996 /* unused read of the interrupt source register */ 1997 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1998 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1999 2000 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2001 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2002 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2003 2004 /* MIB Counter Clear Mode set */ 2005 reg |= YU_PAR_MIB_CLR; 2006 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2007 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2008 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2009 2010 /* MIB Counter Clear Mode clear */ 2011 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2012 reg &= ~YU_PAR_MIB_CLR; 2013 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2014 2015 /* receive control reg */ 2016 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2017 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2018 2019 /* transmit control register */ 2020 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2021 2022 /* transmit flow control register */ 2023 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2024 2025 /* transmit parameter register */ 2026 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2027 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2028 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2029 2030 /* serial mode register */ 2031 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2032 reg = YU_SMR_DATA_BLIND(0x1c) | 2033 YU_SMR_MFL_VLAN | 2034 YU_SMR_IPG_DATA(0x1e); 2035 2036 if (sc->sk_type != SK_YUKON_FE) 2037 reg |= YU_SMR_MFL_JUMBO; 2038 2039 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2040 2041 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2042 /* Setup Yukon's address */ 2043 for (i = 0; i < 3; i++) { 2044 /* Write Source Address 1 (unicast filter) */ 2045 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2046 sc_if->sk_enaddr[i * 2] | 2047 sc_if->sk_enaddr[i * 2 + 1] << 8); 2048 } 2049 2050 for (i = 0; i < 3; i++) { 2051 reg = sk_win_read_2(sc_if->sk_softc, 2052 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2053 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2054 } 2055 2056 /* Set promiscuous mode */ 2057 msk_setpromisc(sc_if); 2058 2059 /* Set multicast filter */ 2060 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2061 msk_setmulti(sc_if); 2062 2063 /* enable interrupt mask for counter overflows */ 2064 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2065 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2066 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2067 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2068 2069 /* Configure RX MAC FIFO Flush Mask */ 2070 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2071 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2072 YU_RXSTAT_JABBER; 2073 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2074 2075 /* Configure RX MAC FIFO */ 2076 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2077 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2078 SK_RFCTL_FIFO_FLUSH_ON); 2079 2080 /* Increase flush threshould to 64 bytes */ 2081 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2082 SK_RFCTL_FIFO_THRESHOLD + 1); 2083 2084 /* Configure TX MAC FIFO */ 2085 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2086 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2087 2088 #if 1 2089 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2090 #endif 2091 DPRINTFN(6, ("msk_init_yukon: end\n")); 2092 } 2093 2094 /* 2095 * Note that to properly initialize any part of the GEnesis chip, 2096 * you first have to take it out of reset mode. 2097 */ 2098 int 2099 msk_init(struct ifnet *ifp) 2100 { 2101 struct sk_if_softc *sc_if = ifp->if_softc; 2102 struct sk_softc *sc = sc_if->sk_softc; 2103 int rc = 0, s; 2104 uint32_t imr, imtimer_ticks; 2105 2106 2107 DPRINTFN(2, ("msk_init\n")); 2108 2109 s = splnet(); 2110 2111 /* Cancel pending I/O and free all RX/TX buffers. */ 2112 msk_stop(ifp,0); 2113 2114 /* Configure I2C registers */ 2115 2116 /* Configure XMAC(s) */ 2117 msk_init_yukon(sc_if); 2118 if ((rc = ether_mediachange(ifp)) != 0) 2119 goto out; 2120 2121 /* Configure transmit arbiter(s) */ 2122 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2123 #if 0 2124 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2125 #endif 2126 2127 /* Configure RAMbuffers */ 2128 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2129 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2130 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2131 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2132 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2133 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2134 2135 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2136 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2137 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2138 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2139 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2140 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2141 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2142 2143 /* Configure BMUs */ 2144 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2145 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2146 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2147 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2148 2149 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2150 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2151 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2152 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2153 2154 /* Make sure the sync transmit queue is disabled. */ 2155 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2156 2157 /* Init descriptors */ 2158 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2159 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2160 "memory for rx buffers\n"); 2161 msk_stop(ifp,0); 2162 splx(s); 2163 return ENOBUFS; 2164 } 2165 2166 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2167 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2168 "memory for tx buffers\n"); 2169 msk_stop(ifp,0); 2170 splx(s); 2171 return ENOBUFS; 2172 } 2173 2174 /* Set interrupt moderation if changed via sysctl. */ 2175 switch (sc->sk_type) { 2176 case SK_YUKON_EC: 2177 case SK_YUKON_EC_U: 2178 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2179 break; 2180 case SK_YUKON_FE: 2181 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2182 break; 2183 case SK_YUKON_XL: 2184 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2185 break; 2186 default: 2187 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2188 } 2189 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2190 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2191 sk_win_write_4(sc, SK_IMTIMERINIT, 2192 SK_IM_USECS(sc->sk_int_mod)); 2193 aprint_verbose_dev(sc->sk_dev, 2194 "interrupt moderation is %d us\n", sc->sk_int_mod); 2195 } 2196 2197 /* Initialize prefetch engine. */ 2198 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2199 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2200 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2201 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2202 MSK_RX_RING_ADDR(sc_if, 0)); 2203 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2204 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2205 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2206 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2207 2208 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2209 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2210 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2211 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2212 MSK_TX_RING_ADDR(sc_if, 0)); 2213 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2214 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2215 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2216 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2217 2218 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2219 sc_if->sk_cdata.sk_rx_prod); 2220 2221 /* Configure interrupt handling */ 2222 if (sc_if->sk_port == SK_PORT_A) 2223 sc->sk_intrmask |= SK_Y2_INTRS1; 2224 else 2225 sc->sk_intrmask |= SK_Y2_INTRS2; 2226 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2227 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2228 2229 ifp->if_flags |= IFF_RUNNING; 2230 ifp->if_flags &= ~IFF_OACTIVE; 2231 2232 callout_schedule(&sc_if->sk_tick_ch, hz); 2233 2234 out: 2235 splx(s); 2236 return rc; 2237 } 2238 2239 void 2240 msk_stop(struct ifnet *ifp, int disable) 2241 { 2242 struct sk_if_softc *sc_if = ifp->if_softc; 2243 struct sk_softc *sc = sc_if->sk_softc; 2244 struct sk_txmap_entry *dma; 2245 int i; 2246 2247 DPRINTFN(2, ("msk_stop\n")); 2248 2249 callout_stop(&sc_if->sk_tick_ch); 2250 2251 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2252 2253 /* Stop transfer of Tx descriptors */ 2254 2255 /* Stop transfer of Rx descriptors */ 2256 2257 /* Turn off various components of this interface. */ 2258 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2259 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2260 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2261 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2262 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2263 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2264 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2265 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2266 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2267 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2268 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2269 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2270 2271 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2272 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2273 2274 /* Disable interrupts */ 2275 if (sc_if->sk_port == SK_PORT_A) 2276 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2277 else 2278 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2279 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2280 2281 SK_XM_READ_2(sc_if, XM_ISR); 2282 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2283 2284 /* Free RX and TX mbufs still in the queues. */ 2285 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2286 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2287 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2288 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2289 } 2290 } 2291 2292 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2293 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2294 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2295 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2296 #if 1 2297 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2298 sc_if->sk_cdata.sk_tx_map[i], link); 2299 sc_if->sk_cdata.sk_tx_map[i] = 0; 2300 #endif 2301 } 2302 } 2303 2304 #if 1 2305 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2306 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2307 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2308 free(dma, M_DEVBUF); 2309 } 2310 #endif 2311 } 2312 2313 CFATTACH_DECL_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2314 NULL, NULL); 2315 2316 CFATTACH_DECL_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2317 NULL, NULL); 2318 2319 #ifdef MSK_DEBUG 2320 void 2321 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2322 { 2323 #define DESC_PRINT(X) \ 2324 if (X) \ 2325 printf("txdesc[%d]." #X "=%#x\n", \ 2326 idx, X); 2327 2328 DESC_PRINT(letoh32(le->sk_addr)); 2329 DESC_PRINT(letoh16(le->sk_len)); 2330 DESC_PRINT(le->sk_ctl); 2331 DESC_PRINT(le->sk_opcode); 2332 #undef DESC_PRINT 2333 } 2334 2335 void 2336 msk_dump_bytes(const char *data, int len) 2337 { 2338 int c, i, j; 2339 2340 for (i = 0; i < len; i += 16) { 2341 printf("%08x ", i); 2342 c = len - i; 2343 if (c > 16) c = 16; 2344 2345 for (j = 0; j < c; j++) { 2346 printf("%02x ", data[i + j] & 0xff); 2347 if ((j & 0xf) == 7 && j > 0) 2348 printf(" "); 2349 } 2350 2351 for (; j < 16; j++) 2352 printf(" "); 2353 printf(" "); 2354 2355 for (j = 0; j < c; j++) { 2356 int ch = data[i + j] & 0xff; 2357 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2358 } 2359 2360 printf("\n"); 2361 2362 if (c < 16) 2363 break; 2364 } 2365 } 2366 2367 void 2368 msk_dump_mbuf(struct mbuf *m) 2369 { 2370 int count = m->m_pkthdr.len; 2371 2372 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2373 2374 while (count > 0 && m) { 2375 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2376 m, m->m_data, m->m_len); 2377 msk_dump_bytes(mtod(m, char *), m->m_len); 2378 2379 count -= m->m_len; 2380 m = m->m_next; 2381 } 2382 } 2383 #endif 2384 2385 static int 2386 msk_sysctl_handler(SYSCTLFN_ARGS) 2387 { 2388 int error, t; 2389 struct sysctlnode node; 2390 struct sk_softc *sc; 2391 2392 node = *rnode; 2393 sc = node.sysctl_data; 2394 t = sc->sk_int_mod; 2395 node.sysctl_data = &t; 2396 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2397 if (error || newp == NULL) 2398 return error; 2399 2400 if (t < SK_IM_MIN || t > SK_IM_MAX) 2401 return EINVAL; 2402 2403 /* update the softc with sysctl-changed value, and mark 2404 for hardware update */ 2405 sc->sk_int_mod = t; 2406 sc->sk_int_mod_pending = 1; 2407 return 0; 2408 } 2409 2410 /* 2411 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2412 * set up in skc_attach() 2413 */ 2414 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2415 { 2416 int rc; 2417 const struct sysctlnode *node; 2418 2419 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2420 0, CTLTYPE_NODE, "hw", NULL, 2421 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2422 goto err; 2423 } 2424 2425 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2426 0, CTLTYPE_NODE, "msk", 2427 SYSCTL_DESCR("msk interface controls"), 2428 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2429 goto err; 2430 } 2431 2432 msk_root_num = node->sysctl_num; 2433 return; 2434 2435 err: 2436 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2437 } 2438