1 /* $NetBSD: if_pcn.c,v 1.52 2010/11/13 13:52:06 uebayasi Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.52 2010/11/13 13:52:06 uebayasi Exp $"); 69 70 #include "rnd.h" 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/callout.h> 75 #include <sys/mbuf.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/socket.h> 79 #include <sys/ioctl.h> 80 #include <sys/errno.h> 81 #include <sys/device.h> 82 #include <sys/queue.h> 83 84 #if NRND > 0 85 #include <sys/rnd.h> 86 #endif 87 88 #include <net/if.h> 89 #include <net/if_dl.h> 90 #include <net/if_media.h> 91 #include <net/if_ether.h> 92 93 #include <net/bpf.h> 94 95 #include <sys/bus.h> 96 #include <sys/intr.h> 97 #include <machine/endian.h> 98 99 #include <dev/mii/mii.h> 100 #include <dev/mii/miivar.h> 101 102 #include <dev/ic/am79900reg.h> 103 #include <dev/ic/lancereg.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 109 #include <dev/pci/if_pcnreg.h> 110 111 /* 112 * Transmit descriptor list size. This is arbitrary, but allocate 113 * enough descriptors for 128 pending transmissions, and 4 segments 114 * per packet. This MUST work out to a power of 2. 115 * 116 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 117 * 118 * So we play a little trick here. We give each packet up to 16 119 * DMA segments, but only allocate the max of 512 descriptors. The 120 * transmit logic can deal with this, we just are hoping to sneak by. 121 */ 122 #define PCN_NTXSEGS 16 123 #define PCN_NTXSEGS_VMWARE 8 /* bug in VMware's emulation */ 124 125 #define PCN_TXQUEUELEN 128 126 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 127 #define PCN_NTXDESC 512 128 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 129 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 130 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 131 132 /* Tx interrupt every N + 1 packets. */ 133 #define PCN_TXINTR_MASK 7 134 135 /* 136 * Receive descriptor list size. We have one Rx buffer per incoming 137 * packet, so this logic is a little simpler. 138 */ 139 #define PCN_NRXDESC 128 140 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 141 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 142 143 /* 144 * Control structures are DMA'd to the PCnet chip. We allocate them in 145 * a single clump that maps to a single DMA segment to make several things 146 * easier. 147 */ 148 struct pcn_control_data { 149 /* The transmit descriptors. */ 150 struct letmd pcd_txdescs[PCN_NTXDESC]; 151 152 /* The receive descriptors. */ 153 struct lermd pcd_rxdescs[PCN_NRXDESC]; 154 155 /* The init block. */ 156 struct leinit pcd_initblock; 157 }; 158 159 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 160 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 161 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 162 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 163 164 /* 165 * Software state for transmit jobs. 166 */ 167 struct pcn_txsoft { 168 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 169 bus_dmamap_t txs_dmamap; /* our DMA map */ 170 int txs_firstdesc; /* first descriptor in packet */ 171 int txs_lastdesc; /* last descriptor in packet */ 172 }; 173 174 /* 175 * Software state for receive jobs. 176 */ 177 struct pcn_rxsoft { 178 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 179 bus_dmamap_t rxs_dmamap; /* our DMA map */ 180 }; 181 182 /* 183 * Description of Rx FIFO watermarks for various revisions. 184 */ 185 static const char * const pcn_79c970_rcvfw[] = { 186 "16 bytes", 187 "64 bytes", 188 "128 bytes", 189 NULL, 190 }; 191 192 static const char * const pcn_79c971_rcvfw[] = { 193 "16 bytes", 194 "64 bytes", 195 "112 bytes", 196 NULL, 197 }; 198 199 /* 200 * Description of Tx start points for various revisions. 201 */ 202 static const char * const pcn_79c970_xmtsp[] = { 203 "8 bytes", 204 "64 bytes", 205 "128 bytes", 206 "248 bytes", 207 }; 208 209 static const char * const pcn_79c971_xmtsp[] = { 210 "20 bytes", 211 "64 bytes", 212 "128 bytes", 213 "248 bytes", 214 }; 215 216 static const char * const pcn_79c971_xmtsp_sram[] = { 217 "44 bytes", 218 "64 bytes", 219 "128 bytes", 220 "store-and-forward", 221 }; 222 223 /* 224 * Description of Tx FIFO watermarks for various revisions. 225 */ 226 static const char * const pcn_79c970_xmtfw[] = { 227 "16 bytes", 228 "64 bytes", 229 "128 bytes", 230 NULL, 231 }; 232 233 static const char * const pcn_79c971_xmtfw[] = { 234 "16 bytes", 235 "64 bytes", 236 "108 bytes", 237 NULL, 238 }; 239 240 /* 241 * Software state per device. 242 */ 243 struct pcn_softc { 244 device_t sc_dev; /* generic device information */ 245 bus_space_tag_t sc_st; /* bus space tag */ 246 bus_space_handle_t sc_sh; /* bus space handle */ 247 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 248 struct ethercom sc_ethercom; /* Ethernet common data */ 249 250 /* Points to our media routines, etc. */ 251 const struct pcn_variant *sc_variant; 252 253 void *sc_ih; /* interrupt cookie */ 254 255 struct mii_data sc_mii; /* MII/media information */ 256 257 callout_t sc_tick_ch; /* tick callout */ 258 259 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 260 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 261 262 /* Software state for transmit and receive descriptors. */ 263 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 264 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 265 266 /* Control data structures */ 267 struct pcn_control_data *sc_control_data; 268 #define sc_txdescs sc_control_data->pcd_txdescs 269 #define sc_rxdescs sc_control_data->pcd_rxdescs 270 #define sc_initblock sc_control_data->pcd_initblock 271 272 #ifdef PCN_EVENT_COUNTERS 273 /* Event counters. */ 274 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 275 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 276 struct evcnt sc_ev_txintr; /* Tx interrupts */ 277 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 278 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 279 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 280 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 281 282 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 283 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 284 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 285 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 286 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 287 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 288 struct evcnt sc_ev_txcopy; /* Tx copies required */ 289 #endif /* PCN_EVENT_COUNTERS */ 290 291 const char * const *sc_rcvfw_desc; /* Rx FIFO watermark info */ 292 int sc_rcvfw; 293 294 const char * const *sc_xmtsp_desc; /* Tx start point info */ 295 int sc_xmtsp; 296 297 const char * const *sc_xmtfw_desc; /* Tx FIFO watermark info */ 298 int sc_xmtfw; 299 300 int sc_flags; /* misc. flags; see below */ 301 int sc_swstyle; /* the software style in use */ 302 303 int sc_txfree; /* number of free Tx descriptors */ 304 int sc_txnext; /* next ready Tx descriptor */ 305 306 int sc_txsfree; /* number of free Tx jobs */ 307 int sc_txsnext; /* next free Tx job */ 308 int sc_txsdirty; /* dirty Tx jobs */ 309 310 int sc_rxptr; /* next ready Rx descriptor/job */ 311 312 uint32_t sc_csr5; /* prototype CSR5 register */ 313 uint32_t sc_mode; /* prototype MODE register */ 314 315 #if NRND > 0 316 rndsource_element_t rnd_source; /* random source */ 317 #endif 318 }; 319 320 /* sc_flags */ 321 #define PCN_F_HAS_MII 0x0001 /* has MII */ 322 323 #ifdef PCN_EVENT_COUNTERS 324 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 325 #else 326 #define PCN_EVCNT_INCR(ev) /* nothing */ 327 #endif 328 329 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 330 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 331 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 332 333 #define PCN_CDTXSYNC(sc, x, n, ops) \ 334 do { \ 335 int __x, __n; \ 336 \ 337 __x = (x); \ 338 __n = (n); \ 339 \ 340 /* If it will wrap around, sync to the end of the ring. */ \ 341 if ((__x + __n) > PCN_NTXDESC) { \ 342 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 343 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 344 (PCN_NTXDESC - __x), (ops)); \ 345 __n -= (PCN_NTXDESC - __x); \ 346 __x = 0; \ 347 } \ 348 \ 349 /* Now sync whatever is left. */ \ 350 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 351 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 352 } while (/*CONSTCOND*/0) 353 354 #define PCN_CDRXSYNC(sc, x, ops) \ 355 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 356 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 357 358 #define PCN_CDINITSYNC(sc, ops) \ 359 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 360 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 361 362 #define PCN_INIT_RXDESC(sc, x) \ 363 do { \ 364 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 365 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 366 struct mbuf *__m = __rxs->rxs_mbuf; \ 367 \ 368 /* \ 369 * Note: We scoot the packet forward 2 bytes in the buffer \ 370 * so that the payload after the Ethernet header is aligned \ 371 * to a 4-byte boundary. \ 372 */ \ 373 __m->m_data = __m->m_ext.ext_buf + 2; \ 374 \ 375 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 376 __rmd->rmd2 = \ 377 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 378 __rmd->rmd0 = 0; \ 379 } else { \ 380 __rmd->rmd2 = 0; \ 381 __rmd->rmd0 = \ 382 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 383 } \ 384 __rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| \ 385 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 386 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\ 387 } while(/*CONSTCOND*/0) 388 389 static void pcn_start(struct ifnet *); 390 static void pcn_watchdog(struct ifnet *); 391 static int pcn_ioctl(struct ifnet *, u_long, void *); 392 static int pcn_init(struct ifnet *); 393 static void pcn_stop(struct ifnet *, int); 394 395 static bool pcn_shutdown(device_t, int); 396 397 static void pcn_reset(struct pcn_softc *); 398 static void pcn_rxdrain(struct pcn_softc *); 399 static int pcn_add_rxbuf(struct pcn_softc *, int); 400 static void pcn_tick(void *); 401 402 static void pcn_spnd(struct pcn_softc *); 403 404 static void pcn_set_filter(struct pcn_softc *); 405 406 static int pcn_intr(void *); 407 static void pcn_txintr(struct pcn_softc *); 408 static int pcn_rxintr(struct pcn_softc *); 409 410 static int pcn_mii_readreg(device_t, int, int); 411 static void pcn_mii_writereg(device_t, int, int, int); 412 static void pcn_mii_statchg(device_t); 413 414 static void pcn_79c970_mediainit(struct pcn_softc *); 415 static int pcn_79c970_mediachange(struct ifnet *); 416 static void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 417 418 static void pcn_79c971_mediainit(struct pcn_softc *); 419 420 /* 421 * Description of a PCnet-PCI variant. Used to select media access 422 * method, mostly, and to print a nice description of the chip. 423 */ 424 static const struct pcn_variant { 425 const char *pcv_desc; 426 void (*pcv_mediainit)(struct pcn_softc *); 427 uint16_t pcv_chipid; 428 } pcn_variants[] = { 429 { "Am79c970 PCnet-PCI", 430 pcn_79c970_mediainit, 431 PARTID_Am79c970 }, 432 433 { "Am79c970A PCnet-PCI II", 434 pcn_79c970_mediainit, 435 PARTID_Am79c970A }, 436 437 { "Am79c971 PCnet-FAST", 438 pcn_79c971_mediainit, 439 PARTID_Am79c971 }, 440 441 { "Am79c972 PCnet-FAST+", 442 pcn_79c971_mediainit, 443 PARTID_Am79c972 }, 444 445 { "Am79c973 PCnet-FAST III", 446 pcn_79c971_mediainit, 447 PARTID_Am79c973 }, 448 449 { "Am79c975 PCnet-FAST III", 450 pcn_79c971_mediainit, 451 PARTID_Am79c975 }, 452 453 { "Unknown PCnet-PCI variant", 454 pcn_79c971_mediainit, 455 0 }, 456 }; 457 458 int pcn_copy_small = 0; 459 460 static int pcn_match(device_t, cfdata_t, void *); 461 static void pcn_attach(device_t, device_t, void *); 462 463 CFATTACH_DECL_NEW(pcn, sizeof(struct pcn_softc), 464 pcn_match, pcn_attach, NULL, NULL); 465 466 /* 467 * Routines to read and write the PCnet-PCI CSR/BCR space. 468 */ 469 470 static inline uint32_t 471 pcn_csr_read(struct pcn_softc *sc, int reg) 472 { 473 474 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 475 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP)); 476 } 477 478 static inline void 479 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 480 { 481 482 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 483 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 484 } 485 486 static inline uint32_t 487 pcn_bcr_read(struct pcn_softc *sc, int reg) 488 { 489 490 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 491 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP)); 492 } 493 494 static inline void 495 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 496 { 497 498 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 499 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 500 } 501 502 static bool 503 pcn_is_vmware(const char *enaddr) 504 { 505 506 /* 507 * VMware uses the OUI 00:0c:29 for auto-generated MAC 508 * addresses. 509 */ 510 if (enaddr[0] == 0x00 && enaddr[1] == 0x0c && enaddr[2] == 0x29) 511 return (TRUE); 512 513 /* 514 * VMware uses the OUI 00:50:56 for manually-set MAC 515 * addresses (and some auto-generated ones). 516 */ 517 if (enaddr[0] == 0x00 && enaddr[1] == 0x50 && enaddr[2] == 0x56) 518 return (TRUE); 519 520 return (FALSE); 521 } 522 523 static const struct pcn_variant * 524 pcn_lookup_variant(uint16_t chipid) 525 { 526 const struct pcn_variant *pcv; 527 528 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 529 if (chipid == pcv->pcv_chipid) 530 return (pcv); 531 } 532 533 /* 534 * This covers unknown chips, which we simply treat like 535 * a generic PCnet-FAST. 536 */ 537 return (pcv); 538 } 539 540 static int 541 pcn_match(device_t parent, cfdata_t cf, void *aux) 542 { 543 struct pci_attach_args *pa = aux; 544 545 /* 546 * IBM Makes a PCI variant of this card which shows up as a 547 * Trident Microsystems 4DWAVE DX (ethernet network, revision 0x25) 548 * this card is truly a pcn card, so we have a special case match for 549 * it 550 */ 551 552 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIDENT && 553 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_TRIDENT_4DWAVE_DX && 554 PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK) 555 return(1); 556 557 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 558 return (0); 559 560 switch (PCI_PRODUCT(pa->pa_id)) { 561 case PCI_PRODUCT_AMD_PCNET_PCI: 562 /* Beat if_le_pci.c */ 563 return (10); 564 } 565 566 return (0); 567 } 568 569 static void 570 pcn_attach(device_t parent, device_t self, void *aux) 571 { 572 struct pcn_softc *sc = device_private(self); 573 struct pci_attach_args *pa = aux; 574 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 575 pci_chipset_tag_t pc = pa->pa_pc; 576 pci_intr_handle_t ih; 577 const char *intrstr = NULL; 578 bus_space_tag_t iot, memt; 579 bus_space_handle_t ioh, memh; 580 bus_dma_segment_t seg; 581 int ioh_valid, memh_valid; 582 int ntxsegs, i, rseg, error; 583 uint32_t chipid, reg; 584 uint8_t enaddr[ETHER_ADDR_LEN]; 585 prop_object_t obj; 586 bool is_vmware; 587 588 sc->sc_dev = self; 589 callout_init(&sc->sc_tick_ch, 0); 590 591 aprint_normal(": AMD PCnet-PCI Ethernet\n"); 592 593 /* 594 * Map the device. 595 */ 596 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 597 &iot, &ioh, NULL, NULL) == 0); 598 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 599 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 600 &memt, &memh, NULL, NULL) == 0); 601 602 if (memh_valid) { 603 sc->sc_st = memt; 604 sc->sc_sh = memh; 605 } else if (ioh_valid) { 606 sc->sc_st = iot; 607 sc->sc_sh = ioh; 608 } else { 609 aprint_error_dev(self, "unable to map device registers\n"); 610 return; 611 } 612 613 sc->sc_dmat = pa->pa_dmat; 614 615 /* Make sure bus mastering is enabled. */ 616 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 617 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 618 PCI_COMMAND_MASTER_ENABLE); 619 620 /* power up chip */ 621 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 622 NULL)) && error != EOPNOTSUPP) { 623 aprint_error_dev(self, "cannot activate %d\n", error); 624 return; 625 } 626 627 /* 628 * Reset the chip to a known state. This also puts the 629 * chip into 32-bit mode. 630 */ 631 pcn_reset(sc); 632 633 /* 634 * On some systems with the chip is an on-board device, the 635 * EEPROM is not used. Handle this by reading the MAC address 636 * from the CSRs (assuming that boot firmware has written 637 * it there). 638 */ 639 obj = prop_dictionary_get(device_properties(sc->sc_dev), 640 "am79c970-no-eeprom"); 641 if (prop_bool_true(obj)) { 642 for (i = 0; i < 3; i++) { 643 uint32_t val; 644 val = pcn_csr_read(sc, LE_CSR12 + i); 645 enaddr[2 * i] = val & 0xff; 646 enaddr[2 * i + 1] = (val >> 8) & 0xff; 647 } 648 } else { 649 for (i = 0; i < ETHER_ADDR_LEN; i++) { 650 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 651 PCN32_APROM + i); 652 } 653 } 654 655 /* Check to see if this is a VMware emulated network interface. */ 656 is_vmware = pcn_is_vmware(enaddr); 657 658 /* 659 * Now that the device is mapped, attempt to figure out what 660 * kind of chip we have. Note that IDL has all 32 bits of 661 * the chip ID when we're in 32-bit mode. 662 */ 663 chipid = pcn_csr_read(sc, LE_CSR88); 664 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 665 666 aprint_normal_dev(self, "%s rev %d, Ethernet address %s\n", 667 sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 668 ether_sprintf(enaddr)); 669 670 /* 671 * VMware has a bug in its network interface emulation; we must 672 * limit the number of Tx segments. 673 */ 674 if (is_vmware) { 675 ntxsegs = PCN_NTXSEGS_VMWARE; 676 prop_dictionary_set_bool(device_properties(sc->sc_dev), 677 "am79c970-vmware-tx-bug", TRUE); 678 aprint_verbose_dev(self, 679 "VMware Tx segment count bug detected\n"); 680 } else { 681 ntxsegs = PCN_NTXSEGS; 682 } 683 684 /* 685 * Map and establish our interrupt. 686 */ 687 if (pci_intr_map(pa, &ih)) { 688 aprint_error_dev(self, "unable to map interrupt\n"); 689 return; 690 } 691 intrstr = pci_intr_string(pc, ih); 692 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, pcn_intr, sc); 693 if (sc->sc_ih == NULL) { 694 aprint_error_dev(self, "unable to establish interrupt"); 695 if (intrstr != NULL) 696 aprint_error(" at %s", intrstr); 697 aprint_error("\n"); 698 return; 699 } 700 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 701 702 /* 703 * Allocate the control data structures, and create and load the 704 * DMA map for it. 705 */ 706 if ((error = bus_dmamem_alloc(sc->sc_dmat, 707 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 708 0)) != 0) { 709 aprint_error_dev(self, "unable to allocate control data, " 710 "error = %d\n", error); 711 goto fail_0; 712 } 713 714 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 715 sizeof(struct pcn_control_data), (void **)&sc->sc_control_data, 716 BUS_DMA_COHERENT)) != 0) { 717 aprint_error_dev(self, "unable to map control data, " 718 "error = %d\n", error); 719 goto fail_1; 720 } 721 722 if ((error = bus_dmamap_create(sc->sc_dmat, 723 sizeof(struct pcn_control_data), 1, 724 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 725 aprint_error_dev(self, "unable to create control data DMA map, " 726 "error = %d\n", error); 727 goto fail_2; 728 } 729 730 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 731 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 732 0)) != 0) { 733 aprint_error_dev(self, 734 "unable to load control data DMA map, error = %d\n", error); 735 goto fail_3; 736 } 737 738 /* Create the transmit buffer DMA maps. */ 739 for (i = 0; i < PCN_TXQUEUELEN; i++) { 740 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 741 ntxsegs, MCLBYTES, 0, 0, 742 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 743 aprint_error_dev(self, 744 "unable to create tx DMA map %d, error = %d\n", 745 i, error); 746 goto fail_4; 747 } 748 } 749 750 /* Create the receive buffer DMA maps. */ 751 for (i = 0; i < PCN_NRXDESC; i++) { 752 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 753 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 754 aprint_error_dev(self, 755 "unable to create rx DMA map %d, error = %d\n", 756 i, error); 757 goto fail_5; 758 } 759 sc->sc_rxsoft[i].rxs_mbuf = NULL; 760 } 761 762 /* Initialize our media structures. */ 763 (*sc->sc_variant->pcv_mediainit)(sc); 764 765 /* 766 * Initialize FIFO watermark info. 767 */ 768 switch (sc->sc_variant->pcv_chipid) { 769 case PARTID_Am79c970: 770 case PARTID_Am79c970A: 771 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 772 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 773 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 774 break; 775 776 default: 777 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 778 /* 779 * Read BCR25 to determine how much SRAM is 780 * on the board. If > 0, then we the chip 781 * uses different Start Point thresholds. 782 * 783 * Note BCR25 and BCR26 are loaded from the 784 * EEPROM on RST, and unaffected by S_RESET, 785 * so we don't really have to worry about 786 * them except for this. 787 */ 788 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 789 if (reg != 0) 790 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 791 else 792 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 793 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 794 break; 795 } 796 797 /* 798 * Set up defaults -- see the tables above for what these 799 * values mean. 800 * 801 * XXX How should we tune RCVFW and XMTFW? 802 */ 803 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 804 sc->sc_xmtsp = 1; 805 sc->sc_xmtfw = 0; 806 807 ifp = &sc->sc_ethercom.ec_if; 808 strcpy(ifp->if_xname, device_xname(self)); 809 ifp->if_softc = sc; 810 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 811 ifp->if_ioctl = pcn_ioctl; 812 ifp->if_start = pcn_start; 813 ifp->if_watchdog = pcn_watchdog; 814 ifp->if_init = pcn_init; 815 ifp->if_stop = pcn_stop; 816 IFQ_SET_READY(&ifp->if_snd); 817 818 /* Attach the interface. */ 819 if_attach(ifp); 820 ether_ifattach(ifp, enaddr); 821 #if NRND > 0 822 rnd_attach_source(&sc->rnd_source, device_xname(self), 823 RND_TYPE_NET, 0); 824 #endif 825 826 #ifdef PCN_EVENT_COUNTERS 827 /* Attach event counters. */ 828 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 829 NULL, device_xname(self), "txsstall"); 830 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 831 NULL, device_xname(self), "txdstall"); 832 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 833 NULL, device_xname(self), "txintr"); 834 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 835 NULL, device_xname(self), "rxintr"); 836 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 837 NULL, device_xname(self), "babl"); 838 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 839 NULL, device_xname(self), "miss"); 840 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 841 NULL, device_xname(self), "merr"); 842 843 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 844 NULL, device_xname(self), "txseg1"); 845 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 846 NULL, device_xname(self), "txseg2"); 847 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 848 NULL, device_xname(self), "txseg3"); 849 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 850 NULL, device_xname(self), "txseg4"); 851 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 852 NULL, device_xname(self), "txseg5"); 853 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 854 NULL, device_xname(self), "txsegmore"); 855 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 856 NULL, device_xname(self), "txcopy"); 857 #endif /* PCN_EVENT_COUNTERS */ 858 859 /* 860 * Establish power handler with shutdown hook, to make sure 861 * the interface is shutdown during reboot. 862 */ 863 if (pmf_device_register1(self, NULL, NULL, pcn_shutdown)) 864 pmf_class_network_register(self, ifp); 865 else 866 aprint_error_dev(self, "couldn't establish power handler\n"); 867 868 return; 869 870 /* 871 * Free any resources we've allocated during the failed attach 872 * attempt. Do this in reverse order and fall through. 873 */ 874 fail_5: 875 for (i = 0; i < PCN_NRXDESC; i++) { 876 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 877 bus_dmamap_destroy(sc->sc_dmat, 878 sc->sc_rxsoft[i].rxs_dmamap); 879 } 880 fail_4: 881 for (i = 0; i < PCN_TXQUEUELEN; i++) { 882 if (sc->sc_txsoft[i].txs_dmamap != NULL) 883 bus_dmamap_destroy(sc->sc_dmat, 884 sc->sc_txsoft[i].txs_dmamap); 885 } 886 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 887 fail_3: 888 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 889 fail_2: 890 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 891 sizeof(struct pcn_control_data)); 892 fail_1: 893 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 894 fail_0: 895 return; 896 } 897 898 /* 899 * pcn_shutdown: 900 * 901 * Make sure the interface is stopped at reboot time. 902 */ 903 static bool 904 pcn_shutdown(device_t self, int howto) 905 { 906 struct pcn_softc *sc = device_private(self); 907 908 pcn_stop(&sc->sc_ethercom.ec_if, 1); 909 /* explicitly reset the chip for some onboard one with lazy firmware */ 910 pcn_reset(sc); 911 912 return true; 913 } 914 915 /* 916 * pcn_start: [ifnet interface function] 917 * 918 * Start packet transmission on the interface. 919 */ 920 static void 921 pcn_start(struct ifnet *ifp) 922 { 923 struct pcn_softc *sc = ifp->if_softc; 924 struct mbuf *m0, *m; 925 struct pcn_txsoft *txs; 926 bus_dmamap_t dmamap; 927 int error, nexttx, lasttx = -1, ofree, seg; 928 929 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 930 return; 931 932 /* 933 * Remember the previous number of free descriptors and 934 * the first descriptor we'll use. 935 */ 936 ofree = sc->sc_txfree; 937 938 /* 939 * Loop through the send queue, setting up transmit descriptors 940 * until we drain the queue, or use up all available transmit 941 * descriptors. 942 */ 943 for (;;) { 944 /* Grab a packet off the queue. */ 945 IFQ_POLL(&ifp->if_snd, m0); 946 if (m0 == NULL) 947 break; 948 m = NULL; 949 950 /* Get a work queue entry. */ 951 if (sc->sc_txsfree == 0) { 952 PCN_EVCNT_INCR(&sc->sc_ev_txsstall); 953 break; 954 } 955 956 txs = &sc->sc_txsoft[sc->sc_txsnext]; 957 dmamap = txs->txs_dmamap; 958 959 /* 960 * Load the DMA map. If this fails, the packet either 961 * didn't fit in the alloted number of segments, or we 962 * were short on resources. In this case, we'll copy 963 * and try again. 964 */ 965 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 966 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 967 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 968 MGETHDR(m, M_DONTWAIT, MT_DATA); 969 if (m == NULL) { 970 printf("%s: unable to allocate Tx mbuf\n", 971 device_xname(sc->sc_dev)); 972 break; 973 } 974 if (m0->m_pkthdr.len > MHLEN) { 975 MCLGET(m, M_DONTWAIT); 976 if ((m->m_flags & M_EXT) == 0) { 977 printf("%s: unable to allocate Tx " 978 "cluster\n", 979 device_xname(sc->sc_dev)); 980 m_freem(m); 981 break; 982 } 983 } 984 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 985 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 986 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 987 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 988 if (error) { 989 printf("%s: unable to load Tx buffer, " 990 "error = %d\n", device_xname(sc->sc_dev), 991 error); 992 break; 993 } 994 } 995 996 /* 997 * Ensure we have enough descriptors free to describe 998 * the packet. Note, we always reserve one descriptor 999 * at the end of the ring as a termination point, to 1000 * prevent wrap-around. 1001 */ 1002 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1003 /* 1004 * Not enough free descriptors to transmit this 1005 * packet. We haven't committed anything yet, 1006 * so just unload the DMA map, put the packet 1007 * back on the queue, and punt. Notify the upper 1008 * layer that there are not more slots left. 1009 * 1010 * XXX We could allocate an mbuf and copy, but 1011 * XXX is it worth it? 1012 */ 1013 ifp->if_flags |= IFF_OACTIVE; 1014 bus_dmamap_unload(sc->sc_dmat, dmamap); 1015 if (m != NULL) 1016 m_freem(m); 1017 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 1018 break; 1019 } 1020 1021 IFQ_DEQUEUE(&ifp->if_snd, m0); 1022 if (m != NULL) { 1023 m_freem(m0); 1024 m0 = m; 1025 } 1026 1027 /* 1028 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1029 */ 1030 1031 /* Sync the DMA map. */ 1032 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1033 BUS_DMASYNC_PREWRITE); 1034 1035 #ifdef PCN_EVENT_COUNTERS 1036 switch (dmamap->dm_nsegs) { 1037 case 1: 1038 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 1039 break; 1040 case 2: 1041 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 1042 break; 1043 case 3: 1044 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 1045 break; 1046 case 4: 1047 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 1048 break; 1049 case 5: 1050 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 1051 break; 1052 default: 1053 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 1054 break; 1055 } 1056 #endif /* PCN_EVENT_COUNTERS */ 1057 1058 /* 1059 * Initialize the transmit descriptors. 1060 */ 1061 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 1062 for (nexttx = sc->sc_txnext, seg = 0; 1063 seg < dmamap->dm_nsegs; 1064 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1065 /* 1066 * If this is the first descriptor we're 1067 * enqueueing, don't set the OWN bit just 1068 * yet. That could cause a race condition. 1069 * We'll do it below. 1070 */ 1071 sc->sc_txdescs[nexttx].tmd0 = 0; 1072 sc->sc_txdescs[nexttx].tmd2 = 1073 htole32(dmamap->dm_segs[seg].ds_addr); 1074 sc->sc_txdescs[nexttx].tmd1 = 1075 htole32(LE_T1_ONES | 1076 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1077 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1078 LE_T1_BCNT_MASK)); 1079 lasttx = nexttx; 1080 } 1081 } else { 1082 for (nexttx = sc->sc_txnext, seg = 0; 1083 seg < dmamap->dm_nsegs; 1084 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1085 /* 1086 * If this is the first descriptor we're 1087 * enqueueing, don't set the OWN bit just 1088 * yet. That could cause a race condition. 1089 * We'll do it below. 1090 */ 1091 sc->sc_txdescs[nexttx].tmd0 = 1092 htole32(dmamap->dm_segs[seg].ds_addr); 1093 sc->sc_txdescs[nexttx].tmd2 = 0; 1094 sc->sc_txdescs[nexttx].tmd1 = 1095 htole32(LE_T1_ONES | 1096 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1097 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1098 LE_T1_BCNT_MASK)); 1099 lasttx = nexttx; 1100 } 1101 } 1102 1103 KASSERT(lasttx != -1); 1104 /* Interrupt on the packet, if appropriate. */ 1105 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1106 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1107 1108 /* Set `start of packet' and `end of packet' appropriately. */ 1109 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1110 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1111 htole32(LE_T1_OWN|LE_T1_STP); 1112 1113 /* Sync the descriptors we're using. */ 1114 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1115 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1116 1117 /* Kick the transmitter. */ 1118 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); 1119 1120 /* 1121 * Store a pointer to the packet so we can free it later, 1122 * and remember what txdirty will be once the packet is 1123 * done. 1124 */ 1125 txs->txs_mbuf = m0; 1126 txs->txs_firstdesc = sc->sc_txnext; 1127 txs->txs_lastdesc = lasttx; 1128 1129 /* Advance the tx pointer. */ 1130 sc->sc_txfree -= dmamap->dm_nsegs; 1131 sc->sc_txnext = nexttx; 1132 1133 sc->sc_txsfree--; 1134 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1135 1136 /* Pass the packet to any BPF listeners. */ 1137 bpf_mtap(ifp, m0); 1138 } 1139 1140 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1141 /* No more slots left; notify upper layer. */ 1142 ifp->if_flags |= IFF_OACTIVE; 1143 } 1144 1145 if (sc->sc_txfree != ofree) { 1146 /* Set a watchdog timer in case the chip flakes out. */ 1147 ifp->if_timer = 5; 1148 } 1149 } 1150 1151 /* 1152 * pcn_watchdog: [ifnet interface function] 1153 * 1154 * Watchdog timer handler. 1155 */ 1156 static void 1157 pcn_watchdog(struct ifnet *ifp) 1158 { 1159 struct pcn_softc *sc = ifp->if_softc; 1160 1161 /* 1162 * Since we're not interrupting every packet, sweep 1163 * up before we report an error. 1164 */ 1165 pcn_txintr(sc); 1166 1167 if (sc->sc_txfree != PCN_NTXDESC) { 1168 printf("%s: device timeout (txfree %d txsfree %d)\n", 1169 device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree); 1170 ifp->if_oerrors++; 1171 1172 /* Reset the interface. */ 1173 (void) pcn_init(ifp); 1174 } 1175 1176 /* Try to get more packets going. */ 1177 pcn_start(ifp); 1178 } 1179 1180 /* 1181 * pcn_ioctl: [ifnet interface function] 1182 * 1183 * Handle control requests from the operator. 1184 */ 1185 static int 1186 pcn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1187 { 1188 struct pcn_softc *sc = ifp->if_softc; 1189 struct ifreq *ifr = (struct ifreq *) data; 1190 int s, error; 1191 1192 s = splnet(); 1193 1194 switch (cmd) { 1195 case SIOCSIFMEDIA: 1196 case SIOCGIFMEDIA: 1197 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1198 break; 1199 1200 default: 1201 error = ether_ioctl(ifp, cmd, data); 1202 if (error == ENETRESET) { 1203 /* 1204 * Multicast list has changed; set the hardware filter 1205 * accordingly. 1206 */ 1207 if (ifp->if_flags & IFF_RUNNING) 1208 error = pcn_init(ifp); 1209 else 1210 error = 0; 1211 } 1212 break; 1213 } 1214 1215 /* Try to get more packets going. */ 1216 pcn_start(ifp); 1217 1218 splx(s); 1219 return (error); 1220 } 1221 1222 /* 1223 * pcn_intr: 1224 * 1225 * Interrupt service routine. 1226 */ 1227 static int 1228 pcn_intr(void *arg) 1229 { 1230 struct pcn_softc *sc = arg; 1231 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1232 uint32_t csr0; 1233 int wantinit, handled = 0; 1234 1235 for (wantinit = 0; wantinit == 0;) { 1236 csr0 = pcn_csr_read(sc, LE_CSR0); 1237 if ((csr0 & LE_C0_INTR) == 0) 1238 break; 1239 1240 #if NRND > 0 1241 if (RND_ENABLED(&sc->rnd_source)) 1242 rnd_add_uint32(&sc->rnd_source, csr0); 1243 #endif 1244 1245 /* ACK the bits and re-enable interrupts. */ 1246 pcn_csr_write(sc, LE_CSR0, csr0 & 1247 (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT| 1248 LE_C0_TINT|LE_C0_IDON)); 1249 1250 handled = 1; 1251 1252 if (csr0 & LE_C0_RINT) { 1253 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1254 wantinit = pcn_rxintr(sc); 1255 } 1256 1257 if (csr0 & LE_C0_TINT) { 1258 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1259 pcn_txintr(sc); 1260 } 1261 1262 if (csr0 & LE_C0_ERR) { 1263 if (csr0 & LE_C0_BABL) { 1264 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1265 ifp->if_oerrors++; 1266 } 1267 if (csr0 & LE_C0_MISS) { 1268 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1269 ifp->if_ierrors++; 1270 } 1271 if (csr0 & LE_C0_MERR) { 1272 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1273 printf("%s: memory error\n", 1274 device_xname(sc->sc_dev)); 1275 wantinit = 1; 1276 break; 1277 } 1278 } 1279 1280 if ((csr0 & LE_C0_RXON) == 0) { 1281 printf("%s: receiver disabled\n", 1282 device_xname(sc->sc_dev)); 1283 ifp->if_ierrors++; 1284 wantinit = 1; 1285 } 1286 1287 if ((csr0 & LE_C0_TXON) == 0) { 1288 printf("%s: transmitter disabled\n", 1289 device_xname(sc->sc_dev)); 1290 ifp->if_oerrors++; 1291 wantinit = 1; 1292 } 1293 } 1294 1295 if (handled) { 1296 if (wantinit) 1297 pcn_init(ifp); 1298 1299 /* Try to get more packets going. */ 1300 pcn_start(ifp); 1301 } 1302 1303 return (handled); 1304 } 1305 1306 /* 1307 * pcn_spnd: 1308 * 1309 * Suspend the chip. 1310 */ 1311 static void 1312 pcn_spnd(struct pcn_softc *sc) 1313 { 1314 int i; 1315 1316 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1317 1318 for (i = 0; i < 10000; i++) { 1319 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1320 return; 1321 delay(5); 1322 } 1323 1324 printf("%s: WARNING: chip failed to enter suspended state\n", 1325 device_xname(sc->sc_dev)); 1326 } 1327 1328 /* 1329 * pcn_txintr: 1330 * 1331 * Helper; handle transmit interrupts. 1332 */ 1333 static void 1334 pcn_txintr(struct pcn_softc *sc) 1335 { 1336 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1337 struct pcn_txsoft *txs; 1338 uint32_t tmd1, tmd2, tmd; 1339 int i, j; 1340 1341 ifp->if_flags &= ~IFF_OACTIVE; 1342 1343 /* 1344 * Go through our Tx list and free mbufs for those 1345 * frames which have been transmitted. 1346 */ 1347 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1348 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1349 txs = &sc->sc_txsoft[i]; 1350 1351 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1352 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1353 1354 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1355 if (tmd1 & LE_T1_OWN) 1356 break; 1357 1358 /* 1359 * Slightly annoying -- we have to loop through the 1360 * descriptors we've used looking for ERR, since it 1361 * can appear on any descriptor in the chain. 1362 */ 1363 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1364 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1365 if (tmd & LE_T1_ERR) { 1366 ifp->if_oerrors++; 1367 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1368 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1369 else 1370 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1371 if (tmd2 & LE_T2_UFLO) { 1372 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1373 sc->sc_xmtsp++; 1374 printf("%s: transmit " 1375 "underrun; new threshold: " 1376 "%s\n", 1377 device_xname(sc->sc_dev), 1378 sc->sc_xmtsp_desc[ 1379 sc->sc_xmtsp]); 1380 pcn_spnd(sc); 1381 pcn_csr_write(sc, LE_CSR80, 1382 LE_C80_RCVFW(sc->sc_rcvfw) | 1383 LE_C80_XMTSP(sc->sc_xmtsp) | 1384 LE_C80_XMTFW(sc->sc_xmtfw)); 1385 pcn_csr_write(sc, LE_CSR5, 1386 sc->sc_csr5); 1387 } else { 1388 printf("%s: transmit " 1389 "underrun\n", 1390 device_xname(sc->sc_dev)); 1391 } 1392 } else if (tmd2 & LE_T2_BUFF) { 1393 printf("%s: transmit buffer error\n", 1394 device_xname(sc->sc_dev)); 1395 } 1396 if (tmd2 & LE_T2_LCOL) 1397 ifp->if_collisions++; 1398 if (tmd2 & LE_T2_RTRY) 1399 ifp->if_collisions += 16; 1400 goto next_packet; 1401 } 1402 if (j == txs->txs_lastdesc) 1403 break; 1404 } 1405 if (tmd1 & LE_T1_ONE) 1406 ifp->if_collisions++; 1407 else if (tmd & LE_T1_MORE) { 1408 /* Real number is unknown. */ 1409 ifp->if_collisions += 2; 1410 } 1411 ifp->if_opackets++; 1412 next_packet: 1413 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1414 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1415 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1416 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1417 m_freem(txs->txs_mbuf); 1418 txs->txs_mbuf = NULL; 1419 } 1420 1421 /* Update the dirty transmit buffer pointer. */ 1422 sc->sc_txsdirty = i; 1423 1424 /* 1425 * If there are no more pending transmissions, cancel the watchdog 1426 * timer. 1427 */ 1428 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1429 ifp->if_timer = 0; 1430 } 1431 1432 /* 1433 * pcn_rxintr: 1434 * 1435 * Helper; handle receive interrupts. 1436 */ 1437 static int 1438 pcn_rxintr(struct pcn_softc *sc) 1439 { 1440 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1441 struct pcn_rxsoft *rxs; 1442 struct mbuf *m; 1443 uint32_t rmd1; 1444 int i, len; 1445 1446 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1447 rxs = &sc->sc_rxsoft[i]; 1448 1449 PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1450 1451 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1452 1453 if (rmd1 & LE_R1_OWN) 1454 break; 1455 1456 /* 1457 * Check for errors and make sure the packet fit into 1458 * a single buffer. We have structured this block of 1459 * code the way it is in order to compress it into 1460 * one test in the common case (no error). 1461 */ 1462 if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) != 1463 (LE_R1_STP|LE_R1_ENP))) { 1464 /* Make sure the packet is in a single buffer. */ 1465 if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) != 1466 (LE_R1_STP|LE_R1_ENP)) { 1467 printf("%s: packet spilled into next buffer\n", 1468 device_xname(sc->sc_dev)); 1469 return (1); /* pcn_intr() will re-init */ 1470 } 1471 1472 /* 1473 * If the packet had an error, simple recycle the 1474 * buffer. 1475 */ 1476 if (rmd1 & LE_R1_ERR) { 1477 ifp->if_ierrors++; 1478 /* 1479 * If we got an overflow error, chances 1480 * are there will be a CRC error. In 1481 * this case, just print the overflow 1482 * error, and skip the others. 1483 */ 1484 if (rmd1 & LE_R1_OFLO) 1485 printf("%s: overflow error\n", 1486 device_xname(sc->sc_dev)); 1487 else { 1488 #define PRINTIT(x, str) \ 1489 if (rmd1 & (x)) \ 1490 printf("%s: %s\n", \ 1491 device_xname(sc->sc_dev), \ 1492 str); 1493 PRINTIT(LE_R1_FRAM, "framing error"); 1494 PRINTIT(LE_R1_CRC, "CRC error"); 1495 PRINTIT(LE_R1_BUFF, "buffer error"); 1496 } 1497 #undef PRINTIT 1498 PCN_INIT_RXDESC(sc, i); 1499 continue; 1500 } 1501 } 1502 1503 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1504 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1505 1506 /* 1507 * No errors; receive the packet. 1508 */ 1509 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1510 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1511 else 1512 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1513 1514 /* 1515 * The LANCE family includes the CRC with every packet; 1516 * trim it off here. 1517 */ 1518 len -= ETHER_CRC_LEN; 1519 1520 /* 1521 * If the packet is small enough to fit in a 1522 * single header mbuf, allocate one and copy 1523 * the data into it. This greatly reduces 1524 * memory consumption when we receive lots 1525 * of small packets. 1526 * 1527 * Otherwise, we add a new buffer to the receive 1528 * chain. If this fails, we drop the packet and 1529 * recycle the old buffer. 1530 */ 1531 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1532 MGETHDR(m, M_DONTWAIT, MT_DATA); 1533 if (m == NULL) 1534 goto dropit; 1535 m->m_data += 2; 1536 memcpy(mtod(m, void *), 1537 mtod(rxs->rxs_mbuf, void *), len); 1538 PCN_INIT_RXDESC(sc, i); 1539 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1540 rxs->rxs_dmamap->dm_mapsize, 1541 BUS_DMASYNC_PREREAD); 1542 } else { 1543 m = rxs->rxs_mbuf; 1544 if (pcn_add_rxbuf(sc, i) != 0) { 1545 dropit: 1546 ifp->if_ierrors++; 1547 PCN_INIT_RXDESC(sc, i); 1548 bus_dmamap_sync(sc->sc_dmat, 1549 rxs->rxs_dmamap, 0, 1550 rxs->rxs_dmamap->dm_mapsize, 1551 BUS_DMASYNC_PREREAD); 1552 continue; 1553 } 1554 } 1555 1556 m->m_pkthdr.rcvif = ifp; 1557 m->m_pkthdr.len = m->m_len = len; 1558 1559 /* Pass this up to any BPF listeners. */ 1560 bpf_mtap(ifp, m); 1561 1562 /* Pass it on. */ 1563 (*ifp->if_input)(ifp, m); 1564 ifp->if_ipackets++; 1565 } 1566 1567 /* Update the receive pointer. */ 1568 sc->sc_rxptr = i; 1569 return (0); 1570 } 1571 1572 /* 1573 * pcn_tick: 1574 * 1575 * One second timer, used to tick the MII. 1576 */ 1577 static void 1578 pcn_tick(void *arg) 1579 { 1580 struct pcn_softc *sc = arg; 1581 int s; 1582 1583 s = splnet(); 1584 mii_tick(&sc->sc_mii); 1585 splx(s); 1586 1587 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1588 } 1589 1590 /* 1591 * pcn_reset: 1592 * 1593 * Perform a soft reset on the PCnet-PCI. 1594 */ 1595 static void 1596 pcn_reset(struct pcn_softc *sc) 1597 { 1598 1599 /* 1600 * The PCnet-PCI chip is reset by reading from the 1601 * RESET register. Note that while the NE2100 LANCE 1602 * boards require a write after the read, the PCnet-PCI 1603 * chips do not require this. 1604 * 1605 * Since we don't know if we're in 16-bit or 32-bit 1606 * mode right now, issue both (it's safe) in the 1607 * hopes that one will succeed. 1608 */ 1609 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1610 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1611 1612 /* Wait 1ms for it to finish. */ 1613 delay(1000); 1614 1615 /* 1616 * Select 32-bit I/O mode by issuing a 32-bit write to the 1617 * RDP. Since the RAP is 0 after a reset, writing a 0 1618 * to RDP is safe (since it simply clears CSR0). 1619 */ 1620 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1621 } 1622 1623 /* 1624 * pcn_init: [ifnet interface function] 1625 * 1626 * Initialize the interface. Must be called at splnet(). 1627 */ 1628 static int 1629 pcn_init(struct ifnet *ifp) 1630 { 1631 struct pcn_softc *sc = ifp->if_softc; 1632 struct pcn_rxsoft *rxs; 1633 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 1634 int i, error = 0; 1635 uint32_t reg; 1636 1637 /* Cancel any pending I/O. */ 1638 pcn_stop(ifp, 0); 1639 1640 /* Reset the chip to a known state. */ 1641 pcn_reset(sc); 1642 1643 /* 1644 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1645 * else. 1646 * 1647 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1648 * because the structure layout is compatible with ILACC, 1649 * but the burst mode is only available in SSTYLE 3, and 1650 * burst mode should provide some performance enhancement. 1651 */ 1652 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1653 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1654 else 1655 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1656 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1657 1658 /* Initialize the transmit descriptor ring. */ 1659 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1660 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1661 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1662 sc->sc_txfree = PCN_NTXDESC; 1663 sc->sc_txnext = 0; 1664 1665 /* Initialize the transmit job descriptors. */ 1666 for (i = 0; i < PCN_TXQUEUELEN; i++) 1667 sc->sc_txsoft[i].txs_mbuf = NULL; 1668 sc->sc_txsfree = PCN_TXQUEUELEN; 1669 sc->sc_txsnext = 0; 1670 sc->sc_txsdirty = 0; 1671 1672 /* 1673 * Initialize the receive descriptor and receive job 1674 * descriptor rings. 1675 */ 1676 for (i = 0; i < PCN_NRXDESC; i++) { 1677 rxs = &sc->sc_rxsoft[i]; 1678 if (rxs->rxs_mbuf == NULL) { 1679 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1680 printf("%s: unable to allocate or map rx " 1681 "buffer %d, error = %d\n", 1682 device_xname(sc->sc_dev), i, error); 1683 /* 1684 * XXX Should attempt to run with fewer receive 1685 * XXX buffers instead of just failing. 1686 */ 1687 pcn_rxdrain(sc); 1688 goto out; 1689 } 1690 } else 1691 PCN_INIT_RXDESC(sc, i); 1692 } 1693 sc->sc_rxptr = 0; 1694 1695 /* Initialize MODE for the initialization block. */ 1696 sc->sc_mode = 0; 1697 if (ifp->if_flags & IFF_PROMISC) 1698 sc->sc_mode |= LE_C15_PROM; 1699 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1700 sc->sc_mode |= LE_C15_DRCVBC; 1701 1702 /* 1703 * If we have MII, simply select MII in the MODE register, 1704 * and clear ASEL. Otherwise, let ASEL stand (for now), 1705 * and leave PORTSEL alone (it is ignored with ASEL is set). 1706 */ 1707 if (sc->sc_flags & PCN_F_HAS_MII) { 1708 pcn_bcr_write(sc, LE_BCR2, 1709 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1710 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1711 1712 /* 1713 * Disable MII auto-negotiation. We handle that in 1714 * our own MII layer. 1715 */ 1716 pcn_bcr_write(sc, LE_BCR32, 1717 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1718 } 1719 1720 /* 1721 * Set the Tx and Rx descriptor ring addresses in the init 1722 * block, the TLEN and RLEN other fields of the init block 1723 * MODE register. 1724 */ 1725 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1726 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1727 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1728 ((ffs(PCN_NTXDESC) - 1) << 28) | 1729 ((ffs(PCN_NRXDESC) - 1) << 20)); 1730 1731 /* Set the station address in the init block. */ 1732 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1733 (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24)); 1734 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1735 (enaddr[5] << 8)); 1736 1737 /* Set the multicast filter in the init block. */ 1738 pcn_set_filter(sc); 1739 1740 /* Initialize CSR3. */ 1741 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO); 1742 1743 /* Initialize CSR4. */ 1744 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT| 1745 LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM); 1746 1747 /* Initialize CSR5. */ 1748 sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE; 1749 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1750 1751 /* 1752 * If we have an Am79c971 or greater, initialize CSR7. 1753 * 1754 * XXX Might be nice to use the MII auto-poll interrupt someday. 1755 */ 1756 switch (sc->sc_variant->pcv_chipid) { 1757 case PARTID_Am79c970: 1758 case PARTID_Am79c970A: 1759 /* Not available on these chips. */ 1760 break; 1761 1762 default: 1763 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1764 break; 1765 } 1766 1767 /* 1768 * On the Am79c970A and greater, initialize BCR18 to 1769 * enable burst mode. 1770 * 1771 * Also enable the "no underflow" option on the Am79c971 and 1772 * higher, which prevents the chip from generating transmit 1773 * underflows, yet sill provides decent performance. Note if 1774 * chip is not connected to external SRAM, then we still have 1775 * to handle underflow errors (the NOUFLO bit is ignored in 1776 * that case). 1777 */ 1778 reg = pcn_bcr_read(sc, LE_BCR18); 1779 switch (sc->sc_variant->pcv_chipid) { 1780 case PARTID_Am79c970: 1781 break; 1782 1783 case PARTID_Am79c970A: 1784 reg |= LE_B18_BREADE|LE_B18_BWRITE; 1785 break; 1786 1787 default: 1788 reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO; 1789 break; 1790 } 1791 pcn_bcr_write(sc, LE_BCR18, reg); 1792 1793 /* 1794 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1795 */ 1796 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1797 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1798 1799 /* 1800 * Send the init block to the chip, and wait for it 1801 * to be processed. 1802 */ 1803 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1804 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1805 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1806 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1807 delay(100); 1808 for (i = 0; i < 10000; i++) { 1809 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1810 break; 1811 delay(10); 1812 } 1813 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1814 if (i == 10000) { 1815 printf("%s: timeout processing init block\n", 1816 device_xname(sc->sc_dev)); 1817 error = EIO; 1818 goto out; 1819 } 1820 1821 /* Set the media. */ 1822 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1823 goto out; 1824 1825 /* Enable interrupts and external activity (and ACK IDON). */ 1826 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); 1827 1828 if (sc->sc_flags & PCN_F_HAS_MII) { 1829 /* Start the one second MII clock. */ 1830 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1831 } 1832 1833 /* ...all done! */ 1834 ifp->if_flags |= IFF_RUNNING; 1835 ifp->if_flags &= ~IFF_OACTIVE; 1836 1837 out: 1838 if (error) 1839 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1840 return (error); 1841 } 1842 1843 /* 1844 * pcn_rxdrain: 1845 * 1846 * Drain the receive queue. 1847 */ 1848 static void 1849 pcn_rxdrain(struct pcn_softc *sc) 1850 { 1851 struct pcn_rxsoft *rxs; 1852 int i; 1853 1854 for (i = 0; i < PCN_NRXDESC; i++) { 1855 rxs = &sc->sc_rxsoft[i]; 1856 if (rxs->rxs_mbuf != NULL) { 1857 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1858 m_freem(rxs->rxs_mbuf); 1859 rxs->rxs_mbuf = NULL; 1860 } 1861 } 1862 } 1863 1864 /* 1865 * pcn_stop: [ifnet interface function] 1866 * 1867 * Stop transmission on the interface. 1868 */ 1869 static void 1870 pcn_stop(struct ifnet *ifp, int disable) 1871 { 1872 struct pcn_softc *sc = ifp->if_softc; 1873 struct pcn_txsoft *txs; 1874 int i; 1875 1876 if (sc->sc_flags & PCN_F_HAS_MII) { 1877 /* Stop the one second clock. */ 1878 callout_stop(&sc->sc_tick_ch); 1879 1880 /* Down the MII. */ 1881 mii_down(&sc->sc_mii); 1882 } 1883 1884 /* Stop the chip. */ 1885 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1886 1887 /* Release any queued transmit buffers. */ 1888 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1889 txs = &sc->sc_txsoft[i]; 1890 if (txs->txs_mbuf != NULL) { 1891 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1892 m_freem(txs->txs_mbuf); 1893 txs->txs_mbuf = NULL; 1894 } 1895 } 1896 1897 /* Mark the interface as down and cancel the watchdog timer. */ 1898 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1899 ifp->if_timer = 0; 1900 1901 if (disable) 1902 pcn_rxdrain(sc); 1903 } 1904 1905 /* 1906 * pcn_add_rxbuf: 1907 * 1908 * Add a receive buffer to the indicated descriptor. 1909 */ 1910 static int 1911 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1912 { 1913 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1914 struct mbuf *m; 1915 int error; 1916 1917 MGETHDR(m, M_DONTWAIT, MT_DATA); 1918 if (m == NULL) 1919 return (ENOBUFS); 1920 1921 MCLGET(m, M_DONTWAIT); 1922 if ((m->m_flags & M_EXT) == 0) { 1923 m_freem(m); 1924 return (ENOBUFS); 1925 } 1926 1927 if (rxs->rxs_mbuf != NULL) 1928 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1929 1930 rxs->rxs_mbuf = m; 1931 1932 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1933 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1934 BUS_DMA_READ|BUS_DMA_NOWAIT); 1935 if (error) { 1936 printf("%s: can't load rx DMA map %d, error = %d\n", 1937 device_xname(sc->sc_dev), idx, error); 1938 panic("pcn_add_rxbuf"); 1939 } 1940 1941 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1942 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1943 1944 PCN_INIT_RXDESC(sc, idx); 1945 1946 return (0); 1947 } 1948 1949 /* 1950 * pcn_set_filter: 1951 * 1952 * Set up the receive filter. 1953 */ 1954 static void 1955 pcn_set_filter(struct pcn_softc *sc) 1956 { 1957 struct ethercom *ec = &sc->sc_ethercom; 1958 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1959 struct ether_multi *enm; 1960 struct ether_multistep step; 1961 uint32_t crc; 1962 1963 /* 1964 * Set up the multicast address filter by passing all multicast 1965 * addresses through a CRC generator, and then using the high 1966 * order 6 bits as an index into the 64-bit logical address 1967 * filter. The high order bits select the word, while the rest 1968 * of the bits select the bit within the word. 1969 */ 1970 1971 if (ifp->if_flags & IFF_PROMISC) 1972 goto allmulti; 1973 1974 sc->sc_initblock.init_ladrf[0] = 1975 sc->sc_initblock.init_ladrf[1] = 1976 sc->sc_initblock.init_ladrf[2] = 1977 sc->sc_initblock.init_ladrf[3] = 0; 1978 1979 ETHER_FIRST_MULTI(step, ec, enm); 1980 while (enm != NULL) { 1981 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1982 /* 1983 * We must listen to a range of multicast addresses. 1984 * For now, just accept all multicasts, rather than 1985 * trying to set only those filter bits needed to match 1986 * the range. (At this time, the only use of address 1987 * ranges is for IP multicast routing, for which the 1988 * range is big enough to require all bits set.) 1989 */ 1990 goto allmulti; 1991 } 1992 1993 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1994 1995 /* Just want the 6 most significant bits. */ 1996 crc >>= 26; 1997 1998 /* Set the corresponding bit in the filter. */ 1999 sc->sc_initblock.init_ladrf[crc >> 4] |= 2000 htole16(1 << (crc & 0xf)); 2001 2002 ETHER_NEXT_MULTI(step, enm); 2003 } 2004 2005 ifp->if_flags &= ~IFF_ALLMULTI; 2006 return; 2007 2008 allmulti: 2009 ifp->if_flags |= IFF_ALLMULTI; 2010 sc->sc_initblock.init_ladrf[0] = 2011 sc->sc_initblock.init_ladrf[1] = 2012 sc->sc_initblock.init_ladrf[2] = 2013 sc->sc_initblock.init_ladrf[3] = 0xffff; 2014 } 2015 2016 /* 2017 * pcn_79c970_mediainit: 2018 * 2019 * Initialize media for the Am79c970. 2020 */ 2021 static void 2022 pcn_79c970_mediainit(struct pcn_softc *sc) 2023 { 2024 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2025 const char *sep = ""; 2026 2027 sc->sc_mii.mii_ifp = ifp; 2028 2029 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, pcn_79c970_mediachange, 2030 pcn_79c970_mediastatus); 2031 2032 #define ADD(str, m, d) \ 2033 do { \ 2034 aprint_normal("%s%s", sep, str); \ 2035 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(m), (d), NULL); \ 2036 sep = ", "; \ 2037 } while (/*CONSTCOND*/0) 2038 2039 aprint_normal("%s: ", device_xname(sc->sc_dev)); 2040 ADD("10base5", IFM_10_5, PORTSEL_AUI); 2041 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2042 ADD("10base5-FDX", IFM_10_5|IFM_FDX, PORTSEL_AUI); 2043 ADD("10baseT", IFM_10_T, PORTSEL_10T); 2044 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2045 ADD("10baseT-FDX", IFM_10_T|IFM_FDX, PORTSEL_10T); 2046 ADD("auto", IFM_AUTO, 0); 2047 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2048 ADD("auto-FDX", IFM_AUTO|IFM_FDX, 0); 2049 aprint_normal("\n"); 2050 2051 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2052 } 2053 2054 /* 2055 * pcn_79c970_mediastatus: [ifmedia interface function] 2056 * 2057 * Get the current interface media status (Am79c970 version). 2058 */ 2059 static void 2060 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2061 { 2062 struct pcn_softc *sc = ifp->if_softc; 2063 2064 /* 2065 * The currently selected media is always the active media. 2066 * Note: We have no way to determine what media the AUTO 2067 * process picked. 2068 */ 2069 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 2070 } 2071 2072 /* 2073 * pcn_79c970_mediachange: [ifmedia interface function] 2074 * 2075 * Set hardware to newly-selected media (Am79c970 version). 2076 */ 2077 static int 2078 pcn_79c970_mediachange(struct ifnet *ifp) 2079 { 2080 struct pcn_softc *sc = ifp->if_softc; 2081 uint32_t reg; 2082 2083 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2084 /* 2085 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2086 */ 2087 reg = pcn_bcr_read(sc, LE_BCR2); 2088 reg |= LE_B2_ASEL; 2089 pcn_bcr_write(sc, LE_BCR2, reg); 2090 } else { 2091 /* 2092 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2093 */ 2094 reg = pcn_bcr_read(sc, LE_BCR2); 2095 reg &= ~LE_B2_ASEL; 2096 pcn_bcr_write(sc, LE_BCR2, reg); 2097 2098 reg = pcn_csr_read(sc, LE_CSR15); 2099 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2100 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2101 pcn_csr_write(sc, LE_CSR15, reg); 2102 } 2103 2104 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2105 reg = LE_B9_FDEN; 2106 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2107 reg |= LE_B9_AUIFD; 2108 pcn_bcr_write(sc, LE_BCR9, reg); 2109 } else 2110 pcn_bcr_write(sc, LE_BCR9, 0); 2111 2112 return (0); 2113 } 2114 2115 /* 2116 * pcn_79c971_mediainit: 2117 * 2118 * Initialize media for the Am79c971. 2119 */ 2120 static void 2121 pcn_79c971_mediainit(struct pcn_softc *sc) 2122 { 2123 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2124 2125 /* We have MII. */ 2126 sc->sc_flags |= PCN_F_HAS_MII; 2127 2128 /* 2129 * The built-in 10BASE-T interface is mapped to the MII 2130 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2131 * word that tells us which PHY to use. 2132 * This driver used to ignore all but the first PHY to 2133 * answer, but this code was removed to support multiple 2134 * external PHYs. As the default instance will be the first 2135 * one to answer, no harm is done by letting the possibly 2136 * non-connected internal PHY show up. 2137 */ 2138 2139 /* Initialize our media structures and probe the MII. */ 2140 sc->sc_mii.mii_ifp = ifp; 2141 sc->sc_mii.mii_readreg = pcn_mii_readreg; 2142 sc->sc_mii.mii_writereg = pcn_mii_writereg; 2143 sc->sc_mii.mii_statchg = pcn_mii_statchg; 2144 2145 sc->sc_ethercom.ec_mii = &sc->sc_mii; 2146 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 2147 ether_mediastatus); 2148 2149 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2150 MII_OFFSET_ANY, 0); 2151 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2152 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2153 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2154 } else 2155 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2156 } 2157 2158 /* 2159 * pcn_mii_readreg: [mii interface function] 2160 * 2161 * Read a PHY register on the MII. 2162 */ 2163 static int 2164 pcn_mii_readreg(device_t self, int phy, int reg) 2165 { 2166 struct pcn_softc *sc = device_private(self); 2167 uint32_t rv; 2168 2169 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2170 rv = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2171 if (rv == 0xffff) 2172 return (0); 2173 2174 return (rv); 2175 } 2176 2177 /* 2178 * pcn_mii_writereg: [mii interface function] 2179 * 2180 * Write a PHY register on the MII. 2181 */ 2182 static void 2183 pcn_mii_writereg(device_t self, int phy, int reg, int val) 2184 { 2185 struct pcn_softc *sc = device_private(self); 2186 2187 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2188 pcn_bcr_write(sc, LE_BCR34, val); 2189 } 2190 2191 /* 2192 * pcn_mii_statchg: [mii interface function] 2193 * 2194 * Callback from MII layer when media changes. 2195 */ 2196 static void 2197 pcn_mii_statchg(device_t self) 2198 { 2199 struct pcn_softc *sc = device_private(self); 2200 2201 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2202 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2203 else 2204 pcn_bcr_write(sc, LE_BCR9, 0); 2205 } 2206