1 /* $NetBSD: if_pcn.c,v 1.9 2002/05/03 00:16:12 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.9 2002/05/03 00:16:12 thorpej Exp $"); 69 70 #include "bpfilter.h" 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/callout.h> 75 #include <sys/mbuf.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/socket.h> 79 #include <sys/ioctl.h> 80 #include <sys/errno.h> 81 #include <sys/device.h> 82 #include <sys/queue.h> 83 84 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 85 86 #include <net/if.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 #include <net/if_ether.h> 90 91 #if NBPFILTER > 0 92 #include <net/bpf.h> 93 #endif 94 95 #include <machine/bus.h> 96 #include <machine/intr.h> 97 #include <machine/endian.h> 98 99 #include <dev/mii/mii.h> 100 #include <dev/mii/miivar.h> 101 102 #include <dev/ic/am79900reg.h> 103 #include <dev/ic/lancereg.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 109 #include <dev/pci/if_pcnreg.h> 110 111 /* 112 * Transmit descriptor list size. This is arbitrary, but allocate 113 * enough descriptors for 128 pending transmissions, and 4 segments 114 * per packet. This MUST work out to a power of 2. 115 * 116 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 117 * 118 * So we play a little trick here. We give each packet up to 16 119 * DMA segments, but only allocate the max of 512 descriptors. The 120 * transmit logic can deal with this, we just are hoping to sneak by. 121 */ 122 #define PCN_NTXSEGS 16 123 124 #define PCN_TXQUEUELEN 128 125 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 126 #define PCN_NTXDESC 512 127 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 128 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 129 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 130 131 /* Tx interrupt every N + 1 packets. */ 132 #define PCN_TXINTR_MASK 7 133 134 /* 135 * Receive descriptor list size. We have one Rx buffer per incoming 136 * packet, so this logic is a little simpler. 137 */ 138 #define PCN_NRXDESC 128 139 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 140 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 141 142 /* 143 * Control structures are DMA'd to the PCnet chip. We allocate them in 144 * a single clump that maps to a single DMA segment to make several things 145 * easier. 146 */ 147 struct pcn_control_data { 148 /* The transmit descriptors. */ 149 struct letmd pcd_txdescs[PCN_NTXDESC]; 150 151 /* The receive descriptors. */ 152 struct lermd pcd_rxdescs[PCN_NRXDESC]; 153 154 /* The init block. */ 155 struct leinit pcd_initblock; 156 }; 157 158 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 159 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 160 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 161 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 162 163 /* 164 * Software state for transmit jobs. 165 */ 166 struct pcn_txsoft { 167 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 168 bus_dmamap_t txs_dmamap; /* our DMA map */ 169 int txs_firstdesc; /* first descriptor in packet */ 170 int txs_lastdesc; /* last descriptor in packet */ 171 }; 172 173 /* 174 * Software state for receive jobs. 175 */ 176 struct pcn_rxsoft { 177 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 178 bus_dmamap_t rxs_dmamap; /* our DMA map */ 179 }; 180 181 /* 182 * Description of Rx FIFO watermarks for various revisions. 183 */ 184 const char *pcn_79c970_rcvfw[] = { 185 "16 bytes", 186 "64 bytes", 187 "128 bytes", 188 NULL, 189 }; 190 191 const char *pcn_79c971_rcvfw[] = { 192 "16 bytes", 193 "64 bytes", 194 "112 bytes", 195 NULL, 196 }; 197 198 /* 199 * Description of Tx start points for various revisions. 200 */ 201 const char *pcn_79c970_xmtsp[] = { 202 "8 bytes", 203 "64 bytes", 204 "128 bytes", 205 "248 bytes", 206 }; 207 208 const char *pcn_79c971_xmtsp[] = { 209 "20 bytes", 210 "64 bytes", 211 "128 bytes", 212 "248 bytes", 213 }; 214 215 const char *pcn_79c971_xmtsp_sram[] = { 216 "44 bytes", 217 "64 bytes", 218 "128 bytes", 219 "store-and-forward", 220 }; 221 222 /* 223 * Description of Tx FIFO watermarks for various revisions. 224 */ 225 const char *pcn_79c970_xmtfw[] = { 226 "16 bytes", 227 "64 bytes", 228 "128 bytes", 229 NULL, 230 }; 231 232 const char *pcn_79c971_xmtfw[] = { 233 "16 bytes", 234 "64 bytes", 235 "108 bytes", 236 NULL, 237 }; 238 239 /* 240 * Software state per device. 241 */ 242 struct pcn_softc { 243 struct device sc_dev; /* generic device information */ 244 bus_space_tag_t sc_st; /* bus space tag */ 245 bus_space_handle_t sc_sh; /* bus space handle */ 246 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 247 struct ethercom sc_ethercom; /* Ethernet common data */ 248 void *sc_sdhook; /* shutdown hook */ 249 250 /* Points to our media routines, etc. */ 251 const struct pcn_variant *sc_variant; 252 253 void *sc_ih; /* interrupt cookie */ 254 255 struct mii_data sc_mii; /* MII/media information */ 256 257 struct callout sc_tick_ch; /* tick callout */ 258 259 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 260 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 261 262 /* Software state for transmit and receive descriptors. */ 263 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 264 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 265 266 /* Control data structures */ 267 struct pcn_control_data *sc_control_data; 268 #define sc_txdescs sc_control_data->pcd_txdescs 269 #define sc_rxdescs sc_control_data->pcd_rxdescs 270 #define sc_initblock sc_control_data->pcd_initblock 271 272 #ifdef PCN_EVENT_COUNTERS 273 /* Event counters. */ 274 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 275 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 276 struct evcnt sc_ev_txintr; /* Tx interrupts */ 277 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 278 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 279 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 280 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 281 282 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 283 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 284 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 285 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 286 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 287 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 288 struct evcnt sc_ev_txcopy; /* Tx copies required */ 289 #endif /* PCN_EVENT_COUNTERS */ 290 291 const char **sc_rcvfw_desc; /* Rx FIFO watermark info */ 292 int sc_rcvfw; 293 294 const char **sc_xmtsp_desc; /* Tx start point info */ 295 int sc_xmtsp; 296 297 const char **sc_xmtfw_desc; /* Tx FIFO watermark info */ 298 int sc_xmtfw; 299 300 int sc_flags; /* misc. flags; see below */ 301 int sc_swstyle; /* the software style in use */ 302 303 int sc_txfree; /* number of free Tx descriptors */ 304 int sc_txnext; /* next ready Tx descriptor */ 305 306 int sc_txsfree; /* number of free Tx jobs */ 307 int sc_txsnext; /* next free Tx job */ 308 int sc_txsdirty; /* dirty Tx jobs */ 309 310 int sc_rxptr; /* next ready Rx descriptor/job */ 311 312 uint32_t sc_csr5; /* prototype CSR5 register */ 313 uint32_t sc_mode; /* prototype MODE register */ 314 int sc_phyaddr; /* PHY address */ 315 }; 316 317 /* sc_flags */ 318 #define PCN_F_HAS_MII 0x0001 /* has MII */ 319 320 #ifdef PCN_EVENT_COUNTERS 321 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 322 #else 323 #define PCN_EVCNT_INCR(ev) /* nothing */ 324 #endif 325 326 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 327 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 328 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 329 330 #define PCN_CDTXSYNC(sc, x, n, ops) \ 331 do { \ 332 int __x, __n; \ 333 \ 334 __x = (x); \ 335 __n = (n); \ 336 \ 337 /* If it will wrap around, sync to the end of the ring. */ \ 338 if ((__x + __n) > PCN_NTXDESC) { \ 339 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 340 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 341 (PCN_NTXDESC - __x), (ops)); \ 342 __n -= (PCN_NTXDESC - __x); \ 343 __x = 0; \ 344 } \ 345 \ 346 /* Now sync whatever is left. */ \ 347 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 348 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 349 } while (/*CONSTCOND*/0) 350 351 #define PCN_CDRXSYNC(sc, x, ops) \ 352 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 353 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 354 355 #define PCN_CDINITSYNC(sc, ops) \ 356 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 357 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 358 359 #define PCN_INIT_RXDESC(sc, x) \ 360 do { \ 361 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 362 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 363 struct mbuf *__m = __rxs->rxs_mbuf; \ 364 \ 365 /* \ 366 * Note: We scoot the packet forward 2 bytes in the buffer \ 367 * so that the payload after the Ethernet header is aligned \ 368 * to a 4-byte boundary. \ 369 */ \ 370 __m->m_data = __m->m_ext.ext_buf + 2; \ 371 \ 372 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 373 __rmd->rmd2 = \ 374 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 375 __rmd->rmd0 = 0; \ 376 } else { \ 377 __rmd->rmd2 = 0; \ 378 __rmd->rmd0 = \ 379 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 380 } \ 381 __rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| \ 382 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 383 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\ 384 } while(/*CONSTCOND*/0) 385 386 void pcn_start(struct ifnet *); 387 void pcn_watchdog(struct ifnet *); 388 int pcn_ioctl(struct ifnet *, u_long, caddr_t); 389 int pcn_init(struct ifnet *); 390 void pcn_stop(struct ifnet *, int); 391 392 void pcn_shutdown(void *); 393 394 void pcn_reset(struct pcn_softc *); 395 void pcn_rxdrain(struct pcn_softc *); 396 int pcn_add_rxbuf(struct pcn_softc *, int); 397 void pcn_tick(void *); 398 399 void pcn_spnd(struct pcn_softc *); 400 401 void pcn_set_filter(struct pcn_softc *); 402 403 int pcn_intr(void *); 404 void pcn_txintr(struct pcn_softc *); 405 int pcn_rxintr(struct pcn_softc *); 406 407 int pcn_mii_readreg(struct device *, int, int); 408 void pcn_mii_writereg(struct device *, int, int, int); 409 void pcn_mii_statchg(struct device *); 410 411 void pcn_79c970_mediainit(struct pcn_softc *); 412 int pcn_79c970_mediachange(struct ifnet *); 413 void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 414 415 void pcn_79c971_mediainit(struct pcn_softc *); 416 int pcn_79c971_mediachange(struct ifnet *); 417 void pcn_79c971_mediastatus(struct ifnet *, struct ifmediareq *); 418 419 /* 420 * Description of a PCnet-PCI variant. Used to select media access 421 * method, mostly, and to print a nice description of the chip. 422 */ 423 const struct pcn_variant { 424 const char *pcv_desc; 425 void (*pcv_mediainit)(struct pcn_softc *); 426 uint16_t pcv_chipid; 427 } pcn_variants[] = { 428 { "Am79c970 PCnet-PCI", 429 pcn_79c970_mediainit, 430 PARTID_Am79c970 }, 431 432 { "Am79c970A PCnet-PCI II", 433 pcn_79c970_mediainit, 434 PARTID_Am79c970A }, 435 436 { "Am79c971 PCnet-FAST", 437 pcn_79c971_mediainit, 438 PARTID_Am79c971 }, 439 440 { "Am79c972 PCnet-FAST+", 441 pcn_79c971_mediainit, 442 PARTID_Am79c972 }, 443 444 { "Am79c973 PCnet-FAST III", 445 pcn_79c971_mediainit, 446 PARTID_Am79c973 }, 447 448 { "Am79c975 PCnet-FAST III", 449 pcn_79c971_mediainit, 450 PARTID_Am79c975 }, 451 452 { "Unknown PCnet-PCI variant", 453 pcn_79c971_mediainit, 454 0 }, 455 }; 456 457 int pcn_copy_small = 0; 458 459 int pcn_match(struct device *, struct cfdata *, void *); 460 void pcn_attach(struct device *, struct device *, void *); 461 462 struct cfattach pcn_ca = { 463 sizeof(struct pcn_softc), pcn_match, pcn_attach, 464 }; 465 466 /* 467 * Routines to read and write the PCnet-PCI CSR/BCR space. 468 */ 469 470 static __inline uint32_t 471 pcn_csr_read(struct pcn_softc *sc, int reg) 472 { 473 474 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 475 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP)); 476 } 477 478 static __inline void 479 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 480 { 481 482 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 483 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 484 } 485 486 static __inline uint32_t 487 pcn_bcr_read(struct pcn_softc *sc, int reg) 488 { 489 490 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 491 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP)); 492 } 493 494 static __inline void 495 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 496 { 497 498 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 499 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 500 } 501 502 static const struct pcn_variant * 503 pcn_lookup_variant(uint16_t chipid) 504 { 505 const struct pcn_variant *pcv; 506 507 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 508 if (chipid == pcv->pcv_chipid) 509 return (pcv); 510 } 511 512 /* 513 * This covers unknown chips, which we simply treat like 514 * a generic PCnet-FAST. 515 */ 516 return (pcv); 517 } 518 519 int 520 pcn_match(struct device *parent, struct cfdata *cf, void *aux) 521 { 522 struct pci_attach_args *pa = aux; 523 524 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 525 return (0); 526 527 switch (PCI_PRODUCT(pa->pa_id)) { 528 case PCI_PRODUCT_AMD_PCNET_PCI: 529 /* Beat if_le_pci.c */ 530 return (10); 531 } 532 533 return (0); 534 } 535 536 void 537 pcn_attach(struct device *parent, struct device *self, void *aux) 538 { 539 struct pcn_softc *sc = (struct pcn_softc *) self; 540 struct pci_attach_args *pa = aux; 541 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 542 pci_chipset_tag_t pc = pa->pa_pc; 543 pci_intr_handle_t ih; 544 const char *intrstr = NULL; 545 bus_space_tag_t iot; 546 bus_space_handle_t ioh; 547 bus_dma_segment_t seg; 548 int ioh_valid; 549 int i, rseg, error; 550 pcireg_t pmode; 551 uint32_t chipid, reg; 552 uint8_t enaddr[ETHER_ADDR_LEN]; 553 int pmreg; 554 555 callout_init(&sc->sc_tick_ch); 556 557 printf(": AMD PCnet-PCI Ethernet\n"); 558 559 /* 560 * Map the device. 561 */ 562 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 563 &iot, &ioh, NULL, NULL) == 0); 564 565 if (ioh_valid) { 566 sc->sc_st = iot; 567 sc->sc_sh = ioh; 568 } else { 569 printf("%s: unable to map device registers\n", 570 sc->sc_dev.dv_xname); 571 return; 572 } 573 574 sc->sc_dmat = pa->pa_dmat; 575 576 /* Make sure bus mastering is enabled. */ 577 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 578 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 579 PCI_COMMAND_MASTER_ENABLE); 580 581 /* Get it out of power save mode, if needed. */ 582 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 583 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 584 if (pmode == 3) { 585 /* 586 * The card has lost all configuration data in 587 * this state, so punt. 588 */ 589 printf("%s: unable to wake from power state D3\n", 590 sc->sc_dev.dv_xname); 591 return; 592 } 593 if (pmode != 0) { 594 printf("%s: waking up from power date D%d\n", 595 sc->sc_dev.dv_xname, pmode); 596 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 597 } 598 } 599 600 /* 601 * Reset the chip to a known state. This also puts the 602 * chip into 32-bit mode. 603 */ 604 pcn_reset(sc); 605 606 /* 607 * Read the Ethernet address from the EEPROM. 608 */ 609 for (i = 0; i < ETHER_ADDR_LEN; i++) 610 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 611 PCN32_APROM + i); 612 613 /* 614 * Now that the device is mapped, attempt to figure out what 615 * kind of chip we have. Note that IDL has all 32 bits of 616 * the chip ID when we're in 32-bit mode. 617 */ 618 chipid = pcn_csr_read(sc, LE_CSR88); 619 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 620 621 printf("%s: %s rev %d, Ethernet address %s\n", 622 sc->sc_dev.dv_xname, sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 623 ether_sprintf(enaddr)); 624 625 /* 626 * Map and establish our interrupt. 627 */ 628 if (pci_intr_map(pa, &ih)) { 629 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 630 return; 631 } 632 intrstr = pci_intr_string(pc, ih); 633 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, pcn_intr, sc); 634 if (sc->sc_ih == NULL) { 635 printf("%s: unable to establish interrupt", 636 sc->sc_dev.dv_xname); 637 if (intrstr != NULL) 638 printf(" at %s", intrstr); 639 printf("\n"); 640 return; 641 } 642 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 643 644 /* 645 * Allocate the control data structures, and create and load the 646 * DMA map for it. 647 */ 648 if ((error = bus_dmamem_alloc(sc->sc_dmat, 649 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 650 0)) != 0) { 651 printf("%s: unable to allocate control data, error = %d\n", 652 sc->sc_dev.dv_xname, error); 653 goto fail_0; 654 } 655 656 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 657 sizeof(struct pcn_control_data), (caddr_t *)&sc->sc_control_data, 658 BUS_DMA_COHERENT)) != 0) { 659 printf("%s: unable to map control data, error = %d\n", 660 sc->sc_dev.dv_xname, error); 661 goto fail_1; 662 } 663 664 if ((error = bus_dmamap_create(sc->sc_dmat, 665 sizeof(struct pcn_control_data), 1, 666 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 667 printf("%s: unable to create control data DMA map, " 668 "error = %d\n", sc->sc_dev.dv_xname, error); 669 goto fail_2; 670 } 671 672 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 673 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 674 0)) != 0) { 675 printf("%s: unable to load control data DMA map, error = %d\n", 676 sc->sc_dev.dv_xname, error); 677 goto fail_3; 678 } 679 680 /* Create the transmit buffer DMA maps. */ 681 for (i = 0; i < PCN_TXQUEUELEN; i++) { 682 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 683 PCN_NTXSEGS, MCLBYTES, 0, 0, 684 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 685 printf("%s: unable to create tx DMA map %d, " 686 "error = %d\n", sc->sc_dev.dv_xname, i, error); 687 goto fail_4; 688 } 689 } 690 691 /* Create the receive buffer DMA maps. */ 692 for (i = 0; i < PCN_NRXDESC; i++) { 693 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 694 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 695 printf("%s: unable to create rx DMA map %d, " 696 "error = %d\n", sc->sc_dev.dv_xname, i, error); 697 goto fail_5; 698 } 699 sc->sc_rxsoft[i].rxs_mbuf = NULL; 700 } 701 702 /* Initialize our media structures. */ 703 (*sc->sc_variant->pcv_mediainit)(sc); 704 705 /* 706 * Initialize FIFO watermark info. 707 */ 708 switch (sc->sc_variant->pcv_chipid) { 709 case PARTID_Am79c970: 710 case PARTID_Am79c970A: 711 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 712 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 713 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 714 break; 715 716 default: 717 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 718 /* 719 * Read BCR25 to determine how much SRAM is 720 * on the board. If > 0, then we the chip 721 * uses different Start Point thresholds. 722 * 723 * Note BCR25 and BCR26 are loaded from the 724 * EEPROM on RST, and unaffected by S_RESET, 725 * so we don't really have to worry about 726 * them except for this. 727 */ 728 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 729 if (reg != 0) 730 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 731 else 732 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 733 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 734 break; 735 } 736 737 /* 738 * Set up defaults -- see the tables above for what these 739 * values mean. 740 * 741 * XXX How should we tune RCVFW and XMTFW? 742 */ 743 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 744 sc->sc_xmtsp = 1; 745 sc->sc_xmtfw = 0; 746 747 ifp = &sc->sc_ethercom.ec_if; 748 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 749 ifp->if_softc = sc; 750 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 751 ifp->if_ioctl = pcn_ioctl; 752 ifp->if_start = pcn_start; 753 ifp->if_watchdog = pcn_watchdog; 754 ifp->if_init = pcn_init; 755 ifp->if_stop = pcn_stop; 756 IFQ_SET_READY(&ifp->if_snd); 757 758 /* Attach the interface. */ 759 if_attach(ifp); 760 ether_ifattach(ifp, enaddr); 761 762 #ifdef PCN_EVENT_COUNTERS 763 /* Attach event counters. */ 764 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 765 NULL, sc->sc_dev.dv_xname, "txsstall"); 766 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 767 NULL, sc->sc_dev.dv_xname, "txdstall"); 768 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 769 NULL, sc->sc_dev.dv_xname, "txintr"); 770 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 771 NULL, sc->sc_dev.dv_xname, "rxintr"); 772 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 773 NULL, sc->sc_dev.dv_xname, "babl"); 774 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 775 NULL, sc->sc_dev.dv_xname, "miss"); 776 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 777 NULL, sc->sc_dev.dv_xname, "merr"); 778 779 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 780 NULL, sc->sc_dev.dv_xname, "txseg1"); 781 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 782 NULL, sc->sc_dev.dv_xname, "txseg2"); 783 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 784 NULL, sc->sc_dev.dv_xname, "txseg3"); 785 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 786 NULL, sc->sc_dev.dv_xname, "txseg4"); 787 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 788 NULL, sc->sc_dev.dv_xname, "txseg5"); 789 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 790 NULL, sc->sc_dev.dv_xname, "txsegmore"); 791 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 792 NULL, sc->sc_dev.dv_xname, "txcopy"); 793 #endif /* PCN_EVENT_COUNTERS */ 794 795 /* Make sure the interface is shutdown during reboot. */ 796 sc->sc_sdhook = shutdownhook_establish(pcn_shutdown, sc); 797 if (sc->sc_sdhook == NULL) 798 printf("%s: WARNING: unable to establish shutdown hook\n", 799 sc->sc_dev.dv_xname); 800 return; 801 802 /* 803 * Free any resources we've allocated during the failed attach 804 * attempt. Do this in reverse order and fall through. 805 */ 806 fail_5: 807 for (i = 0; i < PCN_NRXDESC; i++) { 808 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 809 bus_dmamap_destroy(sc->sc_dmat, 810 sc->sc_rxsoft[i].rxs_dmamap); 811 } 812 fail_4: 813 for (i = 0; i < PCN_TXQUEUELEN; i++) { 814 if (sc->sc_txsoft[i].txs_dmamap != NULL) 815 bus_dmamap_destroy(sc->sc_dmat, 816 sc->sc_txsoft[i].txs_dmamap); 817 } 818 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 819 fail_3: 820 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 821 fail_2: 822 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 823 sizeof(struct pcn_control_data)); 824 fail_1: 825 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 826 fail_0: 827 return; 828 } 829 830 /* 831 * pcn_shutdown: 832 * 833 * Make sure the interface is stopped at reboot time. 834 */ 835 void 836 pcn_shutdown(void *arg) 837 { 838 struct pcn_softc *sc = arg; 839 840 pcn_stop(&sc->sc_ethercom.ec_if, 1); 841 } 842 843 /* 844 * pcn_start: [ifnet interface function] 845 * 846 * Start packet transmission on the interface. 847 */ 848 void 849 pcn_start(struct ifnet *ifp) 850 { 851 struct pcn_softc *sc = ifp->if_softc; 852 struct mbuf *m0, *m; 853 struct pcn_txsoft *txs; 854 bus_dmamap_t dmamap; 855 int error, nexttx, lasttx, ofree, seg; 856 857 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 858 return; 859 860 /* 861 * Remember the previous number of free descriptors and 862 * the first descriptor we'll use. 863 */ 864 ofree = sc->sc_txfree; 865 866 /* 867 * Loop through the send queue, setting up transmit descriptors 868 * until we drain the queue, or use up all available transmit 869 * descriptors. 870 */ 871 for (;;) { 872 /* Grab a packet off the queue. */ 873 IFQ_POLL(&ifp->if_snd, m0); 874 if (m0 == NULL) 875 break; 876 m = NULL; 877 878 /* Get a work queue entry. */ 879 if (sc->sc_txsfree == 0) { 880 PCN_EVCNT_INCR(&sc->sc_ev_txsstall); 881 break; 882 } 883 884 txs = &sc->sc_txsoft[sc->sc_txsnext]; 885 dmamap = txs->txs_dmamap; 886 887 /* 888 * Load the DMA map. If this fails, the packet either 889 * didn't fit in the alloted number of segments, or we 890 * were short on resources. In this case, we'll copy 891 * and try again. 892 */ 893 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 894 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 895 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 896 MGETHDR(m, M_DONTWAIT, MT_DATA); 897 if (m == NULL) { 898 printf("%s: unable to allocate Tx mbuf\n", 899 sc->sc_dev.dv_xname); 900 break; 901 } 902 if (m0->m_pkthdr.len > MHLEN) { 903 MCLGET(m, M_DONTWAIT); 904 if ((m->m_flags & M_EXT) == 0) { 905 printf("%s: unable to allocate Tx " 906 "cluster\n", sc->sc_dev.dv_xname); 907 m_freem(m); 908 break; 909 } 910 } 911 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 912 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 913 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 914 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 915 if (error) { 916 printf("%s: unable to load Tx buffer, " 917 "error = %d\n", sc->sc_dev.dv_xname, error); 918 break; 919 } 920 } 921 922 /* 923 * Ensure we have enough descriptors free to describe 924 * the packet. Note, we always reserve one descriptor 925 * at the end of the ring as a termination point, to 926 * prevent wrap-around. 927 */ 928 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 929 /* 930 * Not enough free descriptors to transmit this 931 * packet. We haven't committed anything yet, 932 * so just unload the DMA map, put the packet 933 * back on the queue, and punt. Notify the upper 934 * layer that there are not more slots left. 935 * 936 * XXX We could allocate an mbuf and copy, but 937 * XXX is it worth it? 938 */ 939 ifp->if_flags |= IFF_OACTIVE; 940 bus_dmamap_unload(sc->sc_dmat, dmamap); 941 if (m != NULL) 942 m_freem(m); 943 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 944 break; 945 } 946 947 IFQ_DEQUEUE(&ifp->if_snd, m0); 948 if (m != NULL) { 949 m_freem(m0); 950 m0 = m; 951 } 952 953 /* 954 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 955 */ 956 957 /* Sync the DMA map. */ 958 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 959 BUS_DMASYNC_PREWRITE); 960 961 #ifdef PCN_EVENT_COUNTERS 962 switch (dmamap->dm_nsegs) { 963 case 1: 964 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 965 break; 966 case 2: 967 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 968 break; 969 case 3: 970 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 971 break; 972 case 4: 973 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 974 break; 975 case 5: 976 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 977 break; 978 default: 979 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 980 break; 981 } 982 #endif /* PCN_EVENT_COUNTERS */ 983 984 /* 985 * Initialize the transmit descriptors. 986 */ 987 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 988 for (nexttx = sc->sc_txnext, seg = 0; 989 seg < dmamap->dm_nsegs; 990 seg++, nexttx = PCN_NEXTTX(nexttx)) { 991 /* 992 * If this is the first descriptor we're 993 * enqueueing, don't set the OWN bit just 994 * yet. That could cause a race condition. 995 * We'll do it below. 996 */ 997 sc->sc_txdescs[nexttx].tmd0 = 0; 998 sc->sc_txdescs[nexttx].tmd2 = 999 htole32(dmamap->dm_segs[seg].ds_addr); 1000 sc->sc_txdescs[nexttx].tmd1 = 1001 htole32(LE_T1_ONES | 1002 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1003 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1004 LE_T1_BCNT_MASK)); 1005 lasttx = nexttx; 1006 } 1007 } else { 1008 for (nexttx = sc->sc_txnext, seg = 0; 1009 seg < dmamap->dm_nsegs; 1010 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1011 /* 1012 * If this is the first descriptor we're 1013 * enqueueing, don't set the OWN bit just 1014 * yet. That could cause a race condition. 1015 * We'll do it below. 1016 */ 1017 sc->sc_txdescs[nexttx].tmd0 = 1018 htole32(dmamap->dm_segs[seg].ds_addr); 1019 sc->sc_txdescs[nexttx].tmd2 = 0; 1020 sc->sc_txdescs[nexttx].tmd1 = 1021 htole32(LE_T1_ONES | 1022 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1023 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1024 LE_T1_BCNT_MASK)); 1025 lasttx = nexttx; 1026 } 1027 } 1028 1029 /* Interrupt on the packet, if appropriate. */ 1030 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1031 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1032 1033 /* Set `start of packet' and `end of packet' appropriately. */ 1034 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1035 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1036 htole32(LE_T1_OWN|LE_T1_STP); 1037 1038 /* Sync the descriptors we're using. */ 1039 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1040 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1041 1042 /* Kick the transmitter. */ 1043 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); 1044 1045 /* 1046 * Store a pointer to the packet so we can free it later, 1047 * and remember what txdirty will be once the packet is 1048 * done. 1049 */ 1050 txs->txs_mbuf = m0; 1051 txs->txs_firstdesc = sc->sc_txnext; 1052 txs->txs_lastdesc = lasttx; 1053 1054 /* Advance the tx pointer. */ 1055 sc->sc_txfree -= dmamap->dm_nsegs; 1056 sc->sc_txnext = nexttx; 1057 1058 sc->sc_txsfree--; 1059 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1060 1061 #if NBPFILTER > 0 1062 /* Pass the packet to any BPF listeners. */ 1063 if (ifp->if_bpf) 1064 bpf_mtap(ifp->if_bpf, m0); 1065 #endif /* NBPFILTER > 0 */ 1066 } 1067 1068 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1069 /* No more slots left; notify upper layer. */ 1070 ifp->if_flags |= IFF_OACTIVE; 1071 } 1072 1073 if (sc->sc_txfree != ofree) { 1074 /* Set a watchdog timer in case the chip flakes out. */ 1075 ifp->if_timer = 5; 1076 } 1077 } 1078 1079 /* 1080 * pcn_watchdog: [ifnet interface function] 1081 * 1082 * Watchdog timer handler. 1083 */ 1084 void 1085 pcn_watchdog(struct ifnet *ifp) 1086 { 1087 struct pcn_softc *sc = ifp->if_softc; 1088 1089 /* 1090 * Since we're not interrupting every packet, sweep 1091 * up before we report an error. 1092 */ 1093 pcn_txintr(sc); 1094 1095 if (sc->sc_txfree != PCN_NTXDESC) { 1096 printf("%s: device timeout (txfree %d txsfree %d)\n", 1097 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree); 1098 ifp->if_oerrors++; 1099 1100 /* Reset the interface. */ 1101 (void) pcn_init(ifp); 1102 } 1103 1104 /* Try to get more packets going. */ 1105 pcn_start(ifp); 1106 } 1107 1108 /* 1109 * pcn_ioctl: [ifnet interface function] 1110 * 1111 * Handle control requests from the operator. 1112 */ 1113 int 1114 pcn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1115 { 1116 struct pcn_softc *sc = ifp->if_softc; 1117 struct ifreq *ifr = (struct ifreq *) data; 1118 int s, error; 1119 1120 s = splnet(); 1121 1122 switch (cmd) { 1123 case SIOCSIFMEDIA: 1124 case SIOCGIFMEDIA: 1125 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1126 break; 1127 1128 default: 1129 error = ether_ioctl(ifp, cmd, data); 1130 if (error == ENETRESET) { 1131 /* 1132 * Multicast list has changed; set the hardware filter 1133 * accordingly. 1134 */ 1135 error = pcn_init(ifp); 1136 } 1137 break; 1138 } 1139 1140 /* Try to get more packets going. */ 1141 pcn_start(ifp); 1142 1143 splx(s); 1144 return (error); 1145 } 1146 1147 /* 1148 * pcn_intr: 1149 * 1150 * Interrupt service routine. 1151 */ 1152 int 1153 pcn_intr(void *arg) 1154 { 1155 struct pcn_softc *sc = arg; 1156 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1157 uint32_t csr0; 1158 int wantinit, handled = 0; 1159 1160 for (wantinit = 0; wantinit == 0;) { 1161 csr0 = pcn_csr_read(sc, LE_CSR0); 1162 if ((csr0 & LE_C0_INTR) == 0) 1163 break; 1164 1165 /* ACK the bits and re-enable interrupts. */ 1166 pcn_csr_write(sc, LE_CSR0, csr0 & 1167 (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT| 1168 LE_C0_TINT|LE_C0_IDON)); 1169 1170 handled = 1; 1171 1172 if (csr0 & LE_C0_RINT) { 1173 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1174 wantinit = pcn_rxintr(sc); 1175 } 1176 1177 if (csr0 & LE_C0_TINT) { 1178 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1179 pcn_txintr(sc); 1180 } 1181 1182 if (csr0 & LE_C0_ERR) { 1183 if (csr0 & LE_C0_BABL) { 1184 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1185 ifp->if_oerrors++; 1186 } 1187 if (csr0 & LE_C0_MISS) { 1188 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1189 ifp->if_ierrors++; 1190 } 1191 if (csr0 & LE_C0_MERR) { 1192 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1193 printf("%s: memory error\n", 1194 sc->sc_dev.dv_xname); 1195 wantinit = 1; 1196 break; 1197 } 1198 } 1199 1200 if ((csr0 & LE_C0_RXON) == 0) { 1201 printf("%s: receiver disabled\n", 1202 sc->sc_dev.dv_xname); 1203 ifp->if_ierrors++; 1204 wantinit = 1; 1205 } 1206 1207 if ((csr0 & LE_C0_TXON) == 0) { 1208 printf("%s: transmitter disabled\n", 1209 sc->sc_dev.dv_xname); 1210 ifp->if_oerrors++; 1211 wantinit = 1; 1212 } 1213 } 1214 1215 if (handled) { 1216 if (wantinit) 1217 pcn_init(ifp); 1218 1219 /* Try to get more packets going. */ 1220 pcn_start(ifp); 1221 } 1222 1223 return (handled); 1224 } 1225 1226 /* 1227 * pcn_spnd: 1228 * 1229 * Suspend the chip. 1230 */ 1231 void 1232 pcn_spnd(struct pcn_softc *sc) 1233 { 1234 int i; 1235 1236 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1237 1238 for (i = 0; i < 10000; i++) { 1239 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1240 return; 1241 delay(5); 1242 } 1243 1244 printf("%s: WARNING: chip failed to enter suspended state\n", 1245 sc->sc_dev.dv_xname); 1246 } 1247 1248 /* 1249 * pcn_txintr: 1250 * 1251 * Helper; handle transmit interrupts. 1252 */ 1253 void 1254 pcn_txintr(struct pcn_softc *sc) 1255 { 1256 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1257 struct pcn_txsoft *txs; 1258 uint32_t tmd1, tmd2, tmd; 1259 int i, j; 1260 1261 ifp->if_flags &= ~IFF_OACTIVE; 1262 1263 /* 1264 * Go through our Tx list and free mbufs for those 1265 * frames which have been transmitted. 1266 */ 1267 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1268 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1269 txs = &sc->sc_txsoft[i]; 1270 1271 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1272 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1273 1274 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1275 if (tmd1 & LE_T1_OWN) 1276 break; 1277 1278 /* 1279 * Slightly annoying -- we have to loop through the 1280 * descriptors we've used looking for ERR, since it 1281 * can appear on any descriptor in the chain. 1282 */ 1283 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1284 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1285 if (tmd & LE_T1_ERR) { 1286 ifp->if_oerrors++; 1287 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1288 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1289 else 1290 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1291 if (tmd2 & LE_T2_UFLO) { 1292 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1293 sc->sc_xmtsp++; 1294 printf("%s: transmit " 1295 "underrun; new threshold: " 1296 "%s\n", 1297 sc->sc_dev.dv_xname, 1298 sc->sc_xmtsp_desc[ 1299 sc->sc_xmtsp]); 1300 pcn_spnd(sc); 1301 pcn_csr_write(sc, LE_CSR80, 1302 LE_C80_RCVFW(sc->sc_rcvfw) | 1303 LE_C80_XMTSP(sc->sc_xmtsp) | 1304 LE_C80_XMTFW(sc->sc_xmtfw)); 1305 pcn_csr_write(sc, LE_CSR5, 1306 sc->sc_csr5); 1307 } else { 1308 printf("%s: transmit " 1309 "underrun\n", 1310 sc->sc_dev.dv_xname); 1311 } 1312 } else if (tmd2 & LE_T2_BUFF) { 1313 printf("%s: transmit buffer error\n", 1314 sc->sc_dev.dv_xname); 1315 } 1316 if (tmd2 & LE_T2_LCOL) 1317 ifp->if_collisions++; 1318 if (tmd2 & LE_T2_RTRY) 1319 ifp->if_collisions += 16; 1320 goto next_packet; 1321 } 1322 if (j == txs->txs_lastdesc) 1323 break; 1324 } 1325 if (tmd1 & LE_T1_ONE) 1326 ifp->if_collisions++; 1327 else if (tmd & LE_T1_MORE) { 1328 /* Real number is unknown. */ 1329 ifp->if_collisions += 2; 1330 } 1331 ifp->if_opackets++; 1332 next_packet: 1333 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1334 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1335 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1336 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1337 m_freem(txs->txs_mbuf); 1338 txs->txs_mbuf = NULL; 1339 } 1340 1341 /* Update the dirty transmit buffer pointer. */ 1342 sc->sc_txsdirty = i; 1343 1344 /* 1345 * If there are no more pending transmissions, cancel the watchdog 1346 * timer. 1347 */ 1348 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1349 ifp->if_timer = 0; 1350 } 1351 1352 /* 1353 * pcn_rxintr: 1354 * 1355 * Helper; handle receive interrupts. 1356 */ 1357 int 1358 pcn_rxintr(struct pcn_softc *sc) 1359 { 1360 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1361 struct pcn_rxsoft *rxs; 1362 struct mbuf *m; 1363 uint32_t rmd1; 1364 int i, len; 1365 1366 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1367 rxs = &sc->sc_rxsoft[i]; 1368 1369 PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1370 1371 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1372 1373 if (rmd1 & LE_R1_OWN) 1374 break; 1375 1376 /* 1377 * Check for errors and make sure the packet fit into 1378 * a single buffer. We have structured this block of 1379 * code the way it is in order to compress it into 1380 * one test in the common case (no error). 1381 */ 1382 if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) != 1383 (LE_R1_STP|LE_R1_ENP))) { 1384 /* Make sure the packet is in a single buffer. */ 1385 if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) != 1386 (LE_R1_STP|LE_R1_ENP)) { 1387 printf("%s: packet spilled into next buffer\n", 1388 sc->sc_dev.dv_xname); 1389 return (1); /* pcn_intr() will re-init */ 1390 } 1391 1392 /* 1393 * If the packet had an error, simple recycle the 1394 * buffer. 1395 */ 1396 if (rmd1 & LE_R1_ERR) { 1397 ifp->if_ierrors++; 1398 /* 1399 * If we got an overflow error, chances 1400 * are there will be a CRC error. In 1401 * this case, just print the overflow 1402 * error, and skip the others. 1403 */ 1404 if (rmd1 & LE_R1_OFLO) 1405 printf("%s: overflow error\n", 1406 sc->sc_dev.dv_xname); 1407 else { 1408 #define PRINTIT(x, s) \ 1409 if (rmd1 & (x)) \ 1410 printf("%s: %s\n", \ 1411 sc->sc_dev.dv_xname, s); 1412 PRINTIT(LE_R1_FRAM, "framing error"); 1413 PRINTIT(LE_R1_CRC, "CRC error"); 1414 PRINTIT(LE_R1_BUFF, "buffer error"); 1415 } 1416 #undef PRINTIT 1417 PCN_INIT_RXDESC(sc, i); 1418 continue; 1419 } 1420 } 1421 1422 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1423 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1424 1425 /* 1426 * No errors; receive the packet. 1427 */ 1428 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1429 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1430 else 1431 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1432 1433 /* 1434 * The LANCE family includes the CRC with every packet; 1435 * trim it off here. 1436 */ 1437 len -= ETHER_CRC_LEN; 1438 1439 /* 1440 * If the packet is small enough to fit in a 1441 * single header mbuf, allocate one and copy 1442 * the data into it. This greatly reduces 1443 * memory consumption when we receive lots 1444 * of small packets. 1445 * 1446 * Otherwise, we add a new buffer to the receive 1447 * chain. If this fails, we drop the packet and 1448 * recycle the old buffer. 1449 */ 1450 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1451 MGETHDR(m, M_DONTWAIT, MT_DATA); 1452 if (m == NULL) 1453 goto dropit; 1454 m->m_data += 2; 1455 memcpy(mtod(m, caddr_t), 1456 mtod(rxs->rxs_mbuf, caddr_t), len); 1457 PCN_INIT_RXDESC(sc, i); 1458 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1459 rxs->rxs_dmamap->dm_mapsize, 1460 BUS_DMASYNC_PREREAD); 1461 } else { 1462 m = rxs->rxs_mbuf; 1463 if (pcn_add_rxbuf(sc, i) != 0) { 1464 dropit: 1465 ifp->if_ierrors++; 1466 PCN_INIT_RXDESC(sc, i); 1467 bus_dmamap_sync(sc->sc_dmat, 1468 rxs->rxs_dmamap, 0, 1469 rxs->rxs_dmamap->dm_mapsize, 1470 BUS_DMASYNC_PREREAD); 1471 continue; 1472 } 1473 } 1474 1475 m->m_pkthdr.rcvif = ifp; 1476 m->m_pkthdr.len = m->m_len = len; 1477 1478 #if NBPFILTER > 0 1479 /* Pass this up to any BPF listeners. */ 1480 if (ifp->if_bpf) 1481 bpf_mtap(ifp->if_bpf, m); 1482 #endif /* NBPFILTER > 0 */ 1483 1484 /* Pass it on. */ 1485 (*ifp->if_input)(ifp, m); 1486 ifp->if_ipackets++; 1487 } 1488 1489 /* Update the receive pointer. */ 1490 sc->sc_rxptr = i; 1491 return (0); 1492 } 1493 1494 /* 1495 * pcn_tick: 1496 * 1497 * One second timer, used to tick the MII. 1498 */ 1499 void 1500 pcn_tick(void *arg) 1501 { 1502 struct pcn_softc *sc = arg; 1503 int s; 1504 1505 s = splnet(); 1506 mii_tick(&sc->sc_mii); 1507 splx(s); 1508 1509 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1510 } 1511 1512 /* 1513 * pcn_reset: 1514 * 1515 * Perform a soft reset on the PCnet-PCI. 1516 */ 1517 void 1518 pcn_reset(struct pcn_softc *sc) 1519 { 1520 1521 /* 1522 * The PCnet-PCI chip is reset by reading from the 1523 * RESET register. Note that while the NE2100 LANCE 1524 * boards require a write after the read, the PCnet-PCI 1525 * chips do not require this. 1526 * 1527 * Since we don't know if we're in 16-bit or 32-bit 1528 * mode right now, issue both (it's safe) in the 1529 * hopes that one will succeed. 1530 */ 1531 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1532 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1533 1534 /* Wait 1ms for it to finish. */ 1535 delay(1000); 1536 1537 /* 1538 * Select 32-bit I/O mode by issuing a 32-bit write to the 1539 * RDP. Since the RAP is 0 after a reset, writing a 0 1540 * to RDP is safe (since it simply clears CSR0). 1541 */ 1542 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1543 } 1544 1545 /* 1546 * pcn_init: [ifnet interface function] 1547 * 1548 * Initialize the interface. Must be called at splnet(). 1549 */ 1550 int 1551 pcn_init(struct ifnet *ifp) 1552 { 1553 struct pcn_softc *sc = ifp->if_softc; 1554 struct pcn_rxsoft *rxs; 1555 uint8_t *enaddr = LLADDR(ifp->if_sadl); 1556 int i, error = 0; 1557 uint32_t reg; 1558 1559 /* Cancel any pending I/O. */ 1560 pcn_stop(ifp, 0); 1561 1562 /* Reset the chip to a known state. */ 1563 pcn_reset(sc); 1564 1565 /* 1566 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1567 * else. 1568 * 1569 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1570 * because the structure layout is compatible with ILACC, 1571 * but the burst mode is only available in SSTYLE 3, and 1572 * burst mode should provide some performance enhancement. 1573 */ 1574 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1575 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1576 else 1577 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1578 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1579 1580 /* Initialize the transmit descriptor ring. */ 1581 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1582 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1583 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1584 sc->sc_txfree = PCN_NTXDESC; 1585 sc->sc_txnext = 0; 1586 1587 /* Initialize the transmit job descriptors. */ 1588 for (i = 0; i < PCN_TXQUEUELEN; i++) 1589 sc->sc_txsoft[i].txs_mbuf = NULL; 1590 sc->sc_txsfree = PCN_TXQUEUELEN; 1591 sc->sc_txsnext = 0; 1592 sc->sc_txsdirty = 0; 1593 1594 /* 1595 * Initialize the receive descriptor and receive job 1596 * descriptor rings. 1597 */ 1598 for (i = 0; i < PCN_NRXDESC; i++) { 1599 rxs = &sc->sc_rxsoft[i]; 1600 if (rxs->rxs_mbuf == NULL) { 1601 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1602 printf("%s: unable to allocate or map rx " 1603 "buffer %d, error = %d\n", 1604 sc->sc_dev.dv_xname, i, error); 1605 /* 1606 * XXX Should attempt to run with fewer receive 1607 * XXX buffers instead of just failing. 1608 */ 1609 pcn_rxdrain(sc); 1610 goto out; 1611 } 1612 } else 1613 PCN_INIT_RXDESC(sc, i); 1614 } 1615 sc->sc_rxptr = 0; 1616 1617 /* Initialize MODE for the initialization block. */ 1618 sc->sc_mode = 0; 1619 if (ifp->if_flags & IFF_PROMISC) 1620 sc->sc_mode |= LE_C15_PROM; 1621 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1622 sc->sc_mode |= LE_C15_DRCVBC; 1623 1624 /* 1625 * If we have MII, simply select MII in the MODE register, 1626 * and clear ASEL. Otherwise, let ASEL stand (for now), 1627 * and leave PORTSEL alone (it is ignored with ASEL is set). 1628 */ 1629 if (sc->sc_flags & PCN_F_HAS_MII) { 1630 pcn_bcr_write(sc, LE_BCR2, 1631 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1632 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1633 1634 /* 1635 * Disable MII auto-negotiation. We handle that in 1636 * our own MII layer. 1637 */ 1638 pcn_bcr_write(sc, LE_BCR32, 1639 pcn_csr_read(sc, LE_BCR32) | LE_B32_DANAS); 1640 } 1641 1642 /* 1643 * Set the Tx and Rx descriptor ring addresses in the init 1644 * block, the TLEN and RLEN other fields of the init block 1645 * MODE register. 1646 */ 1647 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1648 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1649 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1650 ((ffs(PCN_NTXDESC) - 1) << 28) | 1651 ((ffs(PCN_NRXDESC) - 1) << 20)); 1652 1653 /* Set the station address in the init block. */ 1654 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1655 (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24)); 1656 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1657 (enaddr[5] << 8)); 1658 1659 /* Set the multicast filter in the init block. */ 1660 pcn_set_filter(sc); 1661 1662 /* Initialize CSR3. */ 1663 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO); 1664 1665 /* Initialize CSR4. */ 1666 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT| 1667 LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM); 1668 1669 /* Initialize CSR5. */ 1670 sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE; 1671 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1672 1673 /* 1674 * If we have an Am79c971 or greater, initialize CSR7. 1675 * 1676 * XXX Might be nice to use the MII auto-poll interrupt someday. 1677 */ 1678 switch (sc->sc_variant->pcv_chipid) { 1679 case PARTID_Am79c970: 1680 case PARTID_Am79c970A: 1681 /* Not available on these chips. */ 1682 break; 1683 1684 default: 1685 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1686 break; 1687 } 1688 1689 /* 1690 * On the Am79c970A and greater, initialize BCR18 to 1691 * enable burst mode. 1692 * 1693 * Also enable the "no underflow" option on the Am79c971 and 1694 * higher, which prevents the chip from generating transmit 1695 * underflows, yet sill provides decent performance. Note if 1696 * chip is not connected to external SRAM, then we still have 1697 * to handle underflow errors (the NOUFLO bit is ignored in 1698 * that case). 1699 */ 1700 reg = pcn_bcr_read(sc, LE_BCR18); 1701 switch (sc->sc_variant->pcv_chipid) { 1702 case PARTID_Am79c970: 1703 break; 1704 1705 case PARTID_Am79c970A: 1706 reg |= LE_B18_BREADE|LE_B18_BWRITE; 1707 break; 1708 1709 default: 1710 reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO; 1711 break; 1712 } 1713 pcn_bcr_write(sc, LE_BCR18, reg); 1714 1715 /* 1716 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1717 */ 1718 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1719 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1720 1721 /* 1722 * Send the init block to the chip, and wait for it 1723 * to be processed. 1724 */ 1725 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1726 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1727 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1728 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1729 delay(100); 1730 for (i = 0; i < 10000; i++) { 1731 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1732 break; 1733 delay(10); 1734 } 1735 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1736 if (i == 10000) { 1737 printf("%s: timeout processing init block\n", 1738 sc->sc_dev.dv_xname); 1739 error = EIO; 1740 goto out; 1741 } 1742 1743 /* Set the media. */ 1744 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 1745 1746 /* Enable interrupts and external activity (and ACK IDON). */ 1747 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); 1748 1749 if (sc->sc_flags & PCN_F_HAS_MII) { 1750 /* Start the one second MII clock. */ 1751 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1752 } 1753 1754 /* ...all done! */ 1755 ifp->if_flags |= IFF_RUNNING; 1756 ifp->if_flags &= ~IFF_OACTIVE; 1757 1758 out: 1759 if (error) 1760 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1761 return (error); 1762 } 1763 1764 /* 1765 * pcn_rxdrain: 1766 * 1767 * Drain the receive queue. 1768 */ 1769 void 1770 pcn_rxdrain(struct pcn_softc *sc) 1771 { 1772 struct pcn_rxsoft *rxs; 1773 int i; 1774 1775 for (i = 0; i < PCN_NRXDESC; i++) { 1776 rxs = &sc->sc_rxsoft[i]; 1777 if (rxs->rxs_mbuf != NULL) { 1778 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1779 m_freem(rxs->rxs_mbuf); 1780 rxs->rxs_mbuf = NULL; 1781 } 1782 } 1783 } 1784 1785 /* 1786 * pcn_stop: [ifnet interface function] 1787 * 1788 * Stop transmission on the interface. 1789 */ 1790 void 1791 pcn_stop(struct ifnet *ifp, int disable) 1792 { 1793 struct pcn_softc *sc = ifp->if_softc; 1794 struct pcn_txsoft *txs; 1795 int i; 1796 1797 if (sc->sc_flags & PCN_F_HAS_MII) { 1798 /* Stop the one second clock. */ 1799 callout_stop(&sc->sc_tick_ch); 1800 1801 /* Down the MII. */ 1802 mii_down(&sc->sc_mii); 1803 } 1804 1805 /* Stop the chip. */ 1806 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1807 1808 /* Release any queued transmit buffers. */ 1809 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1810 txs = &sc->sc_txsoft[i]; 1811 if (txs->txs_mbuf != NULL) { 1812 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1813 m_freem(txs->txs_mbuf); 1814 txs->txs_mbuf = NULL; 1815 } 1816 } 1817 1818 if (disable) 1819 pcn_rxdrain(sc); 1820 1821 /* Mark the interface as down and cancel the watchdog timer. */ 1822 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1823 ifp->if_timer = 0; 1824 } 1825 1826 /* 1827 * pcn_add_rxbuf: 1828 * 1829 * Add a receive buffer to the indicated descriptor. 1830 */ 1831 int 1832 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1833 { 1834 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1835 struct mbuf *m; 1836 int error; 1837 1838 MGETHDR(m, M_DONTWAIT, MT_DATA); 1839 if (m == NULL) 1840 return (ENOBUFS); 1841 1842 MCLGET(m, M_DONTWAIT); 1843 if ((m->m_flags & M_EXT) == 0) { 1844 m_freem(m); 1845 return (ENOBUFS); 1846 } 1847 1848 if (rxs->rxs_mbuf != NULL) 1849 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1850 1851 rxs->rxs_mbuf = m; 1852 1853 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1854 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1855 BUS_DMA_READ|BUS_DMA_NOWAIT); 1856 if (error) { 1857 printf("%s: can't load rx DMA map %d, error = %d\n", 1858 sc->sc_dev.dv_xname, idx, error); 1859 panic("pcn_add_rxbuf"); 1860 } 1861 1862 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1863 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1864 1865 PCN_INIT_RXDESC(sc, idx); 1866 1867 return (0); 1868 } 1869 1870 /* 1871 * pcn_set_filter: 1872 * 1873 * Set up the receive filter. 1874 */ 1875 void 1876 pcn_set_filter(struct pcn_softc *sc) 1877 { 1878 struct ethercom *ec = &sc->sc_ethercom; 1879 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1880 struct ether_multi *enm; 1881 struct ether_multistep step; 1882 uint32_t crc; 1883 1884 /* 1885 * Set up the multicast address filter by passing all multicast 1886 * addresses through a CRC generator, and then using the high 1887 * order 6 bits as an index into the 64-bit logical address 1888 * filter. The high order bits select the word, while the rest 1889 * of the bits select the bit within the word. 1890 */ 1891 1892 if (ifp->if_flags & IFF_PROMISC) 1893 goto allmulti; 1894 1895 sc->sc_initblock.init_ladrf[0] = 1896 sc->sc_initblock.init_ladrf[1] = 1897 sc->sc_initblock.init_ladrf[2] = 1898 sc->sc_initblock.init_ladrf[3] = 0; 1899 1900 ETHER_FIRST_MULTI(step, ec, enm); 1901 while (enm != NULL) { 1902 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1903 /* 1904 * We must listen to a range of multicast addresses. 1905 * For now, just accept all multicasts, rather than 1906 * trying to set only those filter bits needed to match 1907 * the range. (At this time, the only use of address 1908 * ranges is for IP multicast routing, for which the 1909 * range is big enough to require all bits set.) 1910 */ 1911 goto allmulti; 1912 } 1913 1914 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1915 1916 /* Just want the 6 most significant bits. */ 1917 crc >>= 26; 1918 1919 /* Set the corresponding bit in the filter. */ 1920 sc->sc_initblock.init_ladrf[crc >> 4] |= 1921 htole16(1 << (crc & 0xf)); 1922 1923 ETHER_NEXT_MULTI(step, enm); 1924 } 1925 1926 ifp->if_flags &= ~IFF_ALLMULTI; 1927 return; 1928 1929 allmulti: 1930 ifp->if_flags |= IFF_ALLMULTI; 1931 sc->sc_initblock.init_ladrf[0] = 1932 sc->sc_initblock.init_ladrf[1] = 1933 sc->sc_initblock.init_ladrf[2] = 1934 sc->sc_initblock.init_ladrf[3] = 0xffff; 1935 } 1936 1937 /* 1938 * pcn_79c970_mediainit: 1939 * 1940 * Initialize media for the Am79c970. 1941 */ 1942 void 1943 pcn_79c970_mediainit(struct pcn_softc *sc) 1944 { 1945 const char *sep = ""; 1946 1947 ifmedia_init(&sc->sc_mii.mii_media, 0, pcn_79c970_mediachange, 1948 pcn_79c970_mediastatus); 1949 1950 #define ADD(s, m, d) \ 1951 do { \ 1952 printf("%s%s", sep, s); \ 1953 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(m), (d), NULL); \ 1954 sep = ", "; \ 1955 } while (/*CONSTCOND*/0) 1956 1957 printf("%s: ", sc->sc_dev.dv_xname); 1958 ADD("10base5", IFM_10_5, PORTSEL_AUI); 1959 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1960 ADD("10base5-FDX", IFM_10_5|IFM_FDX, PORTSEL_AUI); 1961 ADD("10baseT", IFM_10_T, PORTSEL_10T); 1962 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1963 ADD("10baseT-FDX", IFM_10_T|IFM_FDX, PORTSEL_10T); 1964 ADD("auto", IFM_AUTO, 0); 1965 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1966 ADD("auto-FDX", IFM_AUTO|IFM_FDX, 0); 1967 printf("\n"); 1968 1969 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1970 } 1971 1972 /* 1973 * pcn_79c970_mediastatus: [ifmedia interface function] 1974 * 1975 * Get the current interface media status (Am79c970 version). 1976 */ 1977 void 1978 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1979 { 1980 struct pcn_softc *sc = ifp->if_softc; 1981 1982 /* 1983 * The currently selected media is always the active media. 1984 * Note: We have no way to determine what media the AUTO 1985 * process picked. 1986 */ 1987 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 1988 } 1989 1990 /* 1991 * pcn_79c970_mediachange: [ifmedia interface function] 1992 * 1993 * Set hardware to newly-selected media (Am79c970 version). 1994 */ 1995 int 1996 pcn_79c970_mediachange(struct ifnet *ifp) 1997 { 1998 struct pcn_softc *sc = ifp->if_softc; 1999 uint32_t reg; 2000 2001 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2002 /* 2003 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2004 */ 2005 reg = pcn_bcr_read(sc, LE_BCR2); 2006 reg |= LE_B2_ASEL; 2007 pcn_bcr_write(sc, LE_BCR2, reg); 2008 } else { 2009 /* 2010 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2011 */ 2012 reg = pcn_bcr_read(sc, LE_BCR2); 2013 reg &= ~LE_B2_ASEL; 2014 pcn_bcr_write(sc, LE_BCR2, reg); 2015 2016 reg = pcn_csr_read(sc, LE_CSR15); 2017 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2018 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2019 pcn_csr_write(sc, LE_CSR15, reg); 2020 } 2021 2022 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2023 reg = LE_B9_FDEN; 2024 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2025 reg |= LE_B9_AUIFD; 2026 pcn_bcr_write(sc, LE_BCR9, reg); 2027 } else 2028 pcn_bcr_write(sc, LE_BCR0, 0); 2029 2030 return (0); 2031 } 2032 2033 /* 2034 * pcn_79c971_mediainit: 2035 * 2036 * Initialize media for the Am79c971. 2037 */ 2038 void 2039 pcn_79c971_mediainit(struct pcn_softc *sc) 2040 { 2041 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2042 2043 /* We have MII. */ 2044 sc->sc_flags |= PCN_F_HAS_MII; 2045 2046 /* 2047 * The built-in 10BASE-T interface is mapped to the MII 2048 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2049 * word that tells us which PHY to use. Since the 10BASE-T 2050 * interface is always at PHY 31, we make a note of the 2051 * first PHY that responds, and disallow any PHYs after 2052 * it. This is all handled in the MII read routine. 2053 */ 2054 sc->sc_phyaddr = -1; 2055 2056 /* Initialize our media structures and probe the MII. */ 2057 sc->sc_mii.mii_ifp = ifp; 2058 sc->sc_mii.mii_readreg = pcn_mii_readreg; 2059 sc->sc_mii.mii_writereg = pcn_mii_writereg; 2060 sc->sc_mii.mii_statchg = pcn_mii_statchg; 2061 ifmedia_init(&sc->sc_mii.mii_media, 0, pcn_79c971_mediachange, 2062 pcn_79c971_mediastatus); 2063 2064 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2065 MII_OFFSET_ANY, 0); 2066 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2067 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2068 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2069 } else 2070 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2071 } 2072 2073 /* 2074 * pcn_79c971_mediastatus: [ifmedia interface function] 2075 * 2076 * Get the current interface media status (Am79c971 version). 2077 */ 2078 void 2079 pcn_79c971_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2080 { 2081 struct pcn_softc *sc = ifp->if_softc; 2082 2083 mii_pollstat(&sc->sc_mii); 2084 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2085 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2086 } 2087 2088 /* 2089 * pcn_79c971_mediachange: [ifmedia interface function] 2090 * 2091 * Set hardware to newly-selected media (Am79c971 version). 2092 */ 2093 int 2094 pcn_79c971_mediachange(struct ifnet *ifp) 2095 { 2096 struct pcn_softc *sc = ifp->if_softc; 2097 2098 if (ifp->if_flags & IFF_UP) 2099 mii_mediachg(&sc->sc_mii); 2100 return (0); 2101 } 2102 2103 /* 2104 * pcn_mii_readreg: [mii interface function] 2105 * 2106 * Read a PHY register on the MII. 2107 */ 2108 int 2109 pcn_mii_readreg(struct device *self, int phy, int reg) 2110 { 2111 struct pcn_softc *sc = (void *) self; 2112 uint32_t rv; 2113 2114 if (sc->sc_phyaddr != -1 && phy != sc->sc_phyaddr) 2115 return (0); 2116 2117 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2118 rv = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2119 if (rv == 0xffff) 2120 return (0); 2121 2122 if (sc->sc_phyaddr == -1) 2123 sc->sc_phyaddr = phy; 2124 2125 return (rv); 2126 } 2127 2128 /* 2129 * pcn_mii_writereg: [mii interface function] 2130 * 2131 * Write a PHY register on the MII. 2132 */ 2133 void 2134 pcn_mii_writereg(struct device *self, int phy, int reg, int val) 2135 { 2136 struct pcn_softc *sc = (void *) self; 2137 2138 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2139 pcn_bcr_write(sc, LE_BCR34, val); 2140 } 2141 2142 /* 2143 * pcn_mii_statchg: [mii interface function] 2144 * 2145 * Callback from MII layer when media changes. 2146 */ 2147 void 2148 pcn_mii_statchg(struct device *self) 2149 { 2150 struct pcn_softc *sc = (void *) self; 2151 2152 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2153 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2154 else 2155 pcn_bcr_write(sc, LE_BCR0, 0); 2156 } 2157