1 /* $NetBSD: if_pcn.c,v 1.17 2002/10/23 01:50:12 perry Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.17 2002/10/23 01:50:12 perry Exp $"); 69 70 #include "bpfilter.h" 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/callout.h> 75 #include <sys/mbuf.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/socket.h> 79 #include <sys/ioctl.h> 80 #include <sys/errno.h> 81 #include <sys/device.h> 82 #include <sys/queue.h> 83 84 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 85 86 #include <net/if.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 #include <net/if_ether.h> 90 91 #if NBPFILTER > 0 92 #include <net/bpf.h> 93 #endif 94 95 #include <machine/bus.h> 96 #include <machine/intr.h> 97 #include <machine/endian.h> 98 99 #include <dev/mii/mii.h> 100 #include <dev/mii/miivar.h> 101 102 #include <dev/ic/am79900reg.h> 103 #include <dev/ic/lancereg.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 109 #include <dev/pci/if_pcnreg.h> 110 111 /* 112 * Transmit descriptor list size. This is arbitrary, but allocate 113 * enough descriptors for 128 pending transmissions, and 4 segments 114 * per packet. This MUST work out to a power of 2. 115 * 116 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 117 * 118 * So we play a little trick here. We give each packet up to 16 119 * DMA segments, but only allocate the max of 512 descriptors. The 120 * transmit logic can deal with this, we just are hoping to sneak by. 121 */ 122 #define PCN_NTXSEGS 16 123 124 #define PCN_TXQUEUELEN 128 125 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 126 #define PCN_NTXDESC 512 127 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 128 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 129 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 130 131 /* Tx interrupt every N + 1 packets. */ 132 #define PCN_TXINTR_MASK 7 133 134 /* 135 * Receive descriptor list size. We have one Rx buffer per incoming 136 * packet, so this logic is a little simpler. 137 */ 138 #define PCN_NRXDESC 128 139 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 140 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 141 142 /* 143 * Control structures are DMA'd to the PCnet chip. We allocate them in 144 * a single clump that maps to a single DMA segment to make several things 145 * easier. 146 */ 147 struct pcn_control_data { 148 /* The transmit descriptors. */ 149 struct letmd pcd_txdescs[PCN_NTXDESC]; 150 151 /* The receive descriptors. */ 152 struct lermd pcd_rxdescs[PCN_NRXDESC]; 153 154 /* The init block. */ 155 struct leinit pcd_initblock; 156 }; 157 158 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 159 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 160 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 161 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 162 163 /* 164 * Software state for transmit jobs. 165 */ 166 struct pcn_txsoft { 167 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 168 bus_dmamap_t txs_dmamap; /* our DMA map */ 169 int txs_firstdesc; /* first descriptor in packet */ 170 int txs_lastdesc; /* last descriptor in packet */ 171 }; 172 173 /* 174 * Software state for receive jobs. 175 */ 176 struct pcn_rxsoft { 177 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 178 bus_dmamap_t rxs_dmamap; /* our DMA map */ 179 }; 180 181 /* 182 * Description of Rx FIFO watermarks for various revisions. 183 */ 184 const char *pcn_79c970_rcvfw[] = { 185 "16 bytes", 186 "64 bytes", 187 "128 bytes", 188 NULL, 189 }; 190 191 const char *pcn_79c971_rcvfw[] = { 192 "16 bytes", 193 "64 bytes", 194 "112 bytes", 195 NULL, 196 }; 197 198 /* 199 * Description of Tx start points for various revisions. 200 */ 201 const char *pcn_79c970_xmtsp[] = { 202 "8 bytes", 203 "64 bytes", 204 "128 bytes", 205 "248 bytes", 206 }; 207 208 const char *pcn_79c971_xmtsp[] = { 209 "20 bytes", 210 "64 bytes", 211 "128 bytes", 212 "248 bytes", 213 }; 214 215 const char *pcn_79c971_xmtsp_sram[] = { 216 "44 bytes", 217 "64 bytes", 218 "128 bytes", 219 "store-and-forward", 220 }; 221 222 /* 223 * Description of Tx FIFO watermarks for various revisions. 224 */ 225 const char *pcn_79c970_xmtfw[] = { 226 "16 bytes", 227 "64 bytes", 228 "128 bytes", 229 NULL, 230 }; 231 232 const char *pcn_79c971_xmtfw[] = { 233 "16 bytes", 234 "64 bytes", 235 "108 bytes", 236 NULL, 237 }; 238 239 /* 240 * Software state per device. 241 */ 242 struct pcn_softc { 243 struct device sc_dev; /* generic device information */ 244 bus_space_tag_t sc_st; /* bus space tag */ 245 bus_space_handle_t sc_sh; /* bus space handle */ 246 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 247 struct ethercom sc_ethercom; /* Ethernet common data */ 248 void *sc_sdhook; /* shutdown hook */ 249 250 /* Points to our media routines, etc. */ 251 const struct pcn_variant *sc_variant; 252 253 void *sc_ih; /* interrupt cookie */ 254 255 struct mii_data sc_mii; /* MII/media information */ 256 257 struct callout sc_tick_ch; /* tick callout */ 258 259 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 260 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 261 262 /* Software state for transmit and receive descriptors. */ 263 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 264 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 265 266 /* Control data structures */ 267 struct pcn_control_data *sc_control_data; 268 #define sc_txdescs sc_control_data->pcd_txdescs 269 #define sc_rxdescs sc_control_data->pcd_rxdescs 270 #define sc_initblock sc_control_data->pcd_initblock 271 272 #ifdef PCN_EVENT_COUNTERS 273 /* Event counters. */ 274 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 275 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 276 struct evcnt sc_ev_txintr; /* Tx interrupts */ 277 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 278 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 279 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 280 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 281 282 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 283 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 284 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 285 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 286 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 287 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 288 struct evcnt sc_ev_txcopy; /* Tx copies required */ 289 #endif /* PCN_EVENT_COUNTERS */ 290 291 const char **sc_rcvfw_desc; /* Rx FIFO watermark info */ 292 int sc_rcvfw; 293 294 const char **sc_xmtsp_desc; /* Tx start point info */ 295 int sc_xmtsp; 296 297 const char **sc_xmtfw_desc; /* Tx FIFO watermark info */ 298 int sc_xmtfw; 299 300 int sc_flags; /* misc. flags; see below */ 301 int sc_swstyle; /* the software style in use */ 302 303 int sc_txfree; /* number of free Tx descriptors */ 304 int sc_txnext; /* next ready Tx descriptor */ 305 306 int sc_txsfree; /* number of free Tx jobs */ 307 int sc_txsnext; /* next free Tx job */ 308 int sc_txsdirty; /* dirty Tx jobs */ 309 310 int sc_rxptr; /* next ready Rx descriptor/job */ 311 312 uint32_t sc_csr5; /* prototype CSR5 register */ 313 uint32_t sc_mode; /* prototype MODE register */ 314 int sc_phyaddr; /* PHY address */ 315 }; 316 317 /* sc_flags */ 318 #define PCN_F_HAS_MII 0x0001 /* has MII */ 319 320 #ifdef PCN_EVENT_COUNTERS 321 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 322 #else 323 #define PCN_EVCNT_INCR(ev) /* nothing */ 324 #endif 325 326 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 327 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 328 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 329 330 #define PCN_CDTXSYNC(sc, x, n, ops) \ 331 do { \ 332 int __x, __n; \ 333 \ 334 __x = (x); \ 335 __n = (n); \ 336 \ 337 /* If it will wrap around, sync to the end of the ring. */ \ 338 if ((__x + __n) > PCN_NTXDESC) { \ 339 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 340 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 341 (PCN_NTXDESC - __x), (ops)); \ 342 __n -= (PCN_NTXDESC - __x); \ 343 __x = 0; \ 344 } \ 345 \ 346 /* Now sync whatever is left. */ \ 347 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 348 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 349 } while (/*CONSTCOND*/0) 350 351 #define PCN_CDRXSYNC(sc, x, ops) \ 352 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 353 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 354 355 #define PCN_CDINITSYNC(sc, ops) \ 356 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 357 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 358 359 #define PCN_INIT_RXDESC(sc, x) \ 360 do { \ 361 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 362 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 363 struct mbuf *__m = __rxs->rxs_mbuf; \ 364 \ 365 /* \ 366 * Note: We scoot the packet forward 2 bytes in the buffer \ 367 * so that the payload after the Ethernet header is aligned \ 368 * to a 4-byte boundary. \ 369 */ \ 370 __m->m_data = __m->m_ext.ext_buf + 2; \ 371 \ 372 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 373 __rmd->rmd2 = \ 374 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 375 __rmd->rmd0 = 0; \ 376 } else { \ 377 __rmd->rmd2 = 0; \ 378 __rmd->rmd0 = \ 379 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 380 } \ 381 __rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| \ 382 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 383 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\ 384 } while(/*CONSTCOND*/0) 385 386 void pcn_start(struct ifnet *); 387 void pcn_watchdog(struct ifnet *); 388 int pcn_ioctl(struct ifnet *, u_long, caddr_t); 389 int pcn_init(struct ifnet *); 390 void pcn_stop(struct ifnet *, int); 391 392 void pcn_shutdown(void *); 393 394 void pcn_reset(struct pcn_softc *); 395 void pcn_rxdrain(struct pcn_softc *); 396 int pcn_add_rxbuf(struct pcn_softc *, int); 397 void pcn_tick(void *); 398 399 void pcn_spnd(struct pcn_softc *); 400 401 void pcn_set_filter(struct pcn_softc *); 402 403 int pcn_intr(void *); 404 void pcn_txintr(struct pcn_softc *); 405 int pcn_rxintr(struct pcn_softc *); 406 407 int pcn_mii_readreg(struct device *, int, int); 408 void pcn_mii_writereg(struct device *, int, int, int); 409 void pcn_mii_statchg(struct device *); 410 411 void pcn_79c970_mediainit(struct pcn_softc *); 412 int pcn_79c970_mediachange(struct ifnet *); 413 void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 414 415 void pcn_79c971_mediainit(struct pcn_softc *); 416 int pcn_79c971_mediachange(struct ifnet *); 417 void pcn_79c971_mediastatus(struct ifnet *, struct ifmediareq *); 418 419 /* 420 * Description of a PCnet-PCI variant. Used to select media access 421 * method, mostly, and to print a nice description of the chip. 422 */ 423 const struct pcn_variant { 424 const char *pcv_desc; 425 void (*pcv_mediainit)(struct pcn_softc *); 426 uint16_t pcv_chipid; 427 } pcn_variants[] = { 428 { "Am79c970 PCnet-PCI", 429 pcn_79c970_mediainit, 430 PARTID_Am79c970 }, 431 432 { "Am79c970A PCnet-PCI II", 433 pcn_79c970_mediainit, 434 PARTID_Am79c970A }, 435 436 { "Am79c971 PCnet-FAST", 437 pcn_79c971_mediainit, 438 PARTID_Am79c971 }, 439 440 { "Am79c972 PCnet-FAST+", 441 pcn_79c971_mediainit, 442 PARTID_Am79c972 }, 443 444 { "Am79c973 PCnet-FAST III", 445 pcn_79c971_mediainit, 446 PARTID_Am79c973 }, 447 448 { "Am79c975 PCnet-FAST III", 449 pcn_79c971_mediainit, 450 PARTID_Am79c975 }, 451 452 { "Unknown PCnet-PCI variant", 453 pcn_79c971_mediainit, 454 0 }, 455 }; 456 457 int pcn_copy_small = 0; 458 459 int pcn_match(struct device *, struct cfdata *, void *); 460 void pcn_attach(struct device *, struct device *, void *); 461 462 CFATTACH_DECL(pcn, sizeof(struct pcn_softc), 463 pcn_match, pcn_attach, NULL, NULL); 464 465 /* 466 * Routines to read and write the PCnet-PCI CSR/BCR space. 467 */ 468 469 static __inline uint32_t 470 pcn_csr_read(struct pcn_softc *sc, int reg) 471 { 472 473 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 474 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP)); 475 } 476 477 static __inline void 478 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 479 { 480 481 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 482 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 483 } 484 485 static __inline uint32_t 486 pcn_bcr_read(struct pcn_softc *sc, int reg) 487 { 488 489 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 490 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP)); 491 } 492 493 static __inline void 494 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 495 { 496 497 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 498 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 499 } 500 501 static const struct pcn_variant * 502 pcn_lookup_variant(uint16_t chipid) 503 { 504 const struct pcn_variant *pcv; 505 506 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 507 if (chipid == pcv->pcv_chipid) 508 return (pcv); 509 } 510 511 /* 512 * This covers unknown chips, which we simply treat like 513 * a generic PCnet-FAST. 514 */ 515 return (pcv); 516 } 517 518 int 519 pcn_match(struct device *parent, struct cfdata *cf, void *aux) 520 { 521 struct pci_attach_args *pa = aux; 522 523 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 524 return (0); 525 526 switch (PCI_PRODUCT(pa->pa_id)) { 527 case PCI_PRODUCT_AMD_PCNET_PCI: 528 /* Beat if_le_pci.c */ 529 return (10); 530 } 531 532 return (0); 533 } 534 535 void 536 pcn_attach(struct device *parent, struct device *self, void *aux) 537 { 538 struct pcn_softc *sc = (struct pcn_softc *) self; 539 struct pci_attach_args *pa = aux; 540 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 541 pci_chipset_tag_t pc = pa->pa_pc; 542 pci_intr_handle_t ih; 543 const char *intrstr = NULL; 544 bus_space_tag_t iot, memt; 545 bus_space_handle_t ioh, memh; 546 bus_dma_segment_t seg; 547 int ioh_valid, memh_valid; 548 int i, rseg, error; 549 pcireg_t pmode; 550 uint32_t chipid, reg; 551 uint8_t enaddr[ETHER_ADDR_LEN]; 552 int pmreg; 553 554 callout_init(&sc->sc_tick_ch); 555 556 printf(": AMD PCnet-PCI Ethernet\n"); 557 558 /* 559 * Map the device. 560 */ 561 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 562 &iot, &ioh, NULL, NULL) == 0); 563 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 564 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 565 &memt, &memh, NULL, NULL) == 0); 566 567 if (memh_valid) { 568 sc->sc_st = memt; 569 sc->sc_sh = memh; 570 } else if (ioh_valid) { 571 sc->sc_st = iot; 572 sc->sc_sh = ioh; 573 } else { 574 printf("%s: unable to map device registers\n", 575 sc->sc_dev.dv_xname); 576 return; 577 } 578 579 sc->sc_dmat = pa->pa_dmat; 580 581 /* Make sure bus mastering is enabled. */ 582 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 583 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 584 PCI_COMMAND_MASTER_ENABLE); 585 586 /* Get it out of power save mode, if needed. */ 587 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 588 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 589 if (pmode == 3) { 590 /* 591 * The card has lost all configuration data in 592 * this state, so punt. 593 */ 594 printf("%s: unable to wake from power state D3\n", 595 sc->sc_dev.dv_xname); 596 return; 597 } 598 if (pmode != 0) { 599 printf("%s: waking up from power date D%d\n", 600 sc->sc_dev.dv_xname, pmode); 601 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 602 } 603 } 604 605 /* 606 * Reset the chip to a known state. This also puts the 607 * chip into 32-bit mode. 608 */ 609 pcn_reset(sc); 610 611 /* 612 * Read the Ethernet address from the EEPROM. 613 */ 614 for (i = 0; i < ETHER_ADDR_LEN; i++) 615 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 616 PCN32_APROM + i); 617 618 /* 619 * Now that the device is mapped, attempt to figure out what 620 * kind of chip we have. Note that IDL has all 32 bits of 621 * the chip ID when we're in 32-bit mode. 622 */ 623 chipid = pcn_csr_read(sc, LE_CSR88); 624 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 625 626 printf("%s: %s rev %d, Ethernet address %s\n", 627 sc->sc_dev.dv_xname, sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 628 ether_sprintf(enaddr)); 629 630 /* 631 * Map and establish our interrupt. 632 */ 633 if (pci_intr_map(pa, &ih)) { 634 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 635 return; 636 } 637 intrstr = pci_intr_string(pc, ih); 638 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, pcn_intr, sc); 639 if (sc->sc_ih == NULL) { 640 printf("%s: unable to establish interrupt", 641 sc->sc_dev.dv_xname); 642 if (intrstr != NULL) 643 printf(" at %s", intrstr); 644 printf("\n"); 645 return; 646 } 647 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 648 649 /* 650 * Allocate the control data structures, and create and load the 651 * DMA map for it. 652 */ 653 if ((error = bus_dmamem_alloc(sc->sc_dmat, 654 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 655 0)) != 0) { 656 printf("%s: unable to allocate control data, error = %d\n", 657 sc->sc_dev.dv_xname, error); 658 goto fail_0; 659 } 660 661 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 662 sizeof(struct pcn_control_data), (caddr_t *)&sc->sc_control_data, 663 BUS_DMA_COHERENT)) != 0) { 664 printf("%s: unable to map control data, error = %d\n", 665 sc->sc_dev.dv_xname, error); 666 goto fail_1; 667 } 668 669 if ((error = bus_dmamap_create(sc->sc_dmat, 670 sizeof(struct pcn_control_data), 1, 671 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 672 printf("%s: unable to create control data DMA map, " 673 "error = %d\n", sc->sc_dev.dv_xname, error); 674 goto fail_2; 675 } 676 677 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 678 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 679 0)) != 0) { 680 printf("%s: unable to load control data DMA map, error = %d\n", 681 sc->sc_dev.dv_xname, error); 682 goto fail_3; 683 } 684 685 /* Create the transmit buffer DMA maps. */ 686 for (i = 0; i < PCN_TXQUEUELEN; i++) { 687 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 688 PCN_NTXSEGS, MCLBYTES, 0, 0, 689 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 690 printf("%s: unable to create tx DMA map %d, " 691 "error = %d\n", sc->sc_dev.dv_xname, i, error); 692 goto fail_4; 693 } 694 } 695 696 /* Create the receive buffer DMA maps. */ 697 for (i = 0; i < PCN_NRXDESC; i++) { 698 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 699 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 700 printf("%s: unable to create rx DMA map %d, " 701 "error = %d\n", sc->sc_dev.dv_xname, i, error); 702 goto fail_5; 703 } 704 sc->sc_rxsoft[i].rxs_mbuf = NULL; 705 } 706 707 /* Initialize our media structures. */ 708 (*sc->sc_variant->pcv_mediainit)(sc); 709 710 /* 711 * Initialize FIFO watermark info. 712 */ 713 switch (sc->sc_variant->pcv_chipid) { 714 case PARTID_Am79c970: 715 case PARTID_Am79c970A: 716 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 717 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 718 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 719 break; 720 721 default: 722 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 723 /* 724 * Read BCR25 to determine how much SRAM is 725 * on the board. If > 0, then we the chip 726 * uses different Start Point thresholds. 727 * 728 * Note BCR25 and BCR26 are loaded from the 729 * EEPROM on RST, and unaffected by S_RESET, 730 * so we don't really have to worry about 731 * them except for this. 732 */ 733 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 734 if (reg != 0) 735 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 736 else 737 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 738 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 739 break; 740 } 741 742 /* 743 * Set up defaults -- see the tables above for what these 744 * values mean. 745 * 746 * XXX How should we tune RCVFW and XMTFW? 747 */ 748 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 749 sc->sc_xmtsp = 1; 750 sc->sc_xmtfw = 0; 751 752 ifp = &sc->sc_ethercom.ec_if; 753 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 754 ifp->if_softc = sc; 755 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 756 ifp->if_ioctl = pcn_ioctl; 757 ifp->if_start = pcn_start; 758 ifp->if_watchdog = pcn_watchdog; 759 ifp->if_init = pcn_init; 760 ifp->if_stop = pcn_stop; 761 IFQ_SET_READY(&ifp->if_snd); 762 763 /* Attach the interface. */ 764 if_attach(ifp); 765 ether_ifattach(ifp, enaddr); 766 767 #ifdef PCN_EVENT_COUNTERS 768 /* Attach event counters. */ 769 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 770 NULL, sc->sc_dev.dv_xname, "txsstall"); 771 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 772 NULL, sc->sc_dev.dv_xname, "txdstall"); 773 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 774 NULL, sc->sc_dev.dv_xname, "txintr"); 775 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 776 NULL, sc->sc_dev.dv_xname, "rxintr"); 777 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 778 NULL, sc->sc_dev.dv_xname, "babl"); 779 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 780 NULL, sc->sc_dev.dv_xname, "miss"); 781 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 782 NULL, sc->sc_dev.dv_xname, "merr"); 783 784 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 785 NULL, sc->sc_dev.dv_xname, "txseg1"); 786 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 787 NULL, sc->sc_dev.dv_xname, "txseg2"); 788 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 789 NULL, sc->sc_dev.dv_xname, "txseg3"); 790 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 791 NULL, sc->sc_dev.dv_xname, "txseg4"); 792 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 793 NULL, sc->sc_dev.dv_xname, "txseg5"); 794 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 795 NULL, sc->sc_dev.dv_xname, "txsegmore"); 796 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 797 NULL, sc->sc_dev.dv_xname, "txcopy"); 798 #endif /* PCN_EVENT_COUNTERS */ 799 800 /* Make sure the interface is shutdown during reboot. */ 801 sc->sc_sdhook = shutdownhook_establish(pcn_shutdown, sc); 802 if (sc->sc_sdhook == NULL) 803 printf("%s: WARNING: unable to establish shutdown hook\n", 804 sc->sc_dev.dv_xname); 805 return; 806 807 /* 808 * Free any resources we've allocated during the failed attach 809 * attempt. Do this in reverse order and fall through. 810 */ 811 fail_5: 812 for (i = 0; i < PCN_NRXDESC; i++) { 813 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 814 bus_dmamap_destroy(sc->sc_dmat, 815 sc->sc_rxsoft[i].rxs_dmamap); 816 } 817 fail_4: 818 for (i = 0; i < PCN_TXQUEUELEN; i++) { 819 if (sc->sc_txsoft[i].txs_dmamap != NULL) 820 bus_dmamap_destroy(sc->sc_dmat, 821 sc->sc_txsoft[i].txs_dmamap); 822 } 823 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 824 fail_3: 825 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 826 fail_2: 827 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 828 sizeof(struct pcn_control_data)); 829 fail_1: 830 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 831 fail_0: 832 return; 833 } 834 835 /* 836 * pcn_shutdown: 837 * 838 * Make sure the interface is stopped at reboot time. 839 */ 840 void 841 pcn_shutdown(void *arg) 842 { 843 struct pcn_softc *sc = arg; 844 845 pcn_stop(&sc->sc_ethercom.ec_if, 1); 846 } 847 848 /* 849 * pcn_start: [ifnet interface function] 850 * 851 * Start packet transmission on the interface. 852 */ 853 void 854 pcn_start(struct ifnet *ifp) 855 { 856 struct pcn_softc *sc = ifp->if_softc; 857 struct mbuf *m0, *m; 858 struct pcn_txsoft *txs; 859 bus_dmamap_t dmamap; 860 int error, nexttx, lasttx, ofree, seg; 861 862 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 863 return; 864 865 /* 866 * Remember the previous number of free descriptors and 867 * the first descriptor we'll use. 868 */ 869 ofree = sc->sc_txfree; 870 871 /* 872 * Loop through the send queue, setting up transmit descriptors 873 * until we drain the queue, or use up all available transmit 874 * descriptors. 875 */ 876 for (;;) { 877 /* Grab a packet off the queue. */ 878 IFQ_POLL(&ifp->if_snd, m0); 879 if (m0 == NULL) 880 break; 881 m = NULL; 882 883 /* Get a work queue entry. */ 884 if (sc->sc_txsfree == 0) { 885 PCN_EVCNT_INCR(&sc->sc_ev_txsstall); 886 break; 887 } 888 889 txs = &sc->sc_txsoft[sc->sc_txsnext]; 890 dmamap = txs->txs_dmamap; 891 892 /* 893 * Load the DMA map. If this fails, the packet either 894 * didn't fit in the alloted number of segments, or we 895 * were short on resources. In this case, we'll copy 896 * and try again. 897 */ 898 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 899 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 900 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 901 MGETHDR(m, M_DONTWAIT, MT_DATA); 902 if (m == NULL) { 903 printf("%s: unable to allocate Tx mbuf\n", 904 sc->sc_dev.dv_xname); 905 break; 906 } 907 if (m0->m_pkthdr.len > MHLEN) { 908 MCLGET(m, M_DONTWAIT); 909 if ((m->m_flags & M_EXT) == 0) { 910 printf("%s: unable to allocate Tx " 911 "cluster\n", sc->sc_dev.dv_xname); 912 m_freem(m); 913 break; 914 } 915 } 916 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 917 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 918 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 919 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 920 if (error) { 921 printf("%s: unable to load Tx buffer, " 922 "error = %d\n", sc->sc_dev.dv_xname, error); 923 break; 924 } 925 } 926 927 /* 928 * Ensure we have enough descriptors free to describe 929 * the packet. Note, we always reserve one descriptor 930 * at the end of the ring as a termination point, to 931 * prevent wrap-around. 932 */ 933 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 934 /* 935 * Not enough free descriptors to transmit this 936 * packet. We haven't committed anything yet, 937 * so just unload the DMA map, put the packet 938 * back on the queue, and punt. Notify the upper 939 * layer that there are not more slots left. 940 * 941 * XXX We could allocate an mbuf and copy, but 942 * XXX is it worth it? 943 */ 944 ifp->if_flags |= IFF_OACTIVE; 945 bus_dmamap_unload(sc->sc_dmat, dmamap); 946 if (m != NULL) 947 m_freem(m); 948 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 949 break; 950 } 951 952 IFQ_DEQUEUE(&ifp->if_snd, m0); 953 if (m != NULL) { 954 m_freem(m0); 955 m0 = m; 956 } 957 958 /* 959 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 960 */ 961 962 /* Sync the DMA map. */ 963 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 964 BUS_DMASYNC_PREWRITE); 965 966 #ifdef PCN_EVENT_COUNTERS 967 switch (dmamap->dm_nsegs) { 968 case 1: 969 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 970 break; 971 case 2: 972 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 973 break; 974 case 3: 975 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 976 break; 977 case 4: 978 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 979 break; 980 case 5: 981 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 982 break; 983 default: 984 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 985 break; 986 } 987 #endif /* PCN_EVENT_COUNTERS */ 988 989 /* 990 * Initialize the transmit descriptors. 991 */ 992 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 993 for (nexttx = sc->sc_txnext, seg = 0; 994 seg < dmamap->dm_nsegs; 995 seg++, nexttx = PCN_NEXTTX(nexttx)) { 996 /* 997 * If this is the first descriptor we're 998 * enqueueing, don't set the OWN bit just 999 * yet. That could cause a race condition. 1000 * We'll do it below. 1001 */ 1002 sc->sc_txdescs[nexttx].tmd0 = 0; 1003 sc->sc_txdescs[nexttx].tmd2 = 1004 htole32(dmamap->dm_segs[seg].ds_addr); 1005 sc->sc_txdescs[nexttx].tmd1 = 1006 htole32(LE_T1_ONES | 1007 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1008 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1009 LE_T1_BCNT_MASK)); 1010 lasttx = nexttx; 1011 } 1012 } else { 1013 for (nexttx = sc->sc_txnext, seg = 0; 1014 seg < dmamap->dm_nsegs; 1015 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1016 /* 1017 * If this is the first descriptor we're 1018 * enqueueing, don't set the OWN bit just 1019 * yet. That could cause a race condition. 1020 * We'll do it below. 1021 */ 1022 sc->sc_txdescs[nexttx].tmd0 = 1023 htole32(dmamap->dm_segs[seg].ds_addr); 1024 sc->sc_txdescs[nexttx].tmd2 = 0; 1025 sc->sc_txdescs[nexttx].tmd1 = 1026 htole32(LE_T1_ONES | 1027 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1028 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1029 LE_T1_BCNT_MASK)); 1030 lasttx = nexttx; 1031 } 1032 } 1033 1034 /* Interrupt on the packet, if appropriate. */ 1035 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1036 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1037 1038 /* Set `start of packet' and `end of packet' appropriately. */ 1039 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1040 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1041 htole32(LE_T1_OWN|LE_T1_STP); 1042 1043 /* Sync the descriptors we're using. */ 1044 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1045 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1046 1047 /* Kick the transmitter. */ 1048 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); 1049 1050 /* 1051 * Store a pointer to the packet so we can free it later, 1052 * and remember what txdirty will be once the packet is 1053 * done. 1054 */ 1055 txs->txs_mbuf = m0; 1056 txs->txs_firstdesc = sc->sc_txnext; 1057 txs->txs_lastdesc = lasttx; 1058 1059 /* Advance the tx pointer. */ 1060 sc->sc_txfree -= dmamap->dm_nsegs; 1061 sc->sc_txnext = nexttx; 1062 1063 sc->sc_txsfree--; 1064 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1065 1066 #if NBPFILTER > 0 1067 /* Pass the packet to any BPF listeners. */ 1068 if (ifp->if_bpf) 1069 bpf_mtap(ifp->if_bpf, m0); 1070 #endif /* NBPFILTER > 0 */ 1071 } 1072 1073 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1074 /* No more slots left; notify upper layer. */ 1075 ifp->if_flags |= IFF_OACTIVE; 1076 } 1077 1078 if (sc->sc_txfree != ofree) { 1079 /* Set a watchdog timer in case the chip flakes out. */ 1080 ifp->if_timer = 5; 1081 } 1082 } 1083 1084 /* 1085 * pcn_watchdog: [ifnet interface function] 1086 * 1087 * Watchdog timer handler. 1088 */ 1089 void 1090 pcn_watchdog(struct ifnet *ifp) 1091 { 1092 struct pcn_softc *sc = ifp->if_softc; 1093 1094 /* 1095 * Since we're not interrupting every packet, sweep 1096 * up before we report an error. 1097 */ 1098 pcn_txintr(sc); 1099 1100 if (sc->sc_txfree != PCN_NTXDESC) { 1101 printf("%s: device timeout (txfree %d txsfree %d)\n", 1102 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree); 1103 ifp->if_oerrors++; 1104 1105 /* Reset the interface. */ 1106 (void) pcn_init(ifp); 1107 } 1108 1109 /* Try to get more packets going. */ 1110 pcn_start(ifp); 1111 } 1112 1113 /* 1114 * pcn_ioctl: [ifnet interface function] 1115 * 1116 * Handle control requests from the operator. 1117 */ 1118 int 1119 pcn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1120 { 1121 struct pcn_softc *sc = ifp->if_softc; 1122 struct ifreq *ifr = (struct ifreq *) data; 1123 int s, error; 1124 1125 s = splnet(); 1126 1127 switch (cmd) { 1128 case SIOCSIFMEDIA: 1129 case SIOCGIFMEDIA: 1130 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1131 break; 1132 1133 default: 1134 error = ether_ioctl(ifp, cmd, data); 1135 if (error == ENETRESET) { 1136 /* 1137 * Multicast list has changed; set the hardware filter 1138 * accordingly. 1139 */ 1140 error = pcn_init(ifp); 1141 } 1142 break; 1143 } 1144 1145 /* Try to get more packets going. */ 1146 pcn_start(ifp); 1147 1148 splx(s); 1149 return (error); 1150 } 1151 1152 /* 1153 * pcn_intr: 1154 * 1155 * Interrupt service routine. 1156 */ 1157 int 1158 pcn_intr(void *arg) 1159 { 1160 struct pcn_softc *sc = arg; 1161 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1162 uint32_t csr0; 1163 int wantinit, handled = 0; 1164 1165 for (wantinit = 0; wantinit == 0;) { 1166 csr0 = pcn_csr_read(sc, LE_CSR0); 1167 if ((csr0 & LE_C0_INTR) == 0) 1168 break; 1169 1170 /* ACK the bits and re-enable interrupts. */ 1171 pcn_csr_write(sc, LE_CSR0, csr0 & 1172 (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT| 1173 LE_C0_TINT|LE_C0_IDON)); 1174 1175 handled = 1; 1176 1177 if (csr0 & LE_C0_RINT) { 1178 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1179 wantinit = pcn_rxintr(sc); 1180 } 1181 1182 if (csr0 & LE_C0_TINT) { 1183 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1184 pcn_txintr(sc); 1185 } 1186 1187 if (csr0 & LE_C0_ERR) { 1188 if (csr0 & LE_C0_BABL) { 1189 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1190 ifp->if_oerrors++; 1191 } 1192 if (csr0 & LE_C0_MISS) { 1193 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1194 ifp->if_ierrors++; 1195 } 1196 if (csr0 & LE_C0_MERR) { 1197 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1198 printf("%s: memory error\n", 1199 sc->sc_dev.dv_xname); 1200 wantinit = 1; 1201 break; 1202 } 1203 } 1204 1205 if ((csr0 & LE_C0_RXON) == 0) { 1206 printf("%s: receiver disabled\n", 1207 sc->sc_dev.dv_xname); 1208 ifp->if_ierrors++; 1209 wantinit = 1; 1210 } 1211 1212 if ((csr0 & LE_C0_TXON) == 0) { 1213 printf("%s: transmitter disabled\n", 1214 sc->sc_dev.dv_xname); 1215 ifp->if_oerrors++; 1216 wantinit = 1; 1217 } 1218 } 1219 1220 if (handled) { 1221 if (wantinit) 1222 pcn_init(ifp); 1223 1224 /* Try to get more packets going. */ 1225 pcn_start(ifp); 1226 } 1227 1228 return (handled); 1229 } 1230 1231 /* 1232 * pcn_spnd: 1233 * 1234 * Suspend the chip. 1235 */ 1236 void 1237 pcn_spnd(struct pcn_softc *sc) 1238 { 1239 int i; 1240 1241 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1242 1243 for (i = 0; i < 10000; i++) { 1244 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1245 return; 1246 delay(5); 1247 } 1248 1249 printf("%s: WARNING: chip failed to enter suspended state\n", 1250 sc->sc_dev.dv_xname); 1251 } 1252 1253 /* 1254 * pcn_txintr: 1255 * 1256 * Helper; handle transmit interrupts. 1257 */ 1258 void 1259 pcn_txintr(struct pcn_softc *sc) 1260 { 1261 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1262 struct pcn_txsoft *txs; 1263 uint32_t tmd1, tmd2, tmd; 1264 int i, j; 1265 1266 ifp->if_flags &= ~IFF_OACTIVE; 1267 1268 /* 1269 * Go through our Tx list and free mbufs for those 1270 * frames which have been transmitted. 1271 */ 1272 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1273 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1274 txs = &sc->sc_txsoft[i]; 1275 1276 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1277 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1278 1279 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1280 if (tmd1 & LE_T1_OWN) 1281 break; 1282 1283 /* 1284 * Slightly annoying -- we have to loop through the 1285 * descriptors we've used looking for ERR, since it 1286 * can appear on any descriptor in the chain. 1287 */ 1288 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1289 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1290 if (tmd & LE_T1_ERR) { 1291 ifp->if_oerrors++; 1292 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1293 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1294 else 1295 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1296 if (tmd2 & LE_T2_UFLO) { 1297 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1298 sc->sc_xmtsp++; 1299 printf("%s: transmit " 1300 "underrun; new threshold: " 1301 "%s\n", 1302 sc->sc_dev.dv_xname, 1303 sc->sc_xmtsp_desc[ 1304 sc->sc_xmtsp]); 1305 pcn_spnd(sc); 1306 pcn_csr_write(sc, LE_CSR80, 1307 LE_C80_RCVFW(sc->sc_rcvfw) | 1308 LE_C80_XMTSP(sc->sc_xmtsp) | 1309 LE_C80_XMTFW(sc->sc_xmtfw)); 1310 pcn_csr_write(sc, LE_CSR5, 1311 sc->sc_csr5); 1312 } else { 1313 printf("%s: transmit " 1314 "underrun\n", 1315 sc->sc_dev.dv_xname); 1316 } 1317 } else if (tmd2 & LE_T2_BUFF) { 1318 printf("%s: transmit buffer error\n", 1319 sc->sc_dev.dv_xname); 1320 } 1321 if (tmd2 & LE_T2_LCOL) 1322 ifp->if_collisions++; 1323 if (tmd2 & LE_T2_RTRY) 1324 ifp->if_collisions += 16; 1325 goto next_packet; 1326 } 1327 if (j == txs->txs_lastdesc) 1328 break; 1329 } 1330 if (tmd1 & LE_T1_ONE) 1331 ifp->if_collisions++; 1332 else if (tmd & LE_T1_MORE) { 1333 /* Real number is unknown. */ 1334 ifp->if_collisions += 2; 1335 } 1336 ifp->if_opackets++; 1337 next_packet: 1338 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1339 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1340 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1341 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1342 m_freem(txs->txs_mbuf); 1343 txs->txs_mbuf = NULL; 1344 } 1345 1346 /* Update the dirty transmit buffer pointer. */ 1347 sc->sc_txsdirty = i; 1348 1349 /* 1350 * If there are no more pending transmissions, cancel the watchdog 1351 * timer. 1352 */ 1353 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1354 ifp->if_timer = 0; 1355 } 1356 1357 /* 1358 * pcn_rxintr: 1359 * 1360 * Helper; handle receive interrupts. 1361 */ 1362 int 1363 pcn_rxintr(struct pcn_softc *sc) 1364 { 1365 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1366 struct pcn_rxsoft *rxs; 1367 struct mbuf *m; 1368 uint32_t rmd1; 1369 int i, len; 1370 1371 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1372 rxs = &sc->sc_rxsoft[i]; 1373 1374 PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1375 1376 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1377 1378 if (rmd1 & LE_R1_OWN) 1379 break; 1380 1381 /* 1382 * Check for errors and make sure the packet fit into 1383 * a single buffer. We have structured this block of 1384 * code the way it is in order to compress it into 1385 * one test in the common case (no error). 1386 */ 1387 if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) != 1388 (LE_R1_STP|LE_R1_ENP))) { 1389 /* Make sure the packet is in a single buffer. */ 1390 if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) != 1391 (LE_R1_STP|LE_R1_ENP)) { 1392 printf("%s: packet spilled into next buffer\n", 1393 sc->sc_dev.dv_xname); 1394 return (1); /* pcn_intr() will re-init */ 1395 } 1396 1397 /* 1398 * If the packet had an error, simple recycle the 1399 * buffer. 1400 */ 1401 if (rmd1 & LE_R1_ERR) { 1402 ifp->if_ierrors++; 1403 /* 1404 * If we got an overflow error, chances 1405 * are there will be a CRC error. In 1406 * this case, just print the overflow 1407 * error, and skip the others. 1408 */ 1409 if (rmd1 & LE_R1_OFLO) 1410 printf("%s: overflow error\n", 1411 sc->sc_dev.dv_xname); 1412 else { 1413 #define PRINTIT(x, str) \ 1414 if (rmd1 & (x)) \ 1415 printf("%s: %s\n", \ 1416 sc->sc_dev.dv_xname, str); 1417 PRINTIT(LE_R1_FRAM, "framing error"); 1418 PRINTIT(LE_R1_CRC, "CRC error"); 1419 PRINTIT(LE_R1_BUFF, "buffer error"); 1420 } 1421 #undef PRINTIT 1422 PCN_INIT_RXDESC(sc, i); 1423 continue; 1424 } 1425 } 1426 1427 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1428 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1429 1430 /* 1431 * No errors; receive the packet. 1432 */ 1433 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1434 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1435 else 1436 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1437 1438 /* 1439 * The LANCE family includes the CRC with every packet; 1440 * trim it off here. 1441 */ 1442 len -= ETHER_CRC_LEN; 1443 1444 /* 1445 * If the packet is small enough to fit in a 1446 * single header mbuf, allocate one and copy 1447 * the data into it. This greatly reduces 1448 * memory consumption when we receive lots 1449 * of small packets. 1450 * 1451 * Otherwise, we add a new buffer to the receive 1452 * chain. If this fails, we drop the packet and 1453 * recycle the old buffer. 1454 */ 1455 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1456 MGETHDR(m, M_DONTWAIT, MT_DATA); 1457 if (m == NULL) 1458 goto dropit; 1459 m->m_data += 2; 1460 memcpy(mtod(m, caddr_t), 1461 mtod(rxs->rxs_mbuf, caddr_t), len); 1462 PCN_INIT_RXDESC(sc, i); 1463 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1464 rxs->rxs_dmamap->dm_mapsize, 1465 BUS_DMASYNC_PREREAD); 1466 } else { 1467 m = rxs->rxs_mbuf; 1468 if (pcn_add_rxbuf(sc, i) != 0) { 1469 dropit: 1470 ifp->if_ierrors++; 1471 PCN_INIT_RXDESC(sc, i); 1472 bus_dmamap_sync(sc->sc_dmat, 1473 rxs->rxs_dmamap, 0, 1474 rxs->rxs_dmamap->dm_mapsize, 1475 BUS_DMASYNC_PREREAD); 1476 continue; 1477 } 1478 } 1479 1480 m->m_pkthdr.rcvif = ifp; 1481 m->m_pkthdr.len = m->m_len = len; 1482 1483 #if NBPFILTER > 0 1484 /* Pass this up to any BPF listeners. */ 1485 if (ifp->if_bpf) 1486 bpf_mtap(ifp->if_bpf, m); 1487 #endif /* NBPFILTER > 0 */ 1488 1489 /* Pass it on. */ 1490 (*ifp->if_input)(ifp, m); 1491 ifp->if_ipackets++; 1492 } 1493 1494 /* Update the receive pointer. */ 1495 sc->sc_rxptr = i; 1496 return (0); 1497 } 1498 1499 /* 1500 * pcn_tick: 1501 * 1502 * One second timer, used to tick the MII. 1503 */ 1504 void 1505 pcn_tick(void *arg) 1506 { 1507 struct pcn_softc *sc = arg; 1508 int s; 1509 1510 s = splnet(); 1511 mii_tick(&sc->sc_mii); 1512 splx(s); 1513 1514 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1515 } 1516 1517 /* 1518 * pcn_reset: 1519 * 1520 * Perform a soft reset on the PCnet-PCI. 1521 */ 1522 void 1523 pcn_reset(struct pcn_softc *sc) 1524 { 1525 1526 /* 1527 * The PCnet-PCI chip is reset by reading from the 1528 * RESET register. Note that while the NE2100 LANCE 1529 * boards require a write after the read, the PCnet-PCI 1530 * chips do not require this. 1531 * 1532 * Since we don't know if we're in 16-bit or 32-bit 1533 * mode right now, issue both (it's safe) in the 1534 * hopes that one will succeed. 1535 */ 1536 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1537 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1538 1539 /* Wait 1ms for it to finish. */ 1540 delay(1000); 1541 1542 /* 1543 * Select 32-bit I/O mode by issuing a 32-bit write to the 1544 * RDP. Since the RAP is 0 after a reset, writing a 0 1545 * to RDP is safe (since it simply clears CSR0). 1546 */ 1547 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1548 } 1549 1550 /* 1551 * pcn_init: [ifnet interface function] 1552 * 1553 * Initialize the interface. Must be called at splnet(). 1554 */ 1555 int 1556 pcn_init(struct ifnet *ifp) 1557 { 1558 struct pcn_softc *sc = ifp->if_softc; 1559 struct pcn_rxsoft *rxs; 1560 uint8_t *enaddr = LLADDR(ifp->if_sadl); 1561 int i, error = 0; 1562 uint32_t reg; 1563 1564 /* Cancel any pending I/O. */ 1565 pcn_stop(ifp, 0); 1566 1567 /* Reset the chip to a known state. */ 1568 pcn_reset(sc); 1569 1570 /* 1571 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1572 * else. 1573 * 1574 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1575 * because the structure layout is compatible with ILACC, 1576 * but the burst mode is only available in SSTYLE 3, and 1577 * burst mode should provide some performance enhancement. 1578 */ 1579 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1580 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1581 else 1582 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1583 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1584 1585 /* Initialize the transmit descriptor ring. */ 1586 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1587 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1588 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1589 sc->sc_txfree = PCN_NTXDESC; 1590 sc->sc_txnext = 0; 1591 1592 /* Initialize the transmit job descriptors. */ 1593 for (i = 0; i < PCN_TXQUEUELEN; i++) 1594 sc->sc_txsoft[i].txs_mbuf = NULL; 1595 sc->sc_txsfree = PCN_TXQUEUELEN; 1596 sc->sc_txsnext = 0; 1597 sc->sc_txsdirty = 0; 1598 1599 /* 1600 * Initialize the receive descriptor and receive job 1601 * descriptor rings. 1602 */ 1603 for (i = 0; i < PCN_NRXDESC; i++) { 1604 rxs = &sc->sc_rxsoft[i]; 1605 if (rxs->rxs_mbuf == NULL) { 1606 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1607 printf("%s: unable to allocate or map rx " 1608 "buffer %d, error = %d\n", 1609 sc->sc_dev.dv_xname, i, error); 1610 /* 1611 * XXX Should attempt to run with fewer receive 1612 * XXX buffers instead of just failing. 1613 */ 1614 pcn_rxdrain(sc); 1615 goto out; 1616 } 1617 } else 1618 PCN_INIT_RXDESC(sc, i); 1619 } 1620 sc->sc_rxptr = 0; 1621 1622 /* Initialize MODE for the initialization block. */ 1623 sc->sc_mode = 0; 1624 if (ifp->if_flags & IFF_PROMISC) 1625 sc->sc_mode |= LE_C15_PROM; 1626 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1627 sc->sc_mode |= LE_C15_DRCVBC; 1628 1629 /* 1630 * If we have MII, simply select MII in the MODE register, 1631 * and clear ASEL. Otherwise, let ASEL stand (for now), 1632 * and leave PORTSEL alone (it is ignored with ASEL is set). 1633 */ 1634 if (sc->sc_flags & PCN_F_HAS_MII) { 1635 pcn_bcr_write(sc, LE_BCR2, 1636 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1637 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1638 1639 /* 1640 * Disable MII auto-negotiation. We handle that in 1641 * our own MII layer. 1642 */ 1643 pcn_bcr_write(sc, LE_BCR32, 1644 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1645 } 1646 1647 /* 1648 * Set the Tx and Rx descriptor ring addresses in the init 1649 * block, the TLEN and RLEN other fields of the init block 1650 * MODE register. 1651 */ 1652 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1653 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1654 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1655 ((ffs(PCN_NTXDESC) - 1) << 28) | 1656 ((ffs(PCN_NRXDESC) - 1) << 20)); 1657 1658 /* Set the station address in the init block. */ 1659 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1660 (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24)); 1661 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1662 (enaddr[5] << 8)); 1663 1664 /* Set the multicast filter in the init block. */ 1665 pcn_set_filter(sc); 1666 1667 /* Initialize CSR3. */ 1668 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO); 1669 1670 /* Initialize CSR4. */ 1671 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT| 1672 LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM); 1673 1674 /* Initialize CSR5. */ 1675 sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE; 1676 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1677 1678 /* 1679 * If we have an Am79c971 or greater, initialize CSR7. 1680 * 1681 * XXX Might be nice to use the MII auto-poll interrupt someday. 1682 */ 1683 switch (sc->sc_variant->pcv_chipid) { 1684 case PARTID_Am79c970: 1685 case PARTID_Am79c970A: 1686 /* Not available on these chips. */ 1687 break; 1688 1689 default: 1690 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1691 break; 1692 } 1693 1694 /* 1695 * On the Am79c970A and greater, initialize BCR18 to 1696 * enable burst mode. 1697 * 1698 * Also enable the "no underflow" option on the Am79c971 and 1699 * higher, which prevents the chip from generating transmit 1700 * underflows, yet sill provides decent performance. Note if 1701 * chip is not connected to external SRAM, then we still have 1702 * to handle underflow errors (the NOUFLO bit is ignored in 1703 * that case). 1704 */ 1705 reg = pcn_bcr_read(sc, LE_BCR18); 1706 switch (sc->sc_variant->pcv_chipid) { 1707 case PARTID_Am79c970: 1708 break; 1709 1710 case PARTID_Am79c970A: 1711 reg |= LE_B18_BREADE|LE_B18_BWRITE; 1712 break; 1713 1714 default: 1715 reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO; 1716 break; 1717 } 1718 pcn_bcr_write(sc, LE_BCR18, reg); 1719 1720 /* 1721 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1722 */ 1723 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1724 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1725 1726 /* 1727 * Send the init block to the chip, and wait for it 1728 * to be processed. 1729 */ 1730 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1731 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1732 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1733 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1734 delay(100); 1735 for (i = 0; i < 10000; i++) { 1736 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1737 break; 1738 delay(10); 1739 } 1740 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1741 if (i == 10000) { 1742 printf("%s: timeout processing init block\n", 1743 sc->sc_dev.dv_xname); 1744 error = EIO; 1745 goto out; 1746 } 1747 1748 /* Set the media. */ 1749 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 1750 1751 /* Enable interrupts and external activity (and ACK IDON). */ 1752 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); 1753 1754 if (sc->sc_flags & PCN_F_HAS_MII) { 1755 /* Start the one second MII clock. */ 1756 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1757 } 1758 1759 /* ...all done! */ 1760 ifp->if_flags |= IFF_RUNNING; 1761 ifp->if_flags &= ~IFF_OACTIVE; 1762 1763 out: 1764 if (error) 1765 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1766 return (error); 1767 } 1768 1769 /* 1770 * pcn_rxdrain: 1771 * 1772 * Drain the receive queue. 1773 */ 1774 void 1775 pcn_rxdrain(struct pcn_softc *sc) 1776 { 1777 struct pcn_rxsoft *rxs; 1778 int i; 1779 1780 for (i = 0; i < PCN_NRXDESC; i++) { 1781 rxs = &sc->sc_rxsoft[i]; 1782 if (rxs->rxs_mbuf != NULL) { 1783 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1784 m_freem(rxs->rxs_mbuf); 1785 rxs->rxs_mbuf = NULL; 1786 } 1787 } 1788 } 1789 1790 /* 1791 * pcn_stop: [ifnet interface function] 1792 * 1793 * Stop transmission on the interface. 1794 */ 1795 void 1796 pcn_stop(struct ifnet *ifp, int disable) 1797 { 1798 struct pcn_softc *sc = ifp->if_softc; 1799 struct pcn_txsoft *txs; 1800 int i; 1801 1802 if (sc->sc_flags & PCN_F_HAS_MII) { 1803 /* Stop the one second clock. */ 1804 callout_stop(&sc->sc_tick_ch); 1805 1806 /* Down the MII. */ 1807 mii_down(&sc->sc_mii); 1808 } 1809 1810 /* Stop the chip. */ 1811 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1812 1813 /* Release any queued transmit buffers. */ 1814 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1815 txs = &sc->sc_txsoft[i]; 1816 if (txs->txs_mbuf != NULL) { 1817 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1818 m_freem(txs->txs_mbuf); 1819 txs->txs_mbuf = NULL; 1820 } 1821 } 1822 1823 if (disable) 1824 pcn_rxdrain(sc); 1825 1826 /* Mark the interface as down and cancel the watchdog timer. */ 1827 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1828 ifp->if_timer = 0; 1829 } 1830 1831 /* 1832 * pcn_add_rxbuf: 1833 * 1834 * Add a receive buffer to the indicated descriptor. 1835 */ 1836 int 1837 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1838 { 1839 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1840 struct mbuf *m; 1841 int error; 1842 1843 MGETHDR(m, M_DONTWAIT, MT_DATA); 1844 if (m == NULL) 1845 return (ENOBUFS); 1846 1847 MCLGET(m, M_DONTWAIT); 1848 if ((m->m_flags & M_EXT) == 0) { 1849 m_freem(m); 1850 return (ENOBUFS); 1851 } 1852 1853 if (rxs->rxs_mbuf != NULL) 1854 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1855 1856 rxs->rxs_mbuf = m; 1857 1858 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1859 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1860 BUS_DMA_READ|BUS_DMA_NOWAIT); 1861 if (error) { 1862 printf("%s: can't load rx DMA map %d, error = %d\n", 1863 sc->sc_dev.dv_xname, idx, error); 1864 panic("pcn_add_rxbuf"); 1865 } 1866 1867 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1868 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1869 1870 PCN_INIT_RXDESC(sc, idx); 1871 1872 return (0); 1873 } 1874 1875 /* 1876 * pcn_set_filter: 1877 * 1878 * Set up the receive filter. 1879 */ 1880 void 1881 pcn_set_filter(struct pcn_softc *sc) 1882 { 1883 struct ethercom *ec = &sc->sc_ethercom; 1884 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1885 struct ether_multi *enm; 1886 struct ether_multistep step; 1887 uint32_t crc; 1888 1889 /* 1890 * Set up the multicast address filter by passing all multicast 1891 * addresses through a CRC generator, and then using the high 1892 * order 6 bits as an index into the 64-bit logical address 1893 * filter. The high order bits select the word, while the rest 1894 * of the bits select the bit within the word. 1895 */ 1896 1897 if (ifp->if_flags & IFF_PROMISC) 1898 goto allmulti; 1899 1900 sc->sc_initblock.init_ladrf[0] = 1901 sc->sc_initblock.init_ladrf[1] = 1902 sc->sc_initblock.init_ladrf[2] = 1903 sc->sc_initblock.init_ladrf[3] = 0; 1904 1905 ETHER_FIRST_MULTI(step, ec, enm); 1906 while (enm != NULL) { 1907 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1908 /* 1909 * We must listen to a range of multicast addresses. 1910 * For now, just accept all multicasts, rather than 1911 * trying to set only those filter bits needed to match 1912 * the range. (At this time, the only use of address 1913 * ranges is for IP multicast routing, for which the 1914 * range is big enough to require all bits set.) 1915 */ 1916 goto allmulti; 1917 } 1918 1919 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1920 1921 /* Just want the 6 most significant bits. */ 1922 crc >>= 26; 1923 1924 /* Set the corresponding bit in the filter. */ 1925 sc->sc_initblock.init_ladrf[crc >> 4] |= 1926 htole16(1 << (crc & 0xf)); 1927 1928 ETHER_NEXT_MULTI(step, enm); 1929 } 1930 1931 ifp->if_flags &= ~IFF_ALLMULTI; 1932 return; 1933 1934 allmulti: 1935 ifp->if_flags |= IFF_ALLMULTI; 1936 sc->sc_initblock.init_ladrf[0] = 1937 sc->sc_initblock.init_ladrf[1] = 1938 sc->sc_initblock.init_ladrf[2] = 1939 sc->sc_initblock.init_ladrf[3] = 0xffff; 1940 } 1941 1942 /* 1943 * pcn_79c970_mediainit: 1944 * 1945 * Initialize media for the Am79c970. 1946 */ 1947 void 1948 pcn_79c970_mediainit(struct pcn_softc *sc) 1949 { 1950 const char *sep = ""; 1951 1952 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, pcn_79c970_mediachange, 1953 pcn_79c970_mediastatus); 1954 1955 #define ADD(str, m, d) \ 1956 do { \ 1957 printf("%s%s", sep, str); \ 1958 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(m), (d), NULL); \ 1959 sep = ", "; \ 1960 } while (/*CONSTCOND*/0) 1961 1962 printf("%s: ", sc->sc_dev.dv_xname); 1963 ADD("10base5", IFM_10_5, PORTSEL_AUI); 1964 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1965 ADD("10base5-FDX", IFM_10_5|IFM_FDX, PORTSEL_AUI); 1966 ADD("10baseT", IFM_10_T, PORTSEL_10T); 1967 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1968 ADD("10baseT-FDX", IFM_10_T|IFM_FDX, PORTSEL_10T); 1969 ADD("auto", IFM_AUTO, 0); 1970 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 1971 ADD("auto-FDX", IFM_AUTO|IFM_FDX, 0); 1972 printf("\n"); 1973 1974 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1975 } 1976 1977 /* 1978 * pcn_79c970_mediastatus: [ifmedia interface function] 1979 * 1980 * Get the current interface media status (Am79c970 version). 1981 */ 1982 void 1983 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1984 { 1985 struct pcn_softc *sc = ifp->if_softc; 1986 1987 /* 1988 * The currently selected media is always the active media. 1989 * Note: We have no way to determine what media the AUTO 1990 * process picked. 1991 */ 1992 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 1993 } 1994 1995 /* 1996 * pcn_79c970_mediachange: [ifmedia interface function] 1997 * 1998 * Set hardware to newly-selected media (Am79c970 version). 1999 */ 2000 int 2001 pcn_79c970_mediachange(struct ifnet *ifp) 2002 { 2003 struct pcn_softc *sc = ifp->if_softc; 2004 uint32_t reg; 2005 2006 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2007 /* 2008 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2009 */ 2010 reg = pcn_bcr_read(sc, LE_BCR2); 2011 reg |= LE_B2_ASEL; 2012 pcn_bcr_write(sc, LE_BCR2, reg); 2013 } else { 2014 /* 2015 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2016 */ 2017 reg = pcn_bcr_read(sc, LE_BCR2); 2018 reg &= ~LE_B2_ASEL; 2019 pcn_bcr_write(sc, LE_BCR2, reg); 2020 2021 reg = pcn_csr_read(sc, LE_CSR15); 2022 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2023 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2024 pcn_csr_write(sc, LE_CSR15, reg); 2025 } 2026 2027 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2028 reg = LE_B9_FDEN; 2029 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2030 reg |= LE_B9_AUIFD; 2031 pcn_bcr_write(sc, LE_BCR9, reg); 2032 } else 2033 pcn_bcr_write(sc, LE_BCR9, 0); 2034 2035 return (0); 2036 } 2037 2038 /* 2039 * pcn_79c971_mediainit: 2040 * 2041 * Initialize media for the Am79c971. 2042 */ 2043 void 2044 pcn_79c971_mediainit(struct pcn_softc *sc) 2045 { 2046 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2047 2048 /* We have MII. */ 2049 sc->sc_flags |= PCN_F_HAS_MII; 2050 2051 /* 2052 * The built-in 10BASE-T interface is mapped to the MII 2053 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2054 * word that tells us which PHY to use. Since the 10BASE-T 2055 * interface is always at PHY 31, we make a note of the 2056 * first PHY that responds, and disallow any PHYs after 2057 * it. This is all handled in the MII read routine. 2058 */ 2059 sc->sc_phyaddr = -1; 2060 2061 /* Initialize our media structures and probe the MII. */ 2062 sc->sc_mii.mii_ifp = ifp; 2063 sc->sc_mii.mii_readreg = pcn_mii_readreg; 2064 sc->sc_mii.mii_writereg = pcn_mii_writereg; 2065 sc->sc_mii.mii_statchg = pcn_mii_statchg; 2066 ifmedia_init(&sc->sc_mii.mii_media, 0, pcn_79c971_mediachange, 2067 pcn_79c971_mediastatus); 2068 2069 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2070 MII_OFFSET_ANY, 0); 2071 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2072 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2073 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2074 } else 2075 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2076 } 2077 2078 /* 2079 * pcn_79c971_mediastatus: [ifmedia interface function] 2080 * 2081 * Get the current interface media status (Am79c971 version). 2082 */ 2083 void 2084 pcn_79c971_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2085 { 2086 struct pcn_softc *sc = ifp->if_softc; 2087 2088 mii_pollstat(&sc->sc_mii); 2089 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2090 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2091 } 2092 2093 /* 2094 * pcn_79c971_mediachange: [ifmedia interface function] 2095 * 2096 * Set hardware to newly-selected media (Am79c971 version). 2097 */ 2098 int 2099 pcn_79c971_mediachange(struct ifnet *ifp) 2100 { 2101 struct pcn_softc *sc = ifp->if_softc; 2102 2103 if (ifp->if_flags & IFF_UP) 2104 mii_mediachg(&sc->sc_mii); 2105 return (0); 2106 } 2107 2108 /* 2109 * pcn_mii_readreg: [mii interface function] 2110 * 2111 * Read a PHY register on the MII. 2112 */ 2113 int 2114 pcn_mii_readreg(struct device *self, int phy, int reg) 2115 { 2116 struct pcn_softc *sc = (void *) self; 2117 uint32_t rv; 2118 2119 if (sc->sc_phyaddr != -1 && phy != sc->sc_phyaddr) 2120 return (0); 2121 2122 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2123 rv = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2124 if (rv == 0xffff) 2125 return (0); 2126 2127 if (sc->sc_phyaddr == -1) 2128 sc->sc_phyaddr = phy; 2129 2130 return (rv); 2131 } 2132 2133 /* 2134 * pcn_mii_writereg: [mii interface function] 2135 * 2136 * Write a PHY register on the MII. 2137 */ 2138 void 2139 pcn_mii_writereg(struct device *self, int phy, int reg, int val) 2140 { 2141 struct pcn_softc *sc = (void *) self; 2142 2143 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2144 pcn_bcr_write(sc, LE_BCR34, val); 2145 } 2146 2147 /* 2148 * pcn_mii_statchg: [mii interface function] 2149 * 2150 * Callback from MII layer when media changes. 2151 */ 2152 void 2153 pcn_mii_statchg(struct device *self) 2154 { 2155 struct pcn_softc *sc = (void *) self; 2156 2157 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2158 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2159 else 2160 pcn_bcr_write(sc, LE_BCR9, 0); 2161 } 2162