1 /* $NetBSD: if_sip.c,v 1.53 2002/05/28 20:20:49 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Support the 10-bit interface on the DP83820 (for fiber). 80 * 81 * - Reduce the interrupt load. 82 */ 83 84 #include <sys/cdefs.h> 85 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.53 2002/05/28 20:20:49 tron Exp $"); 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/callout.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/ioctl.h> 97 #include <sys/errno.h> 98 #include <sys/device.h> 99 #include <sys/queue.h> 100 101 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 102 103 #include <net/if.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_ether.h> 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #endif 111 112 #include <machine/bus.h> 113 #include <machine/intr.h> 114 #include <machine/endian.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 #ifdef DP83820 119 #include <dev/mii/mii_bitbang.h> 120 #endif /* DP83820 */ 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 126 #include <dev/pci/if_sipreg.h> 127 128 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 129 #define SIP_DECL(x) __CONCAT(gsip_,x) 130 #else /* SiS900 and DP83815 */ 131 #define SIP_DECL(x) __CONCAT(sip_,x) 132 #endif 133 134 #define SIP_STR(x) __STRING(SIP_DECL(x)) 135 136 /* 137 * Transmit descriptor list size. This is arbitrary, but allocate 138 * enough descriptors for 128 pending transmissions, and 8 segments 139 * per packet. This MUST work out to a power of 2. 140 */ 141 #define SIP_NTXSEGS 16 142 #define SIP_NTXSEGS_ALLOC 8 143 144 #define SIP_TXQUEUELEN 256 145 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 146 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 147 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 148 149 #if defined(DP83020) 150 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 151 #else 152 #define TX_DMAMAP_SIZE MCLBYTES 153 #endif 154 155 /* 156 * Receive descriptor list size. We have one Rx buffer per incoming 157 * packet, so this logic is a little simpler. 158 * 159 * Actually, on the DP83820, we allow the packet to consume more than 160 * one buffer, in order to support jumbo Ethernet frames. In that 161 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 162 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 163 * so we'd better be quick about handling receive interrupts. 164 */ 165 #if defined(DP83820) 166 #define SIP_NRXDESC 256 167 #else 168 #define SIP_NRXDESC 128 169 #endif /* DP83820 */ 170 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 171 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 172 173 /* 174 * Control structures are DMA'd to the SiS900 chip. We allocate them in 175 * a single clump that maps to a single DMA segment to make several things 176 * easier. 177 */ 178 struct sip_control_data { 179 /* 180 * The transmit descriptors. 181 */ 182 struct sip_desc scd_txdescs[SIP_NTXDESC]; 183 184 /* 185 * The receive descriptors. 186 */ 187 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 188 }; 189 190 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 191 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 192 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 193 194 /* 195 * Software state for transmit jobs. 196 */ 197 struct sip_txsoft { 198 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 199 bus_dmamap_t txs_dmamap; /* our DMA map */ 200 int txs_firstdesc; /* first descriptor in packet */ 201 int txs_lastdesc; /* last descriptor in packet */ 202 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 203 }; 204 205 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 206 207 /* 208 * Software state for receive jobs. 209 */ 210 struct sip_rxsoft { 211 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 212 bus_dmamap_t rxs_dmamap; /* our DMA map */ 213 }; 214 215 /* 216 * Software state per device. 217 */ 218 struct sip_softc { 219 struct device sc_dev; /* generic device information */ 220 bus_space_tag_t sc_st; /* bus space tag */ 221 bus_space_handle_t sc_sh; /* bus space handle */ 222 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 223 struct ethercom sc_ethercom; /* ethernet common data */ 224 void *sc_sdhook; /* shutdown hook */ 225 226 const struct sip_product *sc_model; /* which model are we? */ 227 int sc_rev; /* chip revision */ 228 229 void *sc_ih; /* interrupt cookie */ 230 231 struct mii_data sc_mii; /* MII/media information */ 232 233 struct callout sc_tick_ch; /* tick callout */ 234 235 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 236 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 237 238 /* 239 * Software state for transmit and receive descriptors. 240 */ 241 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 242 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 243 244 /* 245 * Control data structures. 246 */ 247 struct sip_control_data *sc_control_data; 248 #define sc_txdescs sc_control_data->scd_txdescs 249 #define sc_rxdescs sc_control_data->scd_rxdescs 250 251 #ifdef SIP_EVENT_COUNTERS 252 /* 253 * Event counters. 254 */ 255 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 256 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 257 struct evcnt sc_ev_txintr; /* Tx interrupts */ 258 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 259 #ifdef DP83820 260 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 261 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 262 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 263 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 264 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 265 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 266 #endif /* DP83820 */ 267 #endif /* SIP_EVENT_COUNTERS */ 268 269 u_int32_t sc_txcfg; /* prototype TXCFG register */ 270 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 271 u_int32_t sc_imr; /* prototype IMR register */ 272 u_int32_t sc_rfcr; /* prototype RFCR register */ 273 274 u_int32_t sc_cfg; /* prototype CFG register */ 275 276 #ifdef DP83820 277 u_int32_t sc_gpior; /* prototype GPIOR register */ 278 #endif /* DP83820 */ 279 280 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 281 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 282 283 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 284 285 int sc_flags; /* misc. flags; see below */ 286 287 int sc_txfree; /* number of free Tx descriptors */ 288 int sc_txnext; /* next ready Tx descriptor */ 289 290 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 291 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 292 293 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 294 #if defined(DP83820) 295 int sc_rxdiscard; 296 int sc_rxlen; 297 struct mbuf *sc_rxhead; 298 struct mbuf *sc_rxtail; 299 struct mbuf **sc_rxtailp; 300 #endif /* DP83820 */ 301 }; 302 303 /* sc_flags */ 304 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 305 306 #ifdef DP83820 307 #define SIP_RXCHAIN_RESET(sc) \ 308 do { \ 309 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 310 *(sc)->sc_rxtailp = NULL; \ 311 (sc)->sc_rxlen = 0; \ 312 } while (/*CONSTCOND*/0) 313 314 #define SIP_RXCHAIN_LINK(sc, m) \ 315 do { \ 316 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 317 (sc)->sc_rxtailp = &(m)->m_next; \ 318 } while (/*CONSTCOND*/0) 319 #endif /* DP83820 */ 320 321 #ifdef SIP_EVENT_COUNTERS 322 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 323 #else 324 #define SIP_EVCNT_INCR(ev) /* nothing */ 325 #endif 326 327 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 328 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 329 330 #define SIP_CDTXSYNC(sc, x, n, ops) \ 331 do { \ 332 int __x, __n; \ 333 \ 334 __x = (x); \ 335 __n = (n); \ 336 \ 337 /* If it will wrap around, sync to the end of the ring. */ \ 338 if ((__x + __n) > SIP_NTXDESC) { \ 339 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 340 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 341 (SIP_NTXDESC - __x), (ops)); \ 342 __n -= (SIP_NTXDESC - __x); \ 343 __x = 0; \ 344 } \ 345 \ 346 /* Now sync whatever is left. */ \ 347 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 348 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 349 } while (0) 350 351 #define SIP_CDRXSYNC(sc, x, ops) \ 352 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 353 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 354 355 #ifdef DP83820 356 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 357 #define SIP_RXBUF_LEN (MCLBYTES - 4) 358 #else 359 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 360 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 361 #endif 362 #define SIP_INIT_RXDESC(sc, x) \ 363 do { \ 364 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 365 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 366 \ 367 __sipd->sipd_link = \ 368 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 369 __sipd->sipd_bufptr = \ 370 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 371 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 372 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 373 SIP_INIT_RXDESC_EXTSTS \ 374 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 375 } while (0) 376 377 #define SIP_CHIP_VERS(sc, v, p, r) \ 378 ((sc)->sc_model->sip_vendor == (v) && \ 379 (sc)->sc_model->sip_product == (p) && \ 380 (sc)->sc_rev == (r)) 381 382 #define SIP_CHIP_MODEL(sc, v, p) \ 383 ((sc)->sc_model->sip_vendor == (v) && \ 384 (sc)->sc_model->sip_product == (p)) 385 386 #if !defined(DP83820) 387 #define SIP_SIS900_REV(sc, rev) \ 388 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 389 #endif 390 391 #define SIP_TIMEOUT 1000 392 393 void SIP_DECL(start)(struct ifnet *); 394 void SIP_DECL(watchdog)(struct ifnet *); 395 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 396 int SIP_DECL(init)(struct ifnet *); 397 void SIP_DECL(stop)(struct ifnet *, int); 398 399 void SIP_DECL(shutdown)(void *); 400 401 void SIP_DECL(reset)(struct sip_softc *); 402 void SIP_DECL(rxdrain)(struct sip_softc *); 403 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 404 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 405 void SIP_DECL(tick)(void *); 406 407 #if !defined(DP83820) 408 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 409 #endif /* ! DP83820 */ 410 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 411 412 #if defined(DP83820) 413 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 414 const struct pci_attach_args *, u_int8_t *); 415 #else 416 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 417 const struct pci_attach_args *, u_int8_t *); 418 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 419 const struct pci_attach_args *, u_int8_t *); 420 #endif /* DP83820 */ 421 422 int SIP_DECL(intr)(void *); 423 void SIP_DECL(txintr)(struct sip_softc *); 424 void SIP_DECL(rxintr)(struct sip_softc *); 425 426 #if defined(DP83820) 427 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 428 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 429 void SIP_DECL(dp83820_mii_statchg)(struct device *); 430 #else 431 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 432 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 433 void SIP_DECL(sis900_mii_statchg)(struct device *); 434 435 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 436 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 437 void SIP_DECL(dp83815_mii_statchg)(struct device *); 438 #endif /* DP83820 */ 439 440 int SIP_DECL(mediachange)(struct ifnet *); 441 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 442 443 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 444 void SIP_DECL(attach)(struct device *, struct device *, void *); 445 446 int SIP_DECL(copy_small) = 0; 447 448 struct cfattach SIP_DECL(ca) = { 449 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 450 }; 451 452 /* 453 * Descriptions of the variants of the SiS900. 454 */ 455 struct sip_variant { 456 int (*sipv_mii_readreg)(struct device *, int, int); 457 void (*sipv_mii_writereg)(struct device *, int, int, int); 458 void (*sipv_mii_statchg)(struct device *); 459 void (*sipv_set_filter)(struct sip_softc *); 460 void (*sipv_read_macaddr)(struct sip_softc *, 461 const struct pci_attach_args *, u_int8_t *); 462 }; 463 464 #if defined(DP83820) 465 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 466 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 467 468 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 469 SIP_DECL(dp83820_mii_bitbang_read), 470 SIP_DECL(dp83820_mii_bitbang_write), 471 { 472 EROMAR_MDIO, /* MII_BIT_MDO */ 473 EROMAR_MDIO, /* MII_BIT_MDI */ 474 EROMAR_MDC, /* MII_BIT_MDC */ 475 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 476 0, /* MII_BIT_DIR_PHY_HOST */ 477 } 478 }; 479 #endif /* DP83820 */ 480 481 #if defined(DP83820) 482 const struct sip_variant SIP_DECL(variant_dp83820) = { 483 SIP_DECL(dp83820_mii_readreg), 484 SIP_DECL(dp83820_mii_writereg), 485 SIP_DECL(dp83820_mii_statchg), 486 SIP_DECL(dp83815_set_filter), 487 SIP_DECL(dp83820_read_macaddr), 488 }; 489 #else 490 const struct sip_variant SIP_DECL(variant_sis900) = { 491 SIP_DECL(sis900_mii_readreg), 492 SIP_DECL(sis900_mii_writereg), 493 SIP_DECL(sis900_mii_statchg), 494 SIP_DECL(sis900_set_filter), 495 SIP_DECL(sis900_read_macaddr), 496 }; 497 498 const struct sip_variant SIP_DECL(variant_dp83815) = { 499 SIP_DECL(dp83815_mii_readreg), 500 SIP_DECL(dp83815_mii_writereg), 501 SIP_DECL(dp83815_mii_statchg), 502 SIP_DECL(dp83815_set_filter), 503 SIP_DECL(dp83815_read_macaddr), 504 }; 505 #endif /* DP83820 */ 506 507 /* 508 * Devices supported by this driver. 509 */ 510 const struct sip_product { 511 pci_vendor_id_t sip_vendor; 512 pci_product_id_t sip_product; 513 const char *sip_name; 514 const struct sip_variant *sip_variant; 515 } SIP_DECL(products)[] = { 516 #if defined(DP83820) 517 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 518 "NatSemi DP83820 Gigabit Ethernet", 519 &SIP_DECL(variant_dp83820) }, 520 #else 521 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 522 "SiS 900 10/100 Ethernet", 523 &SIP_DECL(variant_sis900) }, 524 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 525 "SiS 7016 10/100 Ethernet", 526 &SIP_DECL(variant_sis900) }, 527 528 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 529 "NatSemi DP83815 10/100 Ethernet", 530 &SIP_DECL(variant_dp83815) }, 531 #endif /* DP83820 */ 532 533 { 0, 0, 534 NULL, 535 NULL }, 536 }; 537 538 static const struct sip_product * 539 SIP_DECL(lookup)(const struct pci_attach_args *pa) 540 { 541 const struct sip_product *sip; 542 543 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 544 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 545 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 546 return (sip); 547 } 548 return (NULL); 549 } 550 551 int 552 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 553 { 554 struct pci_attach_args *pa = aux; 555 556 if (SIP_DECL(lookup)(pa) != NULL) 557 return (1); 558 559 return (0); 560 } 561 562 void 563 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 564 { 565 struct sip_softc *sc = (struct sip_softc *) self; 566 struct pci_attach_args *pa = aux; 567 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 568 pci_chipset_tag_t pc = pa->pa_pc; 569 pci_intr_handle_t ih; 570 const char *intrstr = NULL; 571 bus_space_tag_t iot, memt; 572 bus_space_handle_t ioh, memh; 573 bus_dma_segment_t seg; 574 int ioh_valid, memh_valid; 575 int i, rseg, error; 576 const struct sip_product *sip; 577 pcireg_t pmode; 578 u_int8_t enaddr[ETHER_ADDR_LEN]; 579 int pmreg; 580 #ifdef DP83820 581 pcireg_t memtype; 582 u_int32_t reg; 583 #endif /* DP83820 */ 584 585 callout_init(&sc->sc_tick_ch); 586 587 sip = SIP_DECL(lookup)(pa); 588 if (sip == NULL) { 589 printf("\n"); 590 panic(SIP_STR(attach) ": impossible"); 591 } 592 sc->sc_rev = PCI_REVISION(pa->pa_class); 593 594 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 595 596 sc->sc_model = sip; 597 598 /* 599 * XXX Work-around broken PXE firmware on some boards. 600 * 601 * The DP83815 shares an address decoder with the MEM BAR 602 * and the ROM BAR. Make sure the ROM BAR is disabled, 603 * so that memory mapped access works. 604 */ 605 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 606 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 607 ~PCI_MAPREG_ROM_ENABLE); 608 609 /* 610 * Map the device. 611 */ 612 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 613 PCI_MAPREG_TYPE_IO, 0, 614 &iot, &ioh, NULL, NULL) == 0); 615 #ifdef DP83820 616 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 617 switch (memtype) { 618 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 619 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 620 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 621 memtype, 0, &memt, &memh, NULL, NULL) == 0); 622 break; 623 default: 624 memh_valid = 0; 625 } 626 #else 627 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 628 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 629 &memt, &memh, NULL, NULL) == 0); 630 #endif /* DP83820 */ 631 632 if (memh_valid) { 633 sc->sc_st = memt; 634 sc->sc_sh = memh; 635 } else if (ioh_valid) { 636 sc->sc_st = iot; 637 sc->sc_sh = ioh; 638 } else { 639 printf("%s: unable to map device registers\n", 640 sc->sc_dev.dv_xname); 641 return; 642 } 643 644 sc->sc_dmat = pa->pa_dmat; 645 646 /* 647 * Make sure bus mastering is enabled. Also make sure 648 * Write/Invalidate is enabled if we're allowed to use it. 649 */ 650 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 651 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 652 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 653 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 654 pmreg | PCI_COMMAND_MASTER_ENABLE); 655 656 /* Get it out of power save mode if needed. */ 657 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 658 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 659 if (pmode == 3) { 660 /* 661 * The card has lost all configuration data in 662 * this state, so punt. 663 */ 664 printf("%s: unable to wake up from power state D3\n", 665 sc->sc_dev.dv_xname); 666 return; 667 } 668 if (pmode != 0) { 669 printf("%s: waking up from power state D%d\n", 670 sc->sc_dev.dv_xname, pmode); 671 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 672 } 673 } 674 675 /* 676 * Map and establish our interrupt. 677 */ 678 if (pci_intr_map(pa, &ih)) { 679 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 680 return; 681 } 682 intrstr = pci_intr_string(pc, ih); 683 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 684 if (sc->sc_ih == NULL) { 685 printf("%s: unable to establish interrupt", 686 sc->sc_dev.dv_xname); 687 if (intrstr != NULL) 688 printf(" at %s", intrstr); 689 printf("\n"); 690 return; 691 } 692 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 693 694 SIMPLEQ_INIT(&sc->sc_txfreeq); 695 SIMPLEQ_INIT(&sc->sc_txdirtyq); 696 697 /* 698 * Allocate the control data structures, and create and load the 699 * DMA map for it. 700 */ 701 if ((error = bus_dmamem_alloc(sc->sc_dmat, 702 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 703 0)) != 0) { 704 printf("%s: unable to allocate control data, error = %d\n", 705 sc->sc_dev.dv_xname, error); 706 goto fail_0; 707 } 708 709 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 710 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 711 BUS_DMA_COHERENT)) != 0) { 712 printf("%s: unable to map control data, error = %d\n", 713 sc->sc_dev.dv_xname, error); 714 goto fail_1; 715 } 716 717 if ((error = bus_dmamap_create(sc->sc_dmat, 718 sizeof(struct sip_control_data), 1, 719 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 720 printf("%s: unable to create control data DMA map, " 721 "error = %d\n", sc->sc_dev.dv_xname, error); 722 goto fail_2; 723 } 724 725 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 726 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 727 0)) != 0) { 728 printf("%s: unable to load control data DMA map, error = %d\n", 729 sc->sc_dev.dv_xname, error); 730 goto fail_3; 731 } 732 733 /* 734 * Create the transmit buffer DMA maps. 735 */ 736 for (i = 0; i < SIP_TXQUEUELEN; i++) { 737 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 738 SIP_NTXSEGS, MCLBYTES, 0, 0, 739 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 740 printf("%s: unable to create tx DMA map %d, " 741 "error = %d\n", sc->sc_dev.dv_xname, i, error); 742 goto fail_4; 743 } 744 } 745 746 /* 747 * Create the receive buffer DMA maps. 748 */ 749 for (i = 0; i < SIP_NRXDESC; i++) { 750 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 751 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 752 printf("%s: unable to create rx DMA map %d, " 753 "error = %d\n", sc->sc_dev.dv_xname, i, error); 754 goto fail_5; 755 } 756 sc->sc_rxsoft[i].rxs_mbuf = NULL; 757 } 758 759 /* 760 * Reset the chip to a known state. 761 */ 762 SIP_DECL(reset)(sc); 763 764 /* 765 * Read the Ethernet address from the EEPROM. This might 766 * also fetch other stuff from the EEPROM and stash it 767 * in the softc. 768 */ 769 sc->sc_cfg = 0; 770 #if !defined(DP83820) 771 if (SIP_SIS900_REV(sc,SIS_REV_635) || 772 SIP_SIS900_REV(sc,SIS_REV_900B)) 773 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 774 #endif 775 776 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 777 778 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 779 ether_sprintf(enaddr)); 780 781 /* 782 * Initialize the configuration register: aggressive PCI 783 * bus request algorithm, default backoff, default OW timer, 784 * default parity error detection. 785 * 786 * NOTE: "Big endian mode" is useless on the SiS900 and 787 * friends -- it affects packet data, not descriptors. 788 */ 789 #ifdef DP83820 790 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 791 if (reg & CFG_PCI64_DET) { 792 printf("%s: 64-bit PCI slot detected\n", sc->sc_dev.dv_xname); 793 /* 794 * XXX Need some PCI flags indicating support for 795 * XXX 64-bit addressing (SAC or DAC) and 64-bit 796 * XXX data path. 797 */ 798 } 799 if (sc->sc_cfg & (CFG_TBI_EN|CFG_EXT_125)) { 800 const char *sep = ""; 801 printf("%s: using ", sc->sc_dev.dv_xname); 802 if (sc->sc_cfg & CFG_EXT_125) { 803 printf("%s125MHz clock", sep); 804 sep = ", "; 805 } 806 if (sc->sc_cfg & CFG_TBI_EN) { 807 printf("%sten-bit interface", sep); 808 sep = ", "; 809 } 810 printf("\n"); 811 } 812 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0) 813 sc->sc_cfg |= CFG_MRM_DIS; 814 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 815 sc->sc_cfg |= CFG_MWI_DIS; 816 817 /* 818 * Use the extended descriptor format on the DP83820. This 819 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 820 * checksumming. 821 */ 822 sc->sc_cfg |= CFG_EXTSTS_EN; 823 #endif /* DP83820 */ 824 825 /* 826 * Initialize our media structures and probe the MII. 827 */ 828 sc->sc_mii.mii_ifp = ifp; 829 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 830 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 831 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 832 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 833 SIP_DECL(mediastatus)); 834 #ifdef DP83820 835 if (sc->sc_cfg & CFG_TBI_EN) { 836 /* Using ten-bit interface. */ 837 printf("%s: TBI -- FIXME\n", sc->sc_dev.dv_xname); 838 } else { 839 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 840 MII_OFFSET_ANY, 0); 841 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 842 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 843 0, NULL); 844 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 845 } else 846 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 847 } 848 #else 849 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 850 MII_OFFSET_ANY, 0); 851 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 852 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 853 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 854 } else 855 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 856 #endif /* DP83820 */ 857 858 ifp = &sc->sc_ethercom.ec_if; 859 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 860 ifp->if_softc = sc; 861 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 862 ifp->if_ioctl = SIP_DECL(ioctl); 863 ifp->if_start = SIP_DECL(start); 864 ifp->if_watchdog = SIP_DECL(watchdog); 865 ifp->if_init = SIP_DECL(init); 866 ifp->if_stop = SIP_DECL(stop); 867 IFQ_SET_READY(&ifp->if_snd); 868 869 /* 870 * We can support 802.1Q VLAN-sized frames. 871 */ 872 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 873 874 #ifdef DP83820 875 /* 876 * And the DP83820 can do VLAN tagging in hardware, and 877 * support the jumbo Ethernet MTU. 878 */ 879 sc->sc_ethercom.ec_capabilities |= 880 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 881 882 /* 883 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 884 * in hardware. 885 */ 886 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 887 IFCAP_CSUM_UDPv4; 888 #endif /* DP83820 */ 889 890 /* 891 * Attach the interface. 892 */ 893 if_attach(ifp); 894 ether_ifattach(ifp, enaddr); 895 896 /* 897 * The number of bytes that must be available in 898 * the Tx FIFO before the bus master can DMA more 899 * data into the FIFO. 900 */ 901 sc->sc_tx_fill_thresh = 64 / 32; 902 903 /* 904 * Start at a drain threshold of 512 bytes. We will 905 * increase it if a DMA underrun occurs. 906 * 907 * XXX The minimum value of this variable should be 908 * tuned. We may be able to improve performance 909 * by starting with a lower value. That, however, 910 * may trash the first few outgoing packets if the 911 * PCI bus is saturated. 912 */ 913 sc->sc_tx_drain_thresh = 1504 / 32; 914 915 /* 916 * Initialize the Rx FIFO drain threshold. 917 * 918 * This is in units of 8 bytes. 919 * 920 * We should never set this value lower than 2; 14 bytes are 921 * required to filter the packet. 922 */ 923 sc->sc_rx_drain_thresh = 128 / 8; 924 925 #ifdef SIP_EVENT_COUNTERS 926 /* 927 * Attach event counters. 928 */ 929 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 930 NULL, sc->sc_dev.dv_xname, "txsstall"); 931 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 932 NULL, sc->sc_dev.dv_xname, "txdstall"); 933 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 934 NULL, sc->sc_dev.dv_xname, "txintr"); 935 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 936 NULL, sc->sc_dev.dv_xname, "rxintr"); 937 #ifdef DP83820 938 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 939 NULL, sc->sc_dev.dv_xname, "rxipsum"); 940 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 941 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 942 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 943 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 944 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 945 NULL, sc->sc_dev.dv_xname, "txipsum"); 946 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 947 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 948 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 949 NULL, sc->sc_dev.dv_xname, "txudpsum"); 950 #endif /* DP83820 */ 951 #endif /* SIP_EVENT_COUNTERS */ 952 953 /* 954 * Make sure the interface is shutdown during reboot. 955 */ 956 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 957 if (sc->sc_sdhook == NULL) 958 printf("%s: WARNING: unable to establish shutdown hook\n", 959 sc->sc_dev.dv_xname); 960 return; 961 962 /* 963 * Free any resources we've allocated during the failed attach 964 * attempt. Do this in reverse order and fall through. 965 */ 966 fail_5: 967 for (i = 0; i < SIP_NRXDESC; i++) { 968 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 969 bus_dmamap_destroy(sc->sc_dmat, 970 sc->sc_rxsoft[i].rxs_dmamap); 971 } 972 fail_4: 973 for (i = 0; i < SIP_TXQUEUELEN; i++) { 974 if (sc->sc_txsoft[i].txs_dmamap != NULL) 975 bus_dmamap_destroy(sc->sc_dmat, 976 sc->sc_txsoft[i].txs_dmamap); 977 } 978 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 979 fail_3: 980 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 981 fail_2: 982 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 983 sizeof(struct sip_control_data)); 984 fail_1: 985 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 986 fail_0: 987 return; 988 } 989 990 /* 991 * sip_shutdown: 992 * 993 * Make sure the interface is stopped at reboot time. 994 */ 995 void 996 SIP_DECL(shutdown)(void *arg) 997 { 998 struct sip_softc *sc = arg; 999 1000 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1001 } 1002 1003 /* 1004 * sip_start: [ifnet interface function] 1005 * 1006 * Start packet transmission on the interface. 1007 */ 1008 void 1009 SIP_DECL(start)(struct ifnet *ifp) 1010 { 1011 struct sip_softc *sc = ifp->if_softc; 1012 struct mbuf *m0, *m; 1013 struct sip_txsoft *txs; 1014 bus_dmamap_t dmamap; 1015 int error, firsttx, nexttx, lasttx, ofree, seg; 1016 #ifdef DP83820 1017 u_int32_t extsts; 1018 #endif 1019 1020 /* 1021 * If we've been told to pause, don't transmit any more packets. 1022 */ 1023 if (sc->sc_flags & SIPF_PAUSED) 1024 ifp->if_flags |= IFF_OACTIVE; 1025 1026 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1027 return; 1028 1029 /* 1030 * Remember the previous number of free descriptors and 1031 * the first descriptor we'll use. 1032 */ 1033 ofree = sc->sc_txfree; 1034 firsttx = sc->sc_txnext; 1035 1036 /* 1037 * Loop through the send queue, setting up transmit descriptors 1038 * until we drain the queue, or use up all available transmit 1039 * descriptors. 1040 */ 1041 for (;;) { 1042 /* Get a work queue entry. */ 1043 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1044 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1045 break; 1046 } 1047 1048 /* 1049 * Grab a packet off the queue. 1050 */ 1051 IFQ_POLL(&ifp->if_snd, m0); 1052 if (m0 == NULL) 1053 break; 1054 #ifndef DP83820 1055 m = NULL; 1056 #endif 1057 1058 dmamap = txs->txs_dmamap; 1059 1060 #ifdef DP83820 1061 /* 1062 * Load the DMA map. If this fails, the packet either 1063 * didn't fit in the allotted number of segments, or we 1064 * were short on resources. For the too-many-segments 1065 * case, we simply report an error and drop the packet, 1066 * since we can't sanely copy a jumbo packet to a single 1067 * buffer. 1068 */ 1069 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1070 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1071 if (error) { 1072 if (error == EFBIG) { 1073 printf("%s: Tx packet consumes too many " 1074 "DMA segments, dropping...\n", 1075 sc->sc_dev.dv_xname); 1076 IFQ_DEQUEUE(&ifp->if_snd, m0); 1077 m_freem(m0); 1078 continue; 1079 } 1080 /* 1081 * Short on resources, just stop for now. 1082 */ 1083 break; 1084 } 1085 #else /* DP83820 */ 1086 /* 1087 * Load the DMA map. If this fails, the packet either 1088 * didn't fit in the alloted number of segments, or we 1089 * were short on resources. In this case, we'll copy 1090 * and try again. 1091 */ 1092 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1093 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1094 MGETHDR(m, M_DONTWAIT, MT_DATA); 1095 if (m == NULL) { 1096 printf("%s: unable to allocate Tx mbuf\n", 1097 sc->sc_dev.dv_xname); 1098 break; 1099 } 1100 if (m0->m_pkthdr.len > MHLEN) { 1101 MCLGET(m, M_DONTWAIT); 1102 if ((m->m_flags & M_EXT) == 0) { 1103 printf("%s: unable to allocate Tx " 1104 "cluster\n", sc->sc_dev.dv_xname); 1105 m_freem(m); 1106 break; 1107 } 1108 } 1109 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1110 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1111 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1112 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1113 if (error) { 1114 printf("%s: unable to load Tx buffer, " 1115 "error = %d\n", sc->sc_dev.dv_xname, error); 1116 break; 1117 } 1118 } 1119 #endif /* DP83820 */ 1120 1121 /* 1122 * Ensure we have enough descriptors free to describe 1123 * the packet. Note, we always reserve one descriptor 1124 * at the end of the ring as a termination point, to 1125 * prevent wrap-around. 1126 */ 1127 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1128 /* 1129 * Not enough free descriptors to transmit this 1130 * packet. We haven't committed anything yet, 1131 * so just unload the DMA map, put the packet 1132 * back on the queue, and punt. Notify the upper 1133 * layer that there are not more slots left. 1134 * 1135 * XXX We could allocate an mbuf and copy, but 1136 * XXX is it worth it? 1137 */ 1138 ifp->if_flags |= IFF_OACTIVE; 1139 bus_dmamap_unload(sc->sc_dmat, dmamap); 1140 #ifndef DP83820 1141 if (m != NULL) 1142 m_freem(m); 1143 #endif 1144 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1145 break; 1146 } 1147 1148 IFQ_DEQUEUE(&ifp->if_snd, m0); 1149 #ifndef DP83820 1150 if (m != NULL) { 1151 m_freem(m0); 1152 m0 = m; 1153 } 1154 #endif 1155 1156 /* 1157 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1158 */ 1159 1160 /* Sync the DMA map. */ 1161 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1162 BUS_DMASYNC_PREWRITE); 1163 1164 /* 1165 * Initialize the transmit descriptors. 1166 */ 1167 for (nexttx = sc->sc_txnext, seg = 0; 1168 seg < dmamap->dm_nsegs; 1169 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1170 /* 1171 * If this is the first descriptor we're 1172 * enqueueing, don't set the OWN bit just 1173 * yet. That could cause a race condition. 1174 * We'll do it below. 1175 */ 1176 sc->sc_txdescs[nexttx].sipd_bufptr = 1177 htole32(dmamap->dm_segs[seg].ds_addr); 1178 sc->sc_txdescs[nexttx].sipd_cmdsts = 1179 htole32((nexttx == firsttx ? 0 : CMDSTS_OWN) | 1180 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1181 #ifdef DP83820 1182 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1183 #endif /* DP83820 */ 1184 lasttx = nexttx; 1185 } 1186 1187 /* Clear the MORE bit on the last segment. */ 1188 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1189 1190 #ifdef DP83820 1191 /* 1192 * If VLANs are enabled and the packet has a VLAN tag, set 1193 * up the descriptor to encapsulate the packet for us. 1194 * 1195 * This apparently has to be on the last descriptor of 1196 * the packet. 1197 */ 1198 if (sc->sc_ethercom.ec_nvlans != 0 && 1199 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1200 sc->sc_txdescs[lasttx].sipd_extsts |= 1201 htole32(EXTSTS_VPKT | 1202 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1203 } 1204 1205 /* 1206 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1207 * checksumming, set up the descriptor to do this work 1208 * for us. 1209 * 1210 * This apparently has to be on the first descriptor of 1211 * the packet. 1212 * 1213 * Byte-swap constants so the compiler can optimize. 1214 */ 1215 extsts = 0; 1216 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1217 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1218 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1219 extsts |= htole32(EXTSTS_IPPKT); 1220 } 1221 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1222 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1223 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1224 extsts |= htole32(EXTSTS_TCPPKT); 1225 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1226 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1227 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1228 extsts |= htole32(EXTSTS_UDPPKT); 1229 } 1230 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1231 #endif /* DP83820 */ 1232 1233 /* Sync the descriptors we're using. */ 1234 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1235 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1236 1237 /* 1238 * Store a pointer to the packet so we can free it later, 1239 * and remember what txdirty will be once the packet is 1240 * done. 1241 */ 1242 txs->txs_mbuf = m0; 1243 txs->txs_firstdesc = sc->sc_txnext; 1244 txs->txs_lastdesc = lasttx; 1245 1246 /* Advance the tx pointer. */ 1247 sc->sc_txfree -= dmamap->dm_nsegs; 1248 sc->sc_txnext = nexttx; 1249 1250 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1251 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1252 1253 #if NBPFILTER > 0 1254 /* 1255 * Pass the packet to any BPF listeners. 1256 */ 1257 if (ifp->if_bpf) 1258 bpf_mtap(ifp->if_bpf, m0); 1259 #endif /* NBPFILTER > 0 */ 1260 } 1261 1262 if (txs == NULL || sc->sc_txfree == 0) { 1263 /* No more slots left; notify upper layer. */ 1264 ifp->if_flags |= IFF_OACTIVE; 1265 } 1266 1267 if (sc->sc_txfree != ofree) { 1268 /* 1269 * Cause a descriptor interrupt to happen on the 1270 * last packet we enqueued. 1271 */ 1272 sc->sc_txdescs[lasttx].sipd_cmdsts |= htole32(CMDSTS_INTR); 1273 SIP_CDTXSYNC(sc, lasttx, 1, 1274 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1275 1276 /* 1277 * The entire packet chain is set up. Give the 1278 * first descrptor to the chip now. 1279 */ 1280 sc->sc_txdescs[firsttx].sipd_cmdsts |= htole32(CMDSTS_OWN); 1281 SIP_CDTXSYNC(sc, firsttx, 1, 1282 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1283 1284 /* 1285 * Start the transmit process. Note, the manual says 1286 * that if there are no pending transmissions in the 1287 * chip's internal queue (indicated by TXE being clear), 1288 * then the driver software must set the TXDP to the 1289 * first descriptor to be transmitted. However, if we 1290 * do this, it causes serious performance degredation on 1291 * the DP83820 under load, not setting TXDP doesn't seem 1292 * to adversely affect the SiS 900 or DP83815. 1293 * 1294 * Well, I guess it wouldn't be the first time a manual 1295 * has lied -- and they could be speaking of the NULL- 1296 * terminated descriptor list case, rather than OWN- 1297 * terminated rings. 1298 */ 1299 #if 0 1300 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1301 CR_TXE) == 0) { 1302 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1303 SIP_CDTXADDR(sc, firsttx)); 1304 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1305 } 1306 #else 1307 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1308 #endif 1309 1310 /* Set a watchdog timer in case the chip flakes out. */ 1311 ifp->if_timer = 5; 1312 } 1313 } 1314 1315 /* 1316 * sip_watchdog: [ifnet interface function] 1317 * 1318 * Watchdog timer handler. 1319 */ 1320 void 1321 SIP_DECL(watchdog)(struct ifnet *ifp) 1322 { 1323 struct sip_softc *sc = ifp->if_softc; 1324 1325 /* 1326 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1327 * If we get a timeout, try and sweep up transmit descriptors. 1328 * If we manage to sweep them all up, ignore the lack of 1329 * interrupt. 1330 */ 1331 SIP_DECL(txintr)(sc); 1332 1333 if (sc->sc_txfree != SIP_NTXDESC) { 1334 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1335 ifp->if_oerrors++; 1336 1337 /* Reset the interface. */ 1338 (void) SIP_DECL(init)(ifp); 1339 } else if (ifp->if_flags & IFF_DEBUG) 1340 printf("%s: recovered from device timeout\n", 1341 sc->sc_dev.dv_xname); 1342 1343 /* Try to get more packets going. */ 1344 SIP_DECL(start)(ifp); 1345 } 1346 1347 /* 1348 * sip_ioctl: [ifnet interface function] 1349 * 1350 * Handle control requests from the operator. 1351 */ 1352 int 1353 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1354 { 1355 struct sip_softc *sc = ifp->if_softc; 1356 struct ifreq *ifr = (struct ifreq *)data; 1357 int s, error; 1358 1359 s = splnet(); 1360 1361 switch (cmd) { 1362 case SIOCSIFMEDIA: 1363 case SIOCGIFMEDIA: 1364 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1365 break; 1366 1367 default: 1368 error = ether_ioctl(ifp, cmd, data); 1369 if (error == ENETRESET) { 1370 /* 1371 * Multicast list has changed; set the hardware filter 1372 * accordingly. 1373 */ 1374 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1375 error = 0; 1376 } 1377 break; 1378 } 1379 1380 /* Try to get more packets going. */ 1381 SIP_DECL(start)(ifp); 1382 1383 splx(s); 1384 return (error); 1385 } 1386 1387 /* 1388 * sip_intr: 1389 * 1390 * Interrupt service routine. 1391 */ 1392 int 1393 SIP_DECL(intr)(void *arg) 1394 { 1395 struct sip_softc *sc = arg; 1396 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1397 u_int32_t isr; 1398 int handled = 0; 1399 1400 for (;;) { 1401 /* Reading clears interrupt. */ 1402 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1403 if ((isr & sc->sc_imr) == 0) 1404 break; 1405 1406 handled = 1; 1407 1408 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1409 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1410 1411 /* Grab any new packets. */ 1412 SIP_DECL(rxintr)(sc); 1413 1414 if (isr & ISR_RXORN) { 1415 printf("%s: receive FIFO overrun\n", 1416 sc->sc_dev.dv_xname); 1417 1418 /* XXX adjust rx_drain_thresh? */ 1419 } 1420 1421 if (isr & ISR_RXIDLE) { 1422 printf("%s: receive ring overrun\n", 1423 sc->sc_dev.dv_xname); 1424 1425 /* Get the receive process going again. */ 1426 bus_space_write_4(sc->sc_st, sc->sc_sh, 1427 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1428 bus_space_write_4(sc->sc_st, sc->sc_sh, 1429 SIP_CR, CR_RXE); 1430 } 1431 } 1432 1433 if (isr & (ISR_TXURN|ISR_TXDESC)) { 1434 SIP_EVCNT_INCR(&sc->sc_ev_txintr); 1435 1436 /* Sweep up transmit descriptors. */ 1437 SIP_DECL(txintr)(sc); 1438 1439 if (isr & ISR_TXURN) { 1440 u_int32_t thresh; 1441 1442 printf("%s: transmit FIFO underrun", 1443 sc->sc_dev.dv_xname); 1444 1445 thresh = sc->sc_tx_drain_thresh + 1; 1446 if (thresh <= TXCFG_DRTH && 1447 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1448 (sc->sc_tx_fill_thresh * 32))) { 1449 printf("; increasing Tx drain " 1450 "threshold to %u bytes\n", 1451 thresh * 32); 1452 sc->sc_tx_drain_thresh = thresh; 1453 (void) SIP_DECL(init)(ifp); 1454 } else { 1455 (void) SIP_DECL(init)(ifp); 1456 printf("\n"); 1457 } 1458 } 1459 } 1460 1461 #if !defined(DP83820) 1462 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1463 if (isr & ISR_PAUSE_ST) { 1464 sc->sc_flags |= SIPF_PAUSED; 1465 ifp->if_flags |= IFF_OACTIVE; 1466 } 1467 if (isr & ISR_PAUSE_END) { 1468 sc->sc_flags &= ~SIPF_PAUSED; 1469 ifp->if_flags &= ~IFF_OACTIVE; 1470 } 1471 } 1472 #endif /* ! DP83820 */ 1473 1474 if (isr & ISR_HIBERR) { 1475 #define PRINTERR(bit, str) \ 1476 if (isr & (bit)) \ 1477 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1478 PRINTERR(ISR_DPERR, "parity error"); 1479 PRINTERR(ISR_SSERR, "system error"); 1480 PRINTERR(ISR_RMABT, "master abort"); 1481 PRINTERR(ISR_RTABT, "target abort"); 1482 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1483 (void) SIP_DECL(init)(ifp); 1484 #undef PRINTERR 1485 } 1486 } 1487 1488 /* Try to get more packets going. */ 1489 SIP_DECL(start)(ifp); 1490 1491 return (handled); 1492 } 1493 1494 /* 1495 * sip_txintr: 1496 * 1497 * Helper; handle transmit interrupts. 1498 */ 1499 void 1500 SIP_DECL(txintr)(struct sip_softc *sc) 1501 { 1502 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1503 struct sip_txsoft *txs; 1504 u_int32_t cmdsts; 1505 1506 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1507 ifp->if_flags &= ~IFF_OACTIVE; 1508 1509 /* 1510 * Go through our Tx list and free mbufs for those 1511 * frames which have been transmitted. 1512 */ 1513 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1514 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1515 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1516 1517 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1518 if (cmdsts & CMDSTS_OWN) 1519 break; 1520 1521 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1522 1523 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1524 1525 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1526 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1527 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1528 m_freem(txs->txs_mbuf); 1529 txs->txs_mbuf = NULL; 1530 1531 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1532 1533 /* 1534 * Check for errors and collisions. 1535 */ 1536 if (cmdsts & 1537 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1538 ifp->if_oerrors++; 1539 if (cmdsts & CMDSTS_Tx_EC) 1540 ifp->if_collisions += 16; 1541 if (ifp->if_flags & IFF_DEBUG) { 1542 if (cmdsts & CMDSTS_Tx_ED) 1543 printf("%s: excessive deferral\n", 1544 sc->sc_dev.dv_xname); 1545 if (cmdsts & CMDSTS_Tx_EC) 1546 printf("%s: excessive collisions\n", 1547 sc->sc_dev.dv_xname); 1548 } 1549 } else { 1550 /* Packet was transmitted successfully. */ 1551 ifp->if_opackets++; 1552 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1553 } 1554 } 1555 1556 /* 1557 * If there are no more pending transmissions, cancel the watchdog 1558 * timer. 1559 */ 1560 if (txs == NULL) 1561 ifp->if_timer = 0; 1562 } 1563 1564 #if defined(DP83820) 1565 /* 1566 * sip_rxintr: 1567 * 1568 * Helper; handle receive interrupts. 1569 */ 1570 void 1571 SIP_DECL(rxintr)(struct sip_softc *sc) 1572 { 1573 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1574 struct sip_rxsoft *rxs; 1575 struct mbuf *m, *tailm; 1576 u_int32_t cmdsts, extsts; 1577 int i, len; 1578 1579 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1580 rxs = &sc->sc_rxsoft[i]; 1581 1582 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1583 1584 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1585 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1586 1587 /* 1588 * NOTE: OWN is set if owned by _consumer_. We're the 1589 * consumer of the receive ring, so if the bit is clear, 1590 * we have processed all of the packets. 1591 */ 1592 if ((cmdsts & CMDSTS_OWN) == 0) { 1593 /* 1594 * We have processed all of the receive buffers. 1595 */ 1596 break; 1597 } 1598 1599 if (__predict_false(sc->sc_rxdiscard)) { 1600 SIP_INIT_RXDESC(sc, i); 1601 if ((cmdsts & CMDSTS_MORE) == 0) { 1602 /* Reset our state. */ 1603 sc->sc_rxdiscard = 0; 1604 } 1605 continue; 1606 } 1607 1608 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1609 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1610 1611 m = rxs->rxs_mbuf; 1612 1613 /* 1614 * Add a new receive buffer to the ring. 1615 */ 1616 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1617 /* 1618 * Failed, throw away what we've done so 1619 * far, and discard the rest of the packet. 1620 */ 1621 ifp->if_ierrors++; 1622 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1623 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1624 SIP_INIT_RXDESC(sc, i); 1625 if (cmdsts & CMDSTS_MORE) 1626 sc->sc_rxdiscard = 1; 1627 if (sc->sc_rxhead != NULL) 1628 m_freem(sc->sc_rxhead); 1629 SIP_RXCHAIN_RESET(sc); 1630 continue; 1631 } 1632 1633 SIP_RXCHAIN_LINK(sc, m); 1634 1635 /* 1636 * If this is not the end of the packet, keep 1637 * looking. 1638 */ 1639 if (cmdsts & CMDSTS_MORE) { 1640 sc->sc_rxlen += m->m_len; 1641 continue; 1642 } 1643 1644 /* 1645 * Okay, we have the entire packet now... 1646 */ 1647 *sc->sc_rxtailp = NULL; 1648 m = sc->sc_rxhead; 1649 tailm = sc->sc_rxtail; 1650 1651 SIP_RXCHAIN_RESET(sc); 1652 1653 /* 1654 * If an error occurred, update stats and drop the packet. 1655 */ 1656 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1657 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1658 ifp->if_ierrors++; 1659 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1660 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1661 /* Receive overrun handled elsewhere. */ 1662 printf("%s: receive descriptor error\n", 1663 sc->sc_dev.dv_xname); 1664 } 1665 #define PRINTERR(bit, str) \ 1666 if (cmdsts & (bit)) \ 1667 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1668 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1669 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1670 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1671 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1672 #undef PRINTERR 1673 m_freem(m); 1674 continue; 1675 } 1676 1677 /* 1678 * No errors. 1679 * 1680 * Note, the DP83820 includes the CRC with 1681 * every packet. 1682 */ 1683 len = CMDSTS_SIZE(cmdsts); 1684 tailm->m_len = len - sc->sc_rxlen; 1685 1686 /* 1687 * If the packet is small enough to fit in a 1688 * single header mbuf, allocate one and copy 1689 * the data into it. This greatly reduces 1690 * memory consumption when we receive lots 1691 * of small packets. 1692 */ 1693 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1694 struct mbuf *nm; 1695 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1696 if (nm == NULL) { 1697 ifp->if_ierrors++; 1698 m_freem(m); 1699 continue; 1700 } 1701 nm->m_data += 2; 1702 nm->m_pkthdr.len = nm->m_len = len; 1703 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1704 m_freem(m); 1705 m = nm; 1706 } 1707 #ifndef __NO_STRICT_ALIGNMENT 1708 else { 1709 /* 1710 * The DP83820's receive buffers must be 4-byte 1711 * aligned. But this means that the data after 1712 * the Ethernet header is misaligned. To compensate, 1713 * we have artificially shortened the buffer size 1714 * in the descriptor, and we do an overlapping copy 1715 * of the data two bytes further in (in the first 1716 * buffer of the chain only). 1717 */ 1718 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1719 m->m_len); 1720 m->m_data += 2; 1721 } 1722 #endif /* ! __NO_STRICT_ALIGNMENT */ 1723 1724 /* 1725 * If VLANs are enabled, VLAN packets have been unwrapped 1726 * for us. Associate the tag with the packet. 1727 */ 1728 if (sc->sc_ethercom.ec_nvlans != 0 && 1729 (extsts & EXTSTS_VPKT) != 0) { 1730 struct mbuf *vtag; 1731 1732 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1733 if (vtag == NULL) { 1734 ifp->if_ierrors++; 1735 printf("%s: unable to allocate VLAN tag\n", 1736 sc->sc_dev.dv_xname); 1737 m_freem(m); 1738 continue; 1739 } 1740 1741 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1742 vtag->m_len = sizeof(int); 1743 } 1744 1745 /* 1746 * Set the incoming checksum information for the 1747 * packet. 1748 */ 1749 if ((extsts & EXTSTS_IPPKT) != 0) { 1750 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1751 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1752 if (extsts & EXTSTS_Rx_IPERR) 1753 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1754 if (extsts & EXTSTS_TCPPKT) { 1755 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1756 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1757 if (extsts & EXTSTS_Rx_TCPERR) 1758 m->m_pkthdr.csum_flags |= 1759 M_CSUM_TCP_UDP_BAD; 1760 } else if (extsts & EXTSTS_UDPPKT) { 1761 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1762 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1763 if (extsts & EXTSTS_Rx_UDPERR) 1764 m->m_pkthdr.csum_flags |= 1765 M_CSUM_TCP_UDP_BAD; 1766 } 1767 } 1768 1769 ifp->if_ipackets++; 1770 m->m_flags |= M_HASFCS; 1771 m->m_pkthdr.rcvif = ifp; 1772 m->m_pkthdr.len = len; 1773 1774 #if NBPFILTER > 0 1775 /* 1776 * Pass this up to any BPF listeners, but only 1777 * pass if up the stack if it's for us. 1778 */ 1779 if (ifp->if_bpf) 1780 bpf_mtap(ifp->if_bpf, m); 1781 #endif /* NBPFILTER > 0 */ 1782 1783 /* Pass it on. */ 1784 (*ifp->if_input)(ifp, m); 1785 } 1786 1787 /* Update the receive pointer. */ 1788 sc->sc_rxptr = i; 1789 } 1790 #else /* ! DP83820 */ 1791 /* 1792 * sip_rxintr: 1793 * 1794 * Helper; handle receive interrupts. 1795 */ 1796 void 1797 SIP_DECL(rxintr)(struct sip_softc *sc) 1798 { 1799 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1800 struct sip_rxsoft *rxs; 1801 struct mbuf *m; 1802 u_int32_t cmdsts; 1803 int i, len; 1804 1805 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1806 rxs = &sc->sc_rxsoft[i]; 1807 1808 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1809 1810 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1811 1812 /* 1813 * NOTE: OWN is set if owned by _consumer_. We're the 1814 * consumer of the receive ring, so if the bit is clear, 1815 * we have processed all of the packets. 1816 */ 1817 if ((cmdsts & CMDSTS_OWN) == 0) { 1818 /* 1819 * We have processed all of the receive buffers. 1820 */ 1821 break; 1822 } 1823 1824 /* 1825 * If any collisions were seen on the wire, count one. 1826 */ 1827 if (cmdsts & CMDSTS_Rx_COL) 1828 ifp->if_collisions++; 1829 1830 /* 1831 * If an error occurred, update stats, clear the status 1832 * word, and leave the packet buffer in place. It will 1833 * simply be reused the next time the ring comes around. 1834 */ 1835 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1836 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1837 ifp->if_ierrors++; 1838 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1839 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1840 /* Receive overrun handled elsewhere. */ 1841 printf("%s: receive descriptor error\n", 1842 sc->sc_dev.dv_xname); 1843 } 1844 #define PRINTERR(bit, str) \ 1845 if (cmdsts & (bit)) \ 1846 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1847 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1848 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1849 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1850 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1851 #undef PRINTERR 1852 SIP_INIT_RXDESC(sc, i); 1853 continue; 1854 } 1855 1856 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1857 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1858 1859 /* 1860 * No errors; receive the packet. Note, the SiS 900 1861 * includes the CRC with every packet. 1862 */ 1863 len = CMDSTS_SIZE(cmdsts); 1864 1865 #ifdef __NO_STRICT_ALIGNMENT 1866 /* 1867 * If the packet is small enough to fit in a 1868 * single header mbuf, allocate one and copy 1869 * the data into it. This greatly reduces 1870 * memory consumption when we receive lots 1871 * of small packets. 1872 * 1873 * Otherwise, we add a new buffer to the receive 1874 * chain. If this fails, we drop the packet and 1875 * recycle the old buffer. 1876 */ 1877 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1878 MGETHDR(m, M_DONTWAIT, MT_DATA); 1879 if (m == NULL) 1880 goto dropit; 1881 memcpy(mtod(m, caddr_t), 1882 mtod(rxs->rxs_mbuf, caddr_t), len); 1883 SIP_INIT_RXDESC(sc, i); 1884 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1885 rxs->rxs_dmamap->dm_mapsize, 1886 BUS_DMASYNC_PREREAD); 1887 } else { 1888 m = rxs->rxs_mbuf; 1889 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1890 dropit: 1891 ifp->if_ierrors++; 1892 SIP_INIT_RXDESC(sc, i); 1893 bus_dmamap_sync(sc->sc_dmat, 1894 rxs->rxs_dmamap, 0, 1895 rxs->rxs_dmamap->dm_mapsize, 1896 BUS_DMASYNC_PREREAD); 1897 continue; 1898 } 1899 } 1900 #else 1901 /* 1902 * The SiS 900's receive buffers must be 4-byte aligned. 1903 * But this means that the data after the Ethernet header 1904 * is misaligned. We must allocate a new buffer and 1905 * copy the data, shifted forward 2 bytes. 1906 */ 1907 MGETHDR(m, M_DONTWAIT, MT_DATA); 1908 if (m == NULL) { 1909 dropit: 1910 ifp->if_ierrors++; 1911 SIP_INIT_RXDESC(sc, i); 1912 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1913 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1914 continue; 1915 } 1916 if (len > (MHLEN - 2)) { 1917 MCLGET(m, M_DONTWAIT); 1918 if ((m->m_flags & M_EXT) == 0) { 1919 m_freem(m); 1920 goto dropit; 1921 } 1922 } 1923 m->m_data += 2; 1924 1925 /* 1926 * Note that we use clusters for incoming frames, so the 1927 * buffer is virtually contiguous. 1928 */ 1929 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1930 1931 /* Allow the receive descriptor to continue using its mbuf. */ 1932 SIP_INIT_RXDESC(sc, i); 1933 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1934 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1935 #endif /* __NO_STRICT_ALIGNMENT */ 1936 1937 ifp->if_ipackets++; 1938 m->m_flags |= M_HASFCS; 1939 m->m_pkthdr.rcvif = ifp; 1940 m->m_pkthdr.len = m->m_len = len; 1941 1942 #if NBPFILTER > 0 1943 /* 1944 * Pass this up to any BPF listeners, but only 1945 * pass if up the stack if it's for us. 1946 */ 1947 if (ifp->if_bpf) 1948 bpf_mtap(ifp->if_bpf, m); 1949 #endif /* NBPFILTER > 0 */ 1950 1951 /* Pass it on. */ 1952 (*ifp->if_input)(ifp, m); 1953 } 1954 1955 /* Update the receive pointer. */ 1956 sc->sc_rxptr = i; 1957 } 1958 #endif /* DP83820 */ 1959 1960 /* 1961 * sip_tick: 1962 * 1963 * One second timer, used to tick the MII. 1964 */ 1965 void 1966 SIP_DECL(tick)(void *arg) 1967 { 1968 struct sip_softc *sc = arg; 1969 int s; 1970 1971 s = splnet(); 1972 mii_tick(&sc->sc_mii); 1973 splx(s); 1974 1975 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 1976 } 1977 1978 /* 1979 * sip_reset: 1980 * 1981 * Perform a soft reset on the SiS 900. 1982 */ 1983 void 1984 SIP_DECL(reset)(struct sip_softc *sc) 1985 { 1986 bus_space_tag_t st = sc->sc_st; 1987 bus_space_handle_t sh = sc->sc_sh; 1988 int i; 1989 1990 bus_space_write_4(st, sh, SIP_IER, 0); 1991 bus_space_write_4(st, sh, SIP_IMR, 0); 1992 bus_space_write_4(st, sh, SIP_RFCR, 0); 1993 bus_space_write_4(st, sh, SIP_CR, CR_RST); 1994 1995 for (i = 0; i < SIP_TIMEOUT; i++) { 1996 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 1997 break; 1998 delay(2); 1999 } 2000 2001 if (i == SIP_TIMEOUT) 2002 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2003 2004 delay(1000); 2005 2006 #ifdef DP83820 2007 /* 2008 * Set the general purpose I/O bits. Do it here in case we 2009 * need to have GPIO set up to talk to the media interface. 2010 */ 2011 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2012 delay(1000); 2013 #endif /* DP83820 */ 2014 } 2015 2016 /* 2017 * sip_init: [ ifnet interface function ] 2018 * 2019 * Initialize the interface. Must be called at splnet(). 2020 */ 2021 int 2022 SIP_DECL(init)(struct ifnet *ifp) 2023 { 2024 struct sip_softc *sc = ifp->if_softc; 2025 bus_space_tag_t st = sc->sc_st; 2026 bus_space_handle_t sh = sc->sc_sh; 2027 struct sip_txsoft *txs; 2028 struct sip_rxsoft *rxs; 2029 struct sip_desc *sipd; 2030 u_int32_t reg; 2031 int i, error = 0; 2032 2033 /* 2034 * Cancel any pending I/O. 2035 */ 2036 SIP_DECL(stop)(ifp, 0); 2037 2038 /* 2039 * Reset the chip to a known state. 2040 */ 2041 SIP_DECL(reset)(sc); 2042 2043 #if !defined(DP83820) 2044 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2045 /* 2046 * DP83815 manual, page 78: 2047 * 4.4 Recommended Registers Configuration 2048 * For optimum performance of the DP83815, version noted 2049 * as DP83815CVNG (SRR = 203h), the listed register 2050 * modifications must be followed in sequence... 2051 * 2052 * It's not clear if this should be 302h or 203h because that 2053 * chip name is listed as SRR 302h in the description of the 2054 * SRR register. However, my revision 302h DP83815 on the 2055 * Netgear FA311 purchased in 02/2001 needs these settings 2056 * to avoid tons of errors in AcceptPerfectMatch (non- 2057 * IFF_PROMISC) mode. I do not know if other revisions need 2058 * this set or not. [briggs -- 09 March 2001] 2059 * 2060 * Note that only the low-order 12 bits of 0xe4 are documented 2061 * and that this sets reserved bits in that register. 2062 */ 2063 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 2064 if (reg == 0x302) { 2065 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2066 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2067 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2068 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2069 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2070 } 2071 } 2072 #endif /* ! DP83820 */ 2073 2074 /* 2075 * Initialize the transmit descriptor ring. 2076 */ 2077 for (i = 0; i < SIP_NTXDESC; i++) { 2078 sipd = &sc->sc_txdescs[i]; 2079 memset(sipd, 0, sizeof(struct sip_desc)); 2080 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2081 } 2082 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2083 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2084 sc->sc_txfree = SIP_NTXDESC; 2085 sc->sc_txnext = 0; 2086 2087 /* 2088 * Initialize the transmit job descriptors. 2089 */ 2090 SIMPLEQ_INIT(&sc->sc_txfreeq); 2091 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2092 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2093 txs = &sc->sc_txsoft[i]; 2094 txs->txs_mbuf = NULL; 2095 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2096 } 2097 2098 /* 2099 * Initialize the receive descriptor and receive job 2100 * descriptor rings. 2101 */ 2102 for (i = 0; i < SIP_NRXDESC; i++) { 2103 rxs = &sc->sc_rxsoft[i]; 2104 if (rxs->rxs_mbuf == NULL) { 2105 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2106 printf("%s: unable to allocate or map rx " 2107 "buffer %d, error = %d\n", 2108 sc->sc_dev.dv_xname, i, error); 2109 /* 2110 * XXX Should attempt to run with fewer receive 2111 * XXX buffers instead of just failing. 2112 */ 2113 SIP_DECL(rxdrain)(sc); 2114 goto out; 2115 } 2116 } else 2117 SIP_INIT_RXDESC(sc, i); 2118 } 2119 sc->sc_rxptr = 0; 2120 #ifdef DP83820 2121 sc->sc_rxdiscard = 0; 2122 SIP_RXCHAIN_RESET(sc); 2123 #endif /* DP83820 */ 2124 2125 /* 2126 * Set the configuration register; it's already initialized 2127 * in sip_attach(). 2128 */ 2129 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2130 2131 /* 2132 * Initialize the prototype TXCFG register. 2133 */ 2134 #if defined(DP83820) 2135 sc->sc_txcfg = TXCFG_MXDMA_512; 2136 sc->sc_rxcfg = RXCFG_MXDMA_512; 2137 #else 2138 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2139 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2140 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2141 sc->sc_txcfg = TXCFG_MXDMA_64; 2142 sc->sc_rxcfg = RXCFG_MXDMA_64; 2143 } else { 2144 sc->sc_txcfg = TXCFG_MXDMA_512; 2145 sc->sc_rxcfg = RXCFG_MXDMA_512; 2146 } 2147 #endif /* DP83820 */ 2148 2149 sc->sc_txcfg |= TXCFG_ATP | 2150 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2151 sc->sc_tx_drain_thresh; 2152 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2153 2154 /* 2155 * Initialize the receive drain threshold if we have never 2156 * done so. 2157 */ 2158 if (sc->sc_rx_drain_thresh == 0) { 2159 /* 2160 * XXX This value should be tuned. This is set to the 2161 * maximum of 248 bytes, and we may be able to improve 2162 * performance by decreasing it (although we should never 2163 * set this value lower than 2; 14 bytes are required to 2164 * filter the packet). 2165 */ 2166 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2167 } 2168 2169 /* 2170 * Initialize the prototype RXCFG register. 2171 */ 2172 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2173 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2174 2175 #ifdef DP83820 2176 /* 2177 * Initialize the VLAN/IP receive control register. 2178 * We enable checksum computation on all incoming 2179 * packets, and do not reject packets w/ bad checksums. 2180 */ 2181 reg = 0; 2182 if (ifp->if_capenable & 2183 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2184 reg |= VRCR_IPEN; 2185 if (sc->sc_ethercom.ec_nvlans != 0) 2186 reg |= VRCR_VTDEN|VRCR_VTREN; 2187 bus_space_write_4(st, sh, SIP_VRCR, reg); 2188 2189 /* 2190 * Initialize the VLAN/IP transmit control register. 2191 * We enable outgoing checksum computation on a 2192 * per-packet basis. 2193 */ 2194 reg = 0; 2195 if (ifp->if_capenable & 2196 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2197 reg |= VTCR_PPCHK; 2198 if (sc->sc_ethercom.ec_nvlans != 0) 2199 reg |= VTCR_VPPTI; 2200 bus_space_write_4(st, sh, SIP_VTCR, reg); 2201 2202 /* 2203 * If we're using VLANs, initialize the VLAN data register. 2204 * To understand why we bswap the VLAN Ethertype, see section 2205 * 4.2.36 of the DP83820 manual. 2206 */ 2207 if (sc->sc_ethercom.ec_nvlans != 0) 2208 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2209 #endif /* DP83820 */ 2210 2211 /* 2212 * Give the transmit and receive rings to the chip. 2213 */ 2214 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2215 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2216 2217 /* 2218 * Initialize the interrupt mask. 2219 */ 2220 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2221 ISR_TXURN|ISR_TXDESC|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2222 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2223 2224 /* Set up the receive filter. */ 2225 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2226 2227 /* 2228 * Set the current media. Do this after initializing the prototype 2229 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2230 * control. 2231 */ 2232 mii_mediachg(&sc->sc_mii); 2233 2234 /* 2235 * Enable interrupts. 2236 */ 2237 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2238 2239 /* 2240 * Start the transmit and receive processes. 2241 */ 2242 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2243 2244 /* 2245 * Start the one second MII clock. 2246 */ 2247 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2248 2249 /* 2250 * ...all done! 2251 */ 2252 ifp->if_flags |= IFF_RUNNING; 2253 ifp->if_flags &= ~IFF_OACTIVE; 2254 2255 out: 2256 if (error) 2257 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2258 return (error); 2259 } 2260 2261 /* 2262 * sip_drain: 2263 * 2264 * Drain the receive queue. 2265 */ 2266 void 2267 SIP_DECL(rxdrain)(struct sip_softc *sc) 2268 { 2269 struct sip_rxsoft *rxs; 2270 int i; 2271 2272 for (i = 0; i < SIP_NRXDESC; i++) { 2273 rxs = &sc->sc_rxsoft[i]; 2274 if (rxs->rxs_mbuf != NULL) { 2275 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2276 m_freem(rxs->rxs_mbuf); 2277 rxs->rxs_mbuf = NULL; 2278 } 2279 } 2280 } 2281 2282 /* 2283 * sip_stop: [ ifnet interface function ] 2284 * 2285 * Stop transmission on the interface. 2286 */ 2287 void 2288 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2289 { 2290 struct sip_softc *sc = ifp->if_softc; 2291 bus_space_tag_t st = sc->sc_st; 2292 bus_space_handle_t sh = sc->sc_sh; 2293 struct sip_txsoft *txs; 2294 u_int32_t cmdsts = 0; /* DEBUG */ 2295 2296 /* 2297 * Stop the one second clock. 2298 */ 2299 callout_stop(&sc->sc_tick_ch); 2300 2301 /* Down the MII. */ 2302 mii_down(&sc->sc_mii); 2303 2304 /* 2305 * Disable interrupts. 2306 */ 2307 bus_space_write_4(st, sh, SIP_IER, 0); 2308 2309 /* 2310 * Stop receiver and transmitter. 2311 */ 2312 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2313 2314 /* 2315 * Release any queued transmit buffers. 2316 */ 2317 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2318 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2319 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2320 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2321 CMDSTS_INTR) == 0) 2322 printf("%s: sip_stop: last descriptor does not " 2323 "have INTR bit set\n", sc->sc_dev.dv_xname); 2324 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 2325 #ifdef DIAGNOSTIC 2326 if (txs->txs_mbuf == NULL) { 2327 printf("%s: dirty txsoft with no mbuf chain\n", 2328 sc->sc_dev.dv_xname); 2329 panic("sip_stop"); 2330 } 2331 #endif 2332 cmdsts |= /* DEBUG */ 2333 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2334 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2335 m_freem(txs->txs_mbuf); 2336 txs->txs_mbuf = NULL; 2337 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2338 } 2339 2340 if (disable) 2341 SIP_DECL(rxdrain)(sc); 2342 2343 /* 2344 * Mark the interface down and cancel the watchdog timer. 2345 */ 2346 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2347 ifp->if_timer = 0; 2348 2349 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2350 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2351 printf("%s: sip_stop: no INTR bits set in dirty tx " 2352 "descriptors\n", sc->sc_dev.dv_xname); 2353 } 2354 2355 /* 2356 * sip_read_eeprom: 2357 * 2358 * Read data from the serial EEPROM. 2359 */ 2360 void 2361 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2362 u_int16_t *data) 2363 { 2364 bus_space_tag_t st = sc->sc_st; 2365 bus_space_handle_t sh = sc->sc_sh; 2366 u_int16_t reg; 2367 int i, x; 2368 2369 for (i = 0; i < wordcnt; i++) { 2370 /* Send CHIP SELECT. */ 2371 reg = EROMAR_EECS; 2372 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2373 2374 /* Shift in the READ opcode. */ 2375 for (x = 3; x > 0; x--) { 2376 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2377 reg |= EROMAR_EEDI; 2378 else 2379 reg &= ~EROMAR_EEDI; 2380 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2381 bus_space_write_4(st, sh, SIP_EROMAR, 2382 reg | EROMAR_EESK); 2383 delay(4); 2384 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2385 delay(4); 2386 } 2387 2388 /* Shift in address. */ 2389 for (x = 6; x > 0; x--) { 2390 if ((word + i) & (1 << (x - 1))) 2391 reg |= EROMAR_EEDI; 2392 else 2393 reg &= ~EROMAR_EEDI; 2394 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2395 bus_space_write_4(st, sh, SIP_EROMAR, 2396 reg | EROMAR_EESK); 2397 delay(4); 2398 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2399 delay(4); 2400 } 2401 2402 /* Shift out data. */ 2403 reg = EROMAR_EECS; 2404 data[i] = 0; 2405 for (x = 16; x > 0; x--) { 2406 bus_space_write_4(st, sh, SIP_EROMAR, 2407 reg | EROMAR_EESK); 2408 delay(4); 2409 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2410 data[i] |= (1 << (x - 1)); 2411 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2412 delay(4); 2413 } 2414 2415 /* Clear CHIP SELECT. */ 2416 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2417 delay(4); 2418 } 2419 } 2420 2421 /* 2422 * sip_add_rxbuf: 2423 * 2424 * Add a receive buffer to the indicated descriptor. 2425 */ 2426 int 2427 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2428 { 2429 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2430 struct mbuf *m; 2431 int error; 2432 2433 MGETHDR(m, M_DONTWAIT, MT_DATA); 2434 if (m == NULL) 2435 return (ENOBUFS); 2436 2437 MCLGET(m, M_DONTWAIT); 2438 if ((m->m_flags & M_EXT) == 0) { 2439 m_freem(m); 2440 return (ENOBUFS); 2441 } 2442 2443 #if defined(DP83820) 2444 m->m_len = SIP_RXBUF_LEN; 2445 #endif /* DP83820 */ 2446 2447 if (rxs->rxs_mbuf != NULL) 2448 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2449 2450 rxs->rxs_mbuf = m; 2451 2452 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2453 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2454 BUS_DMA_READ|BUS_DMA_NOWAIT); 2455 if (error) { 2456 printf("%s: can't load rx DMA map %d, error = %d\n", 2457 sc->sc_dev.dv_xname, idx, error); 2458 panic("sip_add_rxbuf"); /* XXX */ 2459 } 2460 2461 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2462 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2463 2464 SIP_INIT_RXDESC(sc, idx); 2465 2466 return (0); 2467 } 2468 2469 #if !defined(DP83820) 2470 /* 2471 * sip_sis900_set_filter: 2472 * 2473 * Set up the receive filter. 2474 */ 2475 void 2476 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2477 { 2478 bus_space_tag_t st = sc->sc_st; 2479 bus_space_handle_t sh = sc->sc_sh; 2480 struct ethercom *ec = &sc->sc_ethercom; 2481 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2482 struct ether_multi *enm; 2483 u_int8_t *cp; 2484 struct ether_multistep step; 2485 u_int32_t crc, mchash[16]; 2486 2487 /* 2488 * Initialize the prototype RFCR. 2489 */ 2490 sc->sc_rfcr = RFCR_RFEN; 2491 if (ifp->if_flags & IFF_BROADCAST) 2492 sc->sc_rfcr |= RFCR_AAB; 2493 if (ifp->if_flags & IFF_PROMISC) { 2494 sc->sc_rfcr |= RFCR_AAP; 2495 goto allmulti; 2496 } 2497 2498 /* 2499 * Set up the multicast address filter by passing all multicast 2500 * addresses through a CRC generator, and then using the high-order 2501 * 6 bits as an index into the 128 bit multicast hash table (only 2502 * the lower 16 bits of each 32 bit multicast hash register are 2503 * valid). The high order bits select the register, while the 2504 * rest of the bits select the bit within the register. 2505 */ 2506 2507 memset(mchash, 0, sizeof(mchash)); 2508 2509 ETHER_FIRST_MULTI(step, ec, enm); 2510 while (enm != NULL) { 2511 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2512 /* 2513 * We must listen to a range of multicast addresses. 2514 * For now, just accept all multicasts, rather than 2515 * trying to set only those filter bits needed to match 2516 * the range. (At this time, the only use of address 2517 * ranges is for IP multicast routing, for which the 2518 * range is big enough to require all bits set.) 2519 */ 2520 goto allmulti; 2521 } 2522 2523 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2524 2525 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2526 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2527 /* Just want the 8 most significant bits. */ 2528 crc >>= 24; 2529 } else { 2530 /* Just want the 7 most significant bits. */ 2531 crc >>= 25; 2532 } 2533 2534 /* Set the corresponding bit in the hash table. */ 2535 mchash[crc >> 4] |= 1 << (crc & 0xf); 2536 2537 ETHER_NEXT_MULTI(step, enm); 2538 } 2539 2540 ifp->if_flags &= ~IFF_ALLMULTI; 2541 goto setit; 2542 2543 allmulti: 2544 ifp->if_flags |= IFF_ALLMULTI; 2545 sc->sc_rfcr |= RFCR_AAM; 2546 2547 setit: 2548 #define FILTER_EMIT(addr, data) \ 2549 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2550 delay(1); \ 2551 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2552 delay(1) 2553 2554 /* 2555 * Disable receive filter, and program the node address. 2556 */ 2557 cp = LLADDR(ifp->if_sadl); 2558 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2559 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2560 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2561 2562 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2563 /* 2564 * Program the multicast hash table. 2565 */ 2566 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2567 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2568 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2569 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2570 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2571 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2572 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2573 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2574 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2575 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2576 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2577 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2578 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2579 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2580 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2581 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2582 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2583 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2584 } 2585 } 2586 #undef FILTER_EMIT 2587 2588 /* 2589 * Re-enable the receiver filter. 2590 */ 2591 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2592 } 2593 #endif /* ! DP83820 */ 2594 2595 /* 2596 * sip_dp83815_set_filter: 2597 * 2598 * Set up the receive filter. 2599 */ 2600 void 2601 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2602 { 2603 bus_space_tag_t st = sc->sc_st; 2604 bus_space_handle_t sh = sc->sc_sh; 2605 struct ethercom *ec = &sc->sc_ethercom; 2606 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2607 struct ether_multi *enm; 2608 u_int8_t *cp; 2609 struct ether_multistep step; 2610 u_int32_t crc, hash, slot, bit; 2611 #ifdef DP83820 2612 #define MCHASH_NWORDS 128 2613 #else 2614 #define MCHASH_NWORDS 32 2615 #endif /* DP83820 */ 2616 u_int16_t mchash[MCHASH_NWORDS]; 2617 int i; 2618 2619 /* 2620 * Initialize the prototype RFCR. 2621 * Enable the receive filter, and accept on 2622 * Perfect (destination address) Match 2623 * If IFF_BROADCAST, also accept all broadcast packets. 2624 * If IFF_PROMISC, accept all unicast packets (and later, set 2625 * IFF_ALLMULTI and accept all multicast, too). 2626 */ 2627 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2628 if (ifp->if_flags & IFF_BROADCAST) 2629 sc->sc_rfcr |= RFCR_AAB; 2630 if (ifp->if_flags & IFF_PROMISC) { 2631 sc->sc_rfcr |= RFCR_AAP; 2632 goto allmulti; 2633 } 2634 2635 #ifdef DP83820 2636 /* 2637 * Set up the DP83820 multicast address filter by passing all multicast 2638 * addresses through a CRC generator, and then using the high-order 2639 * 11 bits as an index into the 2048 bit multicast hash table. The 2640 * high-order 7 bits select the slot, while the low-order 4 bits 2641 * select the bit within the slot. Note that only the low 16-bits 2642 * of each filter word are used, and there are 128 filter words. 2643 */ 2644 #else 2645 /* 2646 * Set up the DP83815 multicast address filter by passing all multicast 2647 * addresses through a CRC generator, and then using the high-order 2648 * 9 bits as an index into the 512 bit multicast hash table. The 2649 * high-order 5 bits select the slot, while the low-order 4 bits 2650 * select the bit within the slot. Note that only the low 16-bits 2651 * of each filter word are used, and there are 32 filter words. 2652 */ 2653 #endif /* DP83820 */ 2654 2655 memset(mchash, 0, sizeof(mchash)); 2656 2657 ifp->if_flags &= ~IFF_ALLMULTI; 2658 ETHER_FIRST_MULTI(step, ec, enm); 2659 if (enm == NULL) 2660 goto setit; 2661 while (enm != NULL) { 2662 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2663 /* 2664 * We must listen to a range of multicast addresses. 2665 * For now, just accept all multicasts, rather than 2666 * trying to set only those filter bits needed to match 2667 * the range. (At this time, the only use of address 2668 * ranges is for IP multicast routing, for which the 2669 * range is big enough to require all bits set.) 2670 */ 2671 goto allmulti; 2672 } 2673 2674 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2675 2676 #ifdef DP83820 2677 /* Just want the 11 most significant bits. */ 2678 hash = crc >> 21; 2679 #else 2680 /* Just want the 9 most significant bits. */ 2681 hash = crc >> 23; 2682 #endif /* DP83820 */ 2683 2684 slot = hash >> 4; 2685 bit = hash & 0xf; 2686 2687 /* Set the corresponding bit in the hash table. */ 2688 mchash[slot] |= 1 << bit; 2689 2690 ETHER_NEXT_MULTI(step, enm); 2691 } 2692 sc->sc_rfcr |= RFCR_MHEN; 2693 goto setit; 2694 2695 allmulti: 2696 ifp->if_flags |= IFF_ALLMULTI; 2697 sc->sc_rfcr |= RFCR_AAM; 2698 2699 setit: 2700 #define FILTER_EMIT(addr, data) \ 2701 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2702 delay(1); \ 2703 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2704 delay(1) 2705 2706 /* 2707 * Disable receive filter, and program the node address. 2708 */ 2709 cp = LLADDR(ifp->if_sadl); 2710 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2711 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2712 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2713 2714 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2715 /* 2716 * Program the multicast hash table. 2717 */ 2718 for (i = 0; i < MCHASH_NWORDS; i++) { 2719 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2720 mchash[i]); 2721 } 2722 } 2723 #undef FILTER_EMIT 2724 #undef MCHASH_NWORDS 2725 2726 /* 2727 * Re-enable the receiver filter. 2728 */ 2729 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2730 } 2731 2732 #if defined(DP83820) 2733 /* 2734 * sip_dp83820_mii_readreg: [mii interface function] 2735 * 2736 * Read a PHY register on the MII of the DP83820. 2737 */ 2738 int 2739 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2740 { 2741 2742 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2743 phy, reg)); 2744 } 2745 2746 /* 2747 * sip_dp83820_mii_writereg: [mii interface function] 2748 * 2749 * Write a PHY register on the MII of the DP83820. 2750 */ 2751 void 2752 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2753 { 2754 2755 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2756 phy, reg, val); 2757 } 2758 2759 /* 2760 * sip_dp83815_mii_statchg: [mii interface function] 2761 * 2762 * Callback from MII layer when media changes. 2763 */ 2764 void 2765 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2766 { 2767 struct sip_softc *sc = (struct sip_softc *) self; 2768 u_int32_t cfg; 2769 2770 /* 2771 * Update TXCFG for full-duplex operation. 2772 */ 2773 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2774 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2775 else 2776 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2777 2778 /* 2779 * Update RXCFG for full-duplex or loopback. 2780 */ 2781 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2782 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2783 sc->sc_rxcfg |= RXCFG_ATX; 2784 else 2785 sc->sc_rxcfg &= ~RXCFG_ATX; 2786 2787 /* 2788 * Update CFG for MII/GMII. 2789 */ 2790 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2791 cfg = sc->sc_cfg | CFG_MODE_1000; 2792 else 2793 cfg = sc->sc_cfg; 2794 2795 /* 2796 * XXX 802.3x flow control. 2797 */ 2798 2799 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2800 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2801 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2802 } 2803 2804 /* 2805 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 2806 * 2807 * Read the MII serial port for the MII bit-bang module. 2808 */ 2809 u_int32_t 2810 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 2811 { 2812 struct sip_softc *sc = (void *) self; 2813 2814 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 2815 } 2816 2817 /* 2818 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 2819 * 2820 * Write the MII serial port for the MII bit-bang module. 2821 */ 2822 void 2823 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 2824 { 2825 struct sip_softc *sc = (void *) self; 2826 2827 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 2828 } 2829 #else /* ! DP83820 */ 2830 /* 2831 * sip_sis900_mii_readreg: [mii interface function] 2832 * 2833 * Read a PHY register on the MII. 2834 */ 2835 int 2836 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 2837 { 2838 struct sip_softc *sc = (struct sip_softc *) self; 2839 u_int32_t enphy; 2840 2841 /* 2842 * The SiS 900 has only an internal PHY on the MII. Only allow 2843 * MII address 0. 2844 */ 2845 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2846 sc->sc_rev < SIS_REV_635 && phy != 0) 2847 return (0); 2848 2849 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2850 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 2851 ENPHY_RWCMD | ENPHY_ACCESS); 2852 do { 2853 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2854 } while (enphy & ENPHY_ACCESS); 2855 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 2856 } 2857 2858 /* 2859 * sip_sis900_mii_writereg: [mii interface function] 2860 * 2861 * Write a PHY register on the MII. 2862 */ 2863 void 2864 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 2865 { 2866 struct sip_softc *sc = (struct sip_softc *) self; 2867 u_int32_t enphy; 2868 2869 /* 2870 * The SiS 900 has only an internal PHY on the MII. Only allow 2871 * MII address 0. 2872 */ 2873 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2874 sc->sc_rev < SIS_REV_635 && phy != 0) 2875 return; 2876 2877 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2878 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 2879 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 2880 do { 2881 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2882 } while (enphy & ENPHY_ACCESS); 2883 } 2884 2885 /* 2886 * sip_sis900_mii_statchg: [mii interface function] 2887 * 2888 * Callback from MII layer when media changes. 2889 */ 2890 void 2891 SIP_DECL(sis900_mii_statchg)(struct device *self) 2892 { 2893 struct sip_softc *sc = (struct sip_softc *) self; 2894 u_int32_t flowctl; 2895 2896 /* 2897 * Update TXCFG for full-duplex operation. 2898 */ 2899 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2900 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2901 else 2902 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2903 2904 /* 2905 * Update RXCFG for full-duplex or loopback. 2906 */ 2907 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2908 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2909 sc->sc_rxcfg |= RXCFG_ATX; 2910 else 2911 sc->sc_rxcfg &= ~RXCFG_ATX; 2912 2913 /* 2914 * Update IMR for use of 802.3x flow control. 2915 */ 2916 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 2917 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 2918 flowctl = FLOWCTL_FLOWEN; 2919 } else { 2920 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 2921 flowctl = 0; 2922 } 2923 2924 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2925 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2926 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 2927 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 2928 } 2929 2930 /* 2931 * sip_dp83815_mii_readreg: [mii interface function] 2932 * 2933 * Read a PHY register on the MII. 2934 */ 2935 int 2936 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 2937 { 2938 struct sip_softc *sc = (struct sip_softc *) self; 2939 u_int32_t val; 2940 2941 /* 2942 * The DP83815 only has an internal PHY. Only allow 2943 * MII address 0. 2944 */ 2945 if (phy != 0) 2946 return (0); 2947 2948 /* 2949 * Apparently, after a reset, the DP83815 can take a while 2950 * to respond. During this recovery period, the BMSR returns 2951 * a value of 0. Catch this -- it's not supposed to happen 2952 * (the BMSR has some hardcoded-to-1 bits), and wait for the 2953 * PHY to come back to life. 2954 * 2955 * This works out because the BMSR is the first register 2956 * read during the PHY probe process. 2957 */ 2958 do { 2959 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 2960 } while (reg == MII_BMSR && val == 0); 2961 2962 return (val & 0xffff); 2963 } 2964 2965 /* 2966 * sip_dp83815_mii_writereg: [mii interface function] 2967 * 2968 * Write a PHY register to the MII. 2969 */ 2970 void 2971 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 2972 { 2973 struct sip_softc *sc = (struct sip_softc *) self; 2974 2975 /* 2976 * The DP83815 only has an internal PHY. Only allow 2977 * MII address 0. 2978 */ 2979 if (phy != 0) 2980 return; 2981 2982 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 2983 } 2984 2985 /* 2986 * sip_dp83815_mii_statchg: [mii interface function] 2987 * 2988 * Callback from MII layer when media changes. 2989 */ 2990 void 2991 SIP_DECL(dp83815_mii_statchg)(struct device *self) 2992 { 2993 struct sip_softc *sc = (struct sip_softc *) self; 2994 2995 /* 2996 * Update TXCFG for full-duplex operation. 2997 */ 2998 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2999 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3000 else 3001 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3002 3003 /* 3004 * Update RXCFG for full-duplex or loopback. 3005 */ 3006 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3007 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3008 sc->sc_rxcfg |= RXCFG_ATX; 3009 else 3010 sc->sc_rxcfg &= ~RXCFG_ATX; 3011 3012 /* 3013 * XXX 802.3x flow control. 3014 */ 3015 3016 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3017 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3018 } 3019 #endif /* DP83820 */ 3020 3021 #if defined(DP83820) 3022 void 3023 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3024 const struct pci_attach_args *pa, u_int8_t *enaddr) 3025 { 3026 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3027 u_int8_t cksum, *e, match; 3028 int i; 3029 3030 /* 3031 * EEPROM data format for the DP83820 can be found in 3032 * the DP83820 manual, section 4.2.4. 3033 */ 3034 3035 SIP_DECL(read_eeprom)(sc, 0, 3036 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3037 3038 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3039 match = ~(match - 1); 3040 3041 cksum = 0x55; 3042 e = (u_int8_t *) eeprom_data; 3043 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3044 cksum += *e++; 3045 3046 if (cksum != match) 3047 printf("%s: Checksum (%x) mismatch (%x)", 3048 sc->sc_dev.dv_xname, cksum, match); 3049 3050 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3051 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3052 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3053 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3054 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3055 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3056 3057 /* Get the GPIOR bits. */ 3058 sc->sc_gpior = eeprom_data[0x04]; 3059 3060 /* Get various CFG related bits. */ 3061 if ((eeprom_data[0x05] >> 0) & 1) 3062 sc->sc_cfg |= CFG_EXT_125; 3063 if ((eeprom_data[0x05] >> 9) & 1) 3064 sc->sc_cfg |= CFG_TBI_EN; 3065 } 3066 #else /* ! DP83820 */ 3067 void 3068 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3069 const struct pci_attach_args *pa, u_int8_t *enaddr) 3070 { 3071 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3072 3073 switch (sc->sc_rev) { 3074 case SIS_REV_630S: 3075 case SIS_REV_630E: 3076 case SIS_REV_630EA1: 3077 case SIS_REV_630ET: 3078 case SIS_REV_635: 3079 /* 3080 * The MAC address for the on-board Ethernet of 3081 * the SiS 630 chipset is in the NVRAM. Kick 3082 * the chip into re-loading it from NVRAM, and 3083 * read the MAC address out of the filter registers. 3084 */ 3085 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3086 3087 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3088 RFCR_RFADDR_NODE0); 3089 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3090 0xffff; 3091 3092 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3093 RFCR_RFADDR_NODE2); 3094 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3095 0xffff; 3096 3097 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3098 RFCR_RFADDR_NODE4); 3099 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3100 0xffff; 3101 break; 3102 3103 default: 3104 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3105 sizeof(myea) / sizeof(myea[0]), myea); 3106 } 3107 3108 enaddr[0] = myea[0] & 0xff; 3109 enaddr[1] = myea[0] >> 8; 3110 enaddr[2] = myea[1] & 0xff; 3111 enaddr[3] = myea[1] >> 8; 3112 enaddr[4] = myea[2] & 0xff; 3113 enaddr[5] = myea[2] >> 8; 3114 } 3115 3116 /* Table and macro to bit-reverse an octet. */ 3117 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3118 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3119 3120 void 3121 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3122 const struct pci_attach_args *pa, u_int8_t *enaddr) 3123 { 3124 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3125 u_int8_t cksum, *e, match; 3126 int i; 3127 3128 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3129 sizeof(eeprom_data[0]), eeprom_data); 3130 3131 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3132 match = ~(match - 1); 3133 3134 cksum = 0x55; 3135 e = (u_int8_t *) eeprom_data; 3136 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3137 cksum += *e++; 3138 } 3139 if (cksum != match) { 3140 printf("%s: Checksum (%x) mismatch (%x)", 3141 sc->sc_dev.dv_xname, cksum, match); 3142 } 3143 3144 /* 3145 * Unrolled because it makes slightly more sense this way. 3146 * The DP83815 stores the MAC address in bit 0 of word 6 3147 * through bit 15 of word 8. 3148 */ 3149 ea = &eeprom_data[6]; 3150 enaddr[0] = ((*ea & 0x1) << 7); 3151 ea++; 3152 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3153 enaddr[1] = ((*ea & 0x1FE) >> 1); 3154 enaddr[2] = ((*ea & 0x1) << 7); 3155 ea++; 3156 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3157 enaddr[3] = ((*ea & 0x1FE) >> 1); 3158 enaddr[4] = ((*ea & 0x1) << 7); 3159 ea++; 3160 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3161 enaddr[5] = ((*ea & 0x1FE) >> 1); 3162 3163 /* 3164 * In case that's not weird enough, we also need to reverse 3165 * the bits in each byte. This all actually makes more sense 3166 * if you think about the EEPROM storage as an array of bits 3167 * being shifted into bytes, but that's not how we're looking 3168 * at it here... 3169 */ 3170 for (i = 0; i < 6 ;i++) 3171 enaddr[i] = bbr(enaddr[i]); 3172 } 3173 #endif /* DP83820 */ 3174 3175 /* 3176 * sip_mediastatus: [ifmedia interface function] 3177 * 3178 * Get the current interface media status. 3179 */ 3180 void 3181 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3182 { 3183 struct sip_softc *sc = ifp->if_softc; 3184 3185 mii_pollstat(&sc->sc_mii); 3186 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3187 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3188 } 3189 3190 /* 3191 * sip_mediachange: [ifmedia interface function] 3192 * 3193 * Set hardware to newly-selected media. 3194 */ 3195 int 3196 SIP_DECL(mediachange)(struct ifnet *ifp) 3197 { 3198 struct sip_softc *sc = ifp->if_softc; 3199 3200 if (ifp->if_flags & IFF_UP) 3201 mii_mediachg(&sc->sc_mii); 3202 return (0); 3203 } 3204