1 /* $NetBSD: if_ste.c,v 1.42 2010/11/13 13:52:07 uebayasi Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. ST-201 10/100 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_ste.c,v 1.42 2010/11/13 13:52:07 uebayasi Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/queue.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/mii_bitbang.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_stereg.h> 72 73 /* 74 * Transmit descriptor list size. 75 */ 76 #define STE_NTXDESC 256 77 #define STE_NTXDESC_MASK (STE_NTXDESC - 1) 78 #define STE_NEXTTX(x) (((x) + 1) & STE_NTXDESC_MASK) 79 80 /* 81 * Receive descriptor list size. 82 */ 83 #define STE_NRXDESC 128 84 #define STE_NRXDESC_MASK (STE_NRXDESC - 1) 85 #define STE_NEXTRX(x) (((x) + 1) & STE_NRXDESC_MASK) 86 87 /* 88 * Control structures are DMA'd to the ST-201 chip. We allocate them in 89 * a single clump that maps to a single DMA segment to make several things 90 * easier. 91 */ 92 struct ste_control_data { 93 /* 94 * The transmit descriptors. 95 */ 96 struct ste_tfd scd_txdescs[STE_NTXDESC]; 97 98 /* 99 * The receive descriptors. 100 */ 101 struct ste_rfd scd_rxdescs[STE_NRXDESC]; 102 }; 103 104 #define STE_CDOFF(x) offsetof(struct ste_control_data, x) 105 #define STE_CDTXOFF(x) STE_CDOFF(scd_txdescs[(x)]) 106 #define STE_CDRXOFF(x) STE_CDOFF(scd_rxdescs[(x)]) 107 108 /* 109 * Software state for transmit and receive jobs. 110 */ 111 struct ste_descsoft { 112 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 113 bus_dmamap_t ds_dmamap; /* our DMA map */ 114 }; 115 116 /* 117 * Software state per device. 118 */ 119 struct ste_softc { 120 struct device sc_dev; /* generic device information */ 121 bus_space_tag_t sc_st; /* bus space tag */ 122 bus_space_handle_t sc_sh; /* bus space handle */ 123 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 124 struct ethercom sc_ethercom; /* ethernet common data */ 125 126 void *sc_ih; /* interrupt cookie */ 127 128 struct mii_data sc_mii; /* MII/media information */ 129 130 callout_t sc_tick_ch; /* tick callout */ 131 132 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 133 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 134 135 /* 136 * Software state for transmit and receive descriptors. 137 */ 138 struct ste_descsoft sc_txsoft[STE_NTXDESC]; 139 struct ste_descsoft sc_rxsoft[STE_NRXDESC]; 140 141 /* 142 * Control data structures. 143 */ 144 struct ste_control_data *sc_control_data; 145 #define sc_txdescs sc_control_data->scd_txdescs 146 #define sc_rxdescs sc_control_data->scd_rxdescs 147 148 int sc_txpending; /* number of Tx requests pending */ 149 int sc_txdirty; /* first dirty Tx descriptor */ 150 int sc_txlast; /* last used Tx descriptor */ 151 152 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 153 154 int sc_txthresh; /* Tx threshold */ 155 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 156 uint16_t sc_IntEnable; /* prototype IntEnable register */ 157 uint16_t sc_MacCtrl0; /* prototype MacCtrl0 register */ 158 uint8_t sc_ReceiveMode; /* prototype ReceiveMode register */ 159 }; 160 161 #define STE_CDTXADDR(sc, x) ((sc)->sc_cddma + STE_CDTXOFF((x))) 162 #define STE_CDRXADDR(sc, x) ((sc)->sc_cddma + STE_CDRXOFF((x))) 163 164 #define STE_CDTXSYNC(sc, x, ops) \ 165 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 166 STE_CDTXOFF((x)), sizeof(struct ste_tfd), (ops)) 167 168 #define STE_CDRXSYNC(sc, x, ops) \ 169 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 170 STE_CDRXOFF((x)), sizeof(struct ste_rfd), (ops)) 171 172 #define STE_INIT_RXDESC(sc, x) \ 173 do { \ 174 struct ste_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 175 struct ste_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 176 struct mbuf *__m = __ds->ds_mbuf; \ 177 \ 178 /* \ 179 * Note: We scoot the packet forward 2 bytes in the buffer \ 180 * so that the payload after the Ethernet header is aligned \ 181 * to a 4-byte boundary. \ 182 */ \ 183 __m->m_data = __m->m_ext.ext_buf + 2; \ 184 __rfd->rfd_frag.frag_addr = \ 185 htole32(__ds->ds_dmamap->dm_segs[0].ds_addr + 2); \ 186 __rfd->rfd_frag.frag_len = htole32((MCLBYTES - 2) | FRAG_LAST); \ 187 __rfd->rfd_next = htole32(STE_CDRXADDR((sc), STE_NEXTRX((x)))); \ 188 __rfd->rfd_status = 0; \ 189 STE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 190 } while (/*CONSTCOND*/0) 191 192 #define STE_TIMEOUT 1000 193 194 static void ste_start(struct ifnet *); 195 static void ste_watchdog(struct ifnet *); 196 static int ste_ioctl(struct ifnet *, u_long, void *); 197 static int ste_init(struct ifnet *); 198 static void ste_stop(struct ifnet *, int); 199 200 static bool ste_shutdown(device_t, int); 201 202 static void ste_reset(struct ste_softc *, u_int32_t); 203 static void ste_setthresh(struct ste_softc *); 204 static void ste_txrestart(struct ste_softc *, u_int8_t); 205 static void ste_rxdrain(struct ste_softc *); 206 static int ste_add_rxbuf(struct ste_softc *, int); 207 static void ste_read_eeprom(struct ste_softc *, int, uint16_t *); 208 static void ste_tick(void *); 209 210 static void ste_stats_update(struct ste_softc *); 211 212 static void ste_set_filter(struct ste_softc *); 213 214 static int ste_intr(void *); 215 static void ste_txintr(struct ste_softc *); 216 static void ste_rxintr(struct ste_softc *); 217 218 static int ste_mii_readreg(device_t, int, int); 219 static void ste_mii_writereg(device_t, int, int, int); 220 static void ste_mii_statchg(device_t); 221 222 static int ste_match(device_t, cfdata_t, void *); 223 static void ste_attach(device_t, device_t, void *); 224 225 int ste_copy_small = 0; 226 227 CFATTACH_DECL(ste, sizeof(struct ste_softc), 228 ste_match, ste_attach, NULL, NULL); 229 230 static uint32_t ste_mii_bitbang_read(device_t); 231 static void ste_mii_bitbang_write(device_t, uint32_t); 232 233 static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 234 ste_mii_bitbang_read, 235 ste_mii_bitbang_write, 236 { 237 PC_MgmtData, /* MII_BIT_MDO */ 238 PC_MgmtData, /* MII_BIT_MDI */ 239 PC_MgmtClk, /* MII_BIT_MDC */ 240 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 241 0, /* MII_BIT_DIR_PHY_HOST */ 242 } 243 }; 244 245 /* 246 * Devices supported by this driver. 247 */ 248 static const struct ste_product { 249 pci_vendor_id_t ste_vendor; 250 pci_product_id_t ste_product; 251 const char *ste_name; 252 } ste_products[] = { 253 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_IP100A, 254 "IC Plus Corp. IP00A 10/100 Fast Ethernet Adapter" }, 255 256 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 257 "Sundance ST-201 10/100 Ethernet" }, 258 259 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 260 "D-Link DL-1002 10/100 Ethernet" }, 261 262 { 0, 0, 263 NULL }, 264 }; 265 266 static const struct ste_product * 267 ste_lookup(const struct pci_attach_args *pa) 268 { 269 const struct ste_product *sp; 270 271 for (sp = ste_products; sp->ste_name != NULL; sp++) { 272 if (PCI_VENDOR(pa->pa_id) == sp->ste_vendor && 273 PCI_PRODUCT(pa->pa_id) == sp->ste_product) 274 return (sp); 275 } 276 return (NULL); 277 } 278 279 static int 280 ste_match(device_t parent, cfdata_t cf, void *aux) 281 { 282 struct pci_attach_args *pa = aux; 283 284 if (ste_lookup(pa) != NULL) 285 return (1); 286 287 return (0); 288 } 289 290 static void 291 ste_attach(device_t parent, device_t self, void *aux) 292 { 293 struct ste_softc *sc = device_private(self); 294 struct pci_attach_args *pa = aux; 295 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 296 pci_chipset_tag_t pc = pa->pa_pc; 297 pci_intr_handle_t ih; 298 const char *intrstr = NULL; 299 bus_space_tag_t iot, memt; 300 bus_space_handle_t ioh, memh; 301 bus_dma_segment_t seg; 302 int ioh_valid, memh_valid; 303 int i, rseg, error; 304 const struct ste_product *sp; 305 uint8_t enaddr[ETHER_ADDR_LEN]; 306 uint16_t myea[ETHER_ADDR_LEN / 2]; 307 308 callout_init(&sc->sc_tick_ch, 0); 309 310 sp = ste_lookup(pa); 311 if (sp == NULL) { 312 printf("\n"); 313 panic("ste_attach: impossible"); 314 } 315 316 printf(": %s\n", sp->ste_name); 317 318 /* 319 * Map the device. 320 */ 321 ioh_valid = (pci_mapreg_map(pa, STE_PCI_IOBA, 322 PCI_MAPREG_TYPE_IO, 0, 323 &iot, &ioh, NULL, NULL) == 0); 324 memh_valid = (pci_mapreg_map(pa, STE_PCI_MMBA, 325 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 326 &memt, &memh, NULL, NULL) == 0); 327 328 if (memh_valid) { 329 sc->sc_st = memt; 330 sc->sc_sh = memh; 331 } else if (ioh_valid) { 332 sc->sc_st = iot; 333 sc->sc_sh = ioh; 334 } else { 335 aprint_error_dev(&sc->sc_dev, "unable to map device registers\n"); 336 return; 337 } 338 339 sc->sc_dmat = pa->pa_dmat; 340 341 /* Enable bus mastering. */ 342 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 343 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 344 PCI_COMMAND_MASTER_ENABLE); 345 346 /* power up chip */ 347 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 348 NULL)) && error != EOPNOTSUPP) { 349 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", 350 error); 351 return; 352 } 353 354 /* 355 * Map and establish our interrupt. 356 */ 357 if (pci_intr_map(pa, &ih)) { 358 aprint_error_dev(&sc->sc_dev, "unable to map interrupt\n"); 359 return; 360 } 361 intrstr = pci_intr_string(pc, ih); 362 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ste_intr, sc); 363 if (sc->sc_ih == NULL) { 364 aprint_error_dev(&sc->sc_dev, "unable to establish interrupt"); 365 if (intrstr != NULL) 366 aprint_error(" at %s", intrstr); 367 aprint_error("\n"); 368 return; 369 } 370 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 371 372 /* 373 * Allocate the control data structures, and create and load the 374 * DMA map for it. 375 */ 376 if ((error = bus_dmamem_alloc(sc->sc_dmat, 377 sizeof(struct ste_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 378 0)) != 0) { 379 aprint_error_dev(&sc->sc_dev, "unable to allocate control data, error = %d\n", 380 error); 381 goto fail_0; 382 } 383 384 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 385 sizeof(struct ste_control_data), (void **)&sc->sc_control_data, 386 BUS_DMA_COHERENT)) != 0) { 387 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 388 error); 389 goto fail_1; 390 } 391 392 if ((error = bus_dmamap_create(sc->sc_dmat, 393 sizeof(struct ste_control_data), 1, 394 sizeof(struct ste_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 395 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 396 "error = %d\n", error); 397 goto fail_2; 398 } 399 400 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 401 sc->sc_control_data, sizeof(struct ste_control_data), NULL, 402 0)) != 0) { 403 aprint_error_dev(&sc->sc_dev, "unable to load control data DMA map, error = %d\n", 404 error); 405 goto fail_3; 406 } 407 408 /* 409 * Create the transmit buffer DMA maps. 410 */ 411 for (i = 0; i < STE_NTXDESC; i++) { 412 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 413 STE_NTXFRAGS, MCLBYTES, 0, 0, 414 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 415 aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, " 416 "error = %d\n", i, error); 417 goto fail_4; 418 } 419 } 420 421 /* 422 * Create the receive buffer DMA maps. 423 */ 424 for (i = 0; i < STE_NRXDESC; i++) { 425 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 426 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 427 aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, " 428 "error = %d\n", i, error); 429 goto fail_5; 430 } 431 sc->sc_rxsoft[i].ds_mbuf = NULL; 432 } 433 434 /* 435 * Reset the chip to a known state. 436 */ 437 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 438 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 439 440 /* 441 * Read the Ethernet address from the EEPROM. 442 */ 443 for (i = 0; i < 3; i++) { 444 ste_read_eeprom(sc, STE_EEPROM_StationAddress0 + i, &myea[i]); 445 myea[i] = le16toh(myea[i]); 446 } 447 memcpy(enaddr, myea, sizeof(enaddr)); 448 449 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 450 ether_sprintf(enaddr)); 451 452 /* 453 * Initialize our media structures and probe the MII. 454 */ 455 sc->sc_mii.mii_ifp = ifp; 456 sc->sc_mii.mii_readreg = ste_mii_readreg; 457 sc->sc_mii.mii_writereg = ste_mii_writereg; 458 sc->sc_mii.mii_statchg = ste_mii_statchg; 459 sc->sc_ethercom.ec_mii = &sc->sc_mii; 460 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 461 ether_mediastatus); 462 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 463 MII_OFFSET_ANY, 0); 464 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 465 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 466 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 467 } else 468 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 469 470 ifp = &sc->sc_ethercom.ec_if; 471 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 472 ifp->if_softc = sc; 473 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 474 ifp->if_ioctl = ste_ioctl; 475 ifp->if_start = ste_start; 476 ifp->if_watchdog = ste_watchdog; 477 ifp->if_init = ste_init; 478 ifp->if_stop = ste_stop; 479 IFQ_SET_READY(&ifp->if_snd); 480 481 /* 482 * Default the transmit threshold to 128 bytes. 483 */ 484 sc->sc_txthresh = 128; 485 486 /* 487 * Disable MWI if the PCI layer tells us to. 488 */ 489 sc->sc_DMACtrl = 0; 490 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 491 sc->sc_DMACtrl |= DC_MWIDisable; 492 493 /* 494 * We can support 802.1Q VLAN-sized frames. 495 */ 496 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 497 498 /* 499 * Attach the interface. 500 */ 501 if_attach(ifp); 502 ether_ifattach(ifp, enaddr); 503 504 /* 505 * Make sure the interface is shutdown during reboot. 506 */ 507 if (pmf_device_register1(self, NULL, NULL, ste_shutdown)) 508 pmf_class_network_register(self, ifp); 509 else 510 aprint_error_dev(self, "couldn't establish power handler\n"); 511 512 return; 513 514 /* 515 * Free any resources we've allocated during the failed attach 516 * attempt. Do this in reverse order and fall through. 517 */ 518 fail_5: 519 for (i = 0; i < STE_NRXDESC; i++) { 520 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 521 bus_dmamap_destroy(sc->sc_dmat, 522 sc->sc_rxsoft[i].ds_dmamap); 523 } 524 fail_4: 525 for (i = 0; i < STE_NTXDESC; i++) { 526 if (sc->sc_txsoft[i].ds_dmamap != NULL) 527 bus_dmamap_destroy(sc->sc_dmat, 528 sc->sc_txsoft[i].ds_dmamap); 529 } 530 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 531 fail_3: 532 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 533 fail_2: 534 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 535 sizeof(struct ste_control_data)); 536 fail_1: 537 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 538 fail_0: 539 return; 540 } 541 542 /* 543 * ste_shutdown: 544 * 545 * Make sure the interface is stopped at reboot time. 546 */ 547 static bool 548 ste_shutdown(device_t self, int howto) 549 { 550 struct ste_softc *sc; 551 552 sc = device_private(self); 553 ste_stop(&sc->sc_ethercom.ec_if, 1); 554 555 return true; 556 } 557 558 static void 559 ste_dmahalt_wait(struct ste_softc *sc) 560 { 561 int i; 562 563 for (i = 0; i < STE_TIMEOUT; i++) { 564 delay(2); 565 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_DMACtrl) & 566 DC_DMAHaltBusy) == 0) 567 break; 568 } 569 570 if (i == STE_TIMEOUT) 571 printf("%s: DMA halt timed out\n", device_xname(&sc->sc_dev)); 572 } 573 574 /* 575 * ste_start: [ifnet interface function] 576 * 577 * Start packet transmission on the interface. 578 */ 579 static void 580 ste_start(struct ifnet *ifp) 581 { 582 struct ste_softc *sc = ifp->if_softc; 583 struct mbuf *m0, *m; 584 struct ste_descsoft *ds; 585 struct ste_tfd *tfd; 586 bus_dmamap_t dmamap; 587 int error, olasttx, nexttx, opending, seg, totlen; 588 589 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 590 return; 591 592 /* 593 * Remember the previous number of pending transmissions 594 * and the current last descriptor in the list. 595 */ 596 opending = sc->sc_txpending; 597 olasttx = sc->sc_txlast; 598 599 /* 600 * Loop through the send queue, setting up transmit descriptors 601 * until we drain the queue, or use up all available transmit 602 * descriptors. 603 */ 604 while (sc->sc_txpending < STE_NTXDESC) { 605 /* 606 * Grab a packet off the queue. 607 */ 608 IFQ_POLL(&ifp->if_snd, m0); 609 if (m0 == NULL) 610 break; 611 m = NULL; 612 613 /* 614 * Get the last and next available transmit descriptor. 615 */ 616 nexttx = STE_NEXTTX(sc->sc_txlast); 617 tfd = &sc->sc_txdescs[nexttx]; 618 ds = &sc->sc_txsoft[nexttx]; 619 620 dmamap = ds->ds_dmamap; 621 622 /* 623 * Load the DMA map. If this fails, the packet either 624 * didn't fit in the alloted number of segments, or we 625 * were short on resources. In this case, we'll copy 626 * and try again. 627 */ 628 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 629 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 630 MGETHDR(m, M_DONTWAIT, MT_DATA); 631 if (m == NULL) { 632 printf("%s: unable to allocate Tx mbuf\n", 633 device_xname(&sc->sc_dev)); 634 break; 635 } 636 if (m0->m_pkthdr.len > MHLEN) { 637 MCLGET(m, M_DONTWAIT); 638 if ((m->m_flags & M_EXT) == 0) { 639 printf("%s: unable to allocate Tx " 640 "cluster\n", device_xname(&sc->sc_dev)); 641 m_freem(m); 642 break; 643 } 644 } 645 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 646 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 647 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 648 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 649 if (error) { 650 printf("%s: unable to load Tx buffer, " 651 "error = %d\n", device_xname(&sc->sc_dev), error); 652 break; 653 } 654 } 655 656 IFQ_DEQUEUE(&ifp->if_snd, m0); 657 if (m != NULL) { 658 m_freem(m0); 659 m0 = m; 660 } 661 662 /* 663 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 664 */ 665 666 /* Sync the DMA map. */ 667 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 668 BUS_DMASYNC_PREWRITE); 669 670 /* Initialize the fragment list. */ 671 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 672 tfd->tfd_frags[seg].frag_addr = 673 htole32(dmamap->dm_segs[seg].ds_addr); 674 tfd->tfd_frags[seg].frag_len = 675 htole32(dmamap->dm_segs[seg].ds_len); 676 totlen += dmamap->dm_segs[seg].ds_len; 677 } 678 tfd->tfd_frags[seg - 1].frag_len |= htole32(FRAG_LAST); 679 680 /* Initialize the descriptor. */ 681 tfd->tfd_next = htole32(STE_CDTXADDR(sc, nexttx)); 682 tfd->tfd_control = htole32(TFD_FrameId(nexttx) | (totlen & 3)); 683 684 /* Sync the descriptor. */ 685 STE_CDTXSYNC(sc, nexttx, 686 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 687 688 /* 689 * Store a pointer to the packet so we can free it later, 690 * and remember what txdirty will be once the packet is 691 * done. 692 */ 693 ds->ds_mbuf = m0; 694 695 /* Advance the tx pointer. */ 696 sc->sc_txpending++; 697 sc->sc_txlast = nexttx; 698 699 /* 700 * Pass the packet to any BPF listeners. 701 */ 702 bpf_mtap(ifp, m0); 703 } 704 705 if (sc->sc_txpending == STE_NTXDESC) { 706 /* No more slots left; notify upper layer. */ 707 ifp->if_flags |= IFF_OACTIVE; 708 } 709 710 if (sc->sc_txpending != opending) { 711 /* 712 * We enqueued packets. If the transmitter was idle, 713 * reset the txdirty pointer. 714 */ 715 if (opending == 0) 716 sc->sc_txdirty = STE_NEXTTX(olasttx); 717 718 /* 719 * Cause a descriptor interrupt to happen on the 720 * last packet we enqueued, and also cause the 721 * DMA engine to wait after is has finished processing 722 * it. 723 */ 724 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0; 725 sc->sc_txdescs[sc->sc_txlast].tfd_control |= 726 htole32(TFD_TxDMAIndicate); 727 STE_CDTXSYNC(sc, sc->sc_txlast, 728 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 729 730 /* 731 * Link up the new chain of descriptors to the 732 * last. 733 */ 734 sc->sc_txdescs[olasttx].tfd_next = 735 htole32(STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 736 STE_CDTXSYNC(sc, olasttx, 737 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 738 739 /* 740 * Kick the transmit DMA logic. Note that since we're 741 * using auto-polling, reading the Tx desc pointer will 742 * give it the nudge it needs to get going. 743 */ 744 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 745 STE_TxDMAListPtr) == 0) { 746 bus_space_write_4(sc->sc_st, sc->sc_sh, 747 STE_DMACtrl, DC_TxDMAHalt); 748 ste_dmahalt_wait(sc); 749 bus_space_write_4(sc->sc_st, sc->sc_sh, 750 STE_TxDMAListPtr, 751 STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 752 bus_space_write_4(sc->sc_st, sc->sc_sh, 753 STE_DMACtrl, DC_TxDMAResume); 754 } 755 756 /* Set a watchdog timer in case the chip flakes out. */ 757 ifp->if_timer = 5; 758 } 759 } 760 761 /* 762 * ste_watchdog: [ifnet interface function] 763 * 764 * Watchdog timer handler. 765 */ 766 static void 767 ste_watchdog(struct ifnet *ifp) 768 { 769 struct ste_softc *sc = ifp->if_softc; 770 771 printf("%s: device timeout\n", device_xname(&sc->sc_dev)); 772 ifp->if_oerrors++; 773 774 ste_txintr(sc); 775 ste_rxintr(sc); 776 (void) ste_init(ifp); 777 778 /* Try to get more packets going. */ 779 ste_start(ifp); 780 } 781 782 /* 783 * ste_ioctl: [ifnet interface function] 784 * 785 * Handle control requests from the operator. 786 */ 787 static int 788 ste_ioctl(struct ifnet *ifp, u_long cmd, void *data) 789 { 790 struct ste_softc *sc = ifp->if_softc; 791 int s, error; 792 793 s = splnet(); 794 795 error = ether_ioctl(ifp, cmd, data); 796 if (error == ENETRESET) { 797 /* 798 * Multicast list has changed; set the hardware filter 799 * accordingly. 800 */ 801 if (ifp->if_flags & IFF_RUNNING) 802 ste_set_filter(sc); 803 error = 0; 804 } 805 806 /* Try to get more packets going. */ 807 ste_start(ifp); 808 809 splx(s); 810 return (error); 811 } 812 813 /* 814 * ste_intr: 815 * 816 * Interrupt service routine. 817 */ 818 static int 819 ste_intr(void *arg) 820 { 821 struct ste_softc *sc = arg; 822 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 823 uint16_t isr; 824 uint8_t txstat; 825 int wantinit; 826 827 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatus) & 828 IS_InterruptStatus) == 0) 829 return (0); 830 831 for (wantinit = 0; wantinit == 0;) { 832 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatusAck); 833 if ((isr & sc->sc_IntEnable) == 0) 834 break; 835 836 /* Receive interrupts. */ 837 if (isr & IE_RxDMAComplete) 838 ste_rxintr(sc); 839 840 /* Transmit interrupts. */ 841 if (isr & (IE_TxDMAComplete|IE_TxComplete)) 842 ste_txintr(sc); 843 844 /* Statistics overflow. */ 845 if (isr & IE_UpdateStats) 846 ste_stats_update(sc); 847 848 /* Transmission errors. */ 849 if (isr & IE_TxComplete) { 850 for (;;) { 851 txstat = bus_space_read_1(sc->sc_st, sc->sc_sh, 852 STE_TxStatus); 853 if ((txstat & TS_TxComplete) == 0) 854 break; 855 if (txstat & TS_TxUnderrun) { 856 sc->sc_txthresh += 32; 857 if (sc->sc_txthresh > 0x1ffc) 858 sc->sc_txthresh = 0x1ffc; 859 printf("%s: transmit underrun, new " 860 "threshold: %d bytes\n", 861 device_xname(&sc->sc_dev), 862 sc->sc_txthresh); 863 ste_reset(sc, AC_TxReset | AC_DMA | 864 AC_FIFO | AC_Network); 865 ste_setthresh(sc); 866 bus_space_write_1(sc->sc_st, sc->sc_sh, 867 STE_TxDMAPollPeriod, 127); 868 ste_txrestart(sc, 869 bus_space_read_1(sc->sc_st, 870 sc->sc_sh, STE_TxFrameId)); 871 } 872 if (txstat & TS_TxReleaseError) { 873 printf("%s: Tx FIFO release error\n", 874 device_xname(&sc->sc_dev)); 875 wantinit = 1; 876 } 877 if (txstat & TS_MaxCollisions) { 878 printf("%s: excessive collisions\n", 879 device_xname(&sc->sc_dev)); 880 wantinit = 1; 881 } 882 if (txstat & TS_TxStatusOverflow) { 883 printf("%s: status overflow\n", 884 device_xname(&sc->sc_dev)); 885 wantinit = 1; 886 } 887 bus_space_write_2(sc->sc_st, sc->sc_sh, 888 STE_TxStatus, 0); 889 } 890 } 891 892 /* Host interface errors. */ 893 if (isr & IE_HostError) { 894 printf("%s: Host interface error\n", 895 device_xname(&sc->sc_dev)); 896 wantinit = 1; 897 } 898 } 899 900 if (wantinit) 901 ste_init(ifp); 902 903 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 904 sc->sc_IntEnable); 905 906 /* Try to get more packets going. */ 907 ste_start(ifp); 908 909 return (1); 910 } 911 912 /* 913 * ste_txintr: 914 * 915 * Helper; handle transmit interrupts. 916 */ 917 static void 918 ste_txintr(struct ste_softc *sc) 919 { 920 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 921 struct ste_descsoft *ds; 922 uint32_t control; 923 int i; 924 925 ifp->if_flags &= ~IFF_OACTIVE; 926 927 /* 928 * Go through our Tx list and free mbufs for those 929 * frames which have been transmitted. 930 */ 931 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 932 i = STE_NEXTTX(i), sc->sc_txpending--) { 933 ds = &sc->sc_txsoft[i]; 934 935 STE_CDTXSYNC(sc, i, 936 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 937 938 control = le32toh(sc->sc_txdescs[i].tfd_control); 939 if ((control & TFD_TxDMAComplete) == 0) 940 break; 941 942 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 943 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 944 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 945 m_freem(ds->ds_mbuf); 946 ds->ds_mbuf = NULL; 947 } 948 949 /* Update the dirty transmit buffer pointer. */ 950 sc->sc_txdirty = i; 951 952 /* 953 * If there are no more pending transmissions, cancel the watchdog 954 * timer. 955 */ 956 if (sc->sc_txpending == 0) 957 ifp->if_timer = 0; 958 } 959 960 /* 961 * ste_rxintr: 962 * 963 * Helper; handle receive interrupts. 964 */ 965 static void 966 ste_rxintr(struct ste_softc *sc) 967 { 968 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 969 struct ste_descsoft *ds; 970 struct mbuf *m; 971 uint32_t status; 972 int i, len; 973 974 for (i = sc->sc_rxptr;; i = STE_NEXTRX(i)) { 975 ds = &sc->sc_rxsoft[i]; 976 977 STE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 978 979 status = le32toh(sc->sc_rxdescs[i].rfd_status); 980 981 if ((status & RFD_RxDMAComplete) == 0) 982 break; 983 984 /* 985 * If the packet had an error, simply recycle the 986 * buffer. Note, we count the error later in the 987 * periodic stats update. 988 */ 989 if (status & RFD_RxFrameError) { 990 STE_INIT_RXDESC(sc, i); 991 continue; 992 } 993 994 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 995 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 996 997 /* 998 * No errors; receive the packet. Note, we have 999 * configured the chip to not include the CRC at 1000 * the end of the packet. 1001 */ 1002 len = RFD_RxDMAFrameLen(status); 1003 1004 /* 1005 * If the packet is small enough to fit in a 1006 * single header mbuf, allocate one and copy 1007 * the data into it. This greatly reduces 1008 * memory consumption when we receive lots 1009 * of small packets. 1010 * 1011 * Otherwise, we add a new buffer to the receive 1012 * chain. If this fails, we drop the packet and 1013 * recycle the old buffer. 1014 */ 1015 if (ste_copy_small != 0 && len <= (MHLEN - 2)) { 1016 MGETHDR(m, M_DONTWAIT, MT_DATA); 1017 if (m == NULL) 1018 goto dropit; 1019 m->m_data += 2; 1020 memcpy(mtod(m, void *), 1021 mtod(ds->ds_mbuf, void *), len); 1022 STE_INIT_RXDESC(sc, i); 1023 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1024 ds->ds_dmamap->dm_mapsize, 1025 BUS_DMASYNC_PREREAD); 1026 } else { 1027 m = ds->ds_mbuf; 1028 if (ste_add_rxbuf(sc, i) != 0) { 1029 dropit: 1030 ifp->if_ierrors++; 1031 STE_INIT_RXDESC(sc, i); 1032 bus_dmamap_sync(sc->sc_dmat, 1033 ds->ds_dmamap, 0, 1034 ds->ds_dmamap->dm_mapsize, 1035 BUS_DMASYNC_PREREAD); 1036 continue; 1037 } 1038 } 1039 1040 m->m_pkthdr.rcvif = ifp; 1041 m->m_pkthdr.len = m->m_len = len; 1042 1043 /* 1044 * Pass this up to any BPF listeners, but only 1045 * pass if up the stack if it's for us. 1046 */ 1047 bpf_mtap(ifp, m); 1048 1049 /* Pass it on. */ 1050 (*ifp->if_input)(ifp, m); 1051 } 1052 1053 /* Update the receive pointer. */ 1054 sc->sc_rxptr = i; 1055 } 1056 1057 /* 1058 * ste_tick: 1059 * 1060 * One second timer, used to tick the MII. 1061 */ 1062 static void 1063 ste_tick(void *arg) 1064 { 1065 struct ste_softc *sc = arg; 1066 int s; 1067 1068 s = splnet(); 1069 mii_tick(&sc->sc_mii); 1070 ste_stats_update(sc); 1071 splx(s); 1072 1073 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1074 } 1075 1076 /* 1077 * ste_stats_update: 1078 * 1079 * Read the ST-201 statistics counters. 1080 */ 1081 static void 1082 ste_stats_update(struct ste_softc *sc) 1083 { 1084 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1085 bus_space_tag_t st = sc->sc_st; 1086 bus_space_handle_t sh = sc->sc_sh; 1087 1088 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk0); 1089 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk1); 1090 1091 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk0); 1092 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk1); 1093 1094 ifp->if_opackets += 1095 (u_int) bus_space_read_2(st, sh, STE_FramesTransmittedOK); 1096 ifp->if_ipackets += 1097 (u_int) bus_space_read_2(st, sh, STE_FramesReceivedOK); 1098 1099 ifp->if_collisions += 1100 (u_int) bus_space_read_1(st, sh, STE_LateCollisions) + 1101 (u_int) bus_space_read_1(st, sh, STE_MultipleColFrames) + 1102 (u_int) bus_space_read_1(st, sh, STE_SingleColFrames); 1103 1104 (void) bus_space_read_1(st, sh, STE_FramesWDeferredXmt); 1105 1106 ifp->if_ierrors += 1107 (u_int) bus_space_read_1(st, sh, STE_FramesLostRxErrors); 1108 1109 ifp->if_oerrors += 1110 (u_int) bus_space_read_1(st, sh, STE_FramesWExDeferral) + 1111 (u_int) bus_space_read_1(st, sh, STE_FramesXbortXSColls) + 1112 bus_space_read_1(st, sh, STE_CarrierSenseErrors); 1113 1114 (void) bus_space_read_1(st, sh, STE_BcstFramesXmtdOk); 1115 (void) bus_space_read_1(st, sh, STE_BcstFramesRcvdOk); 1116 (void) bus_space_read_1(st, sh, STE_McstFramesXmtdOk); 1117 (void) bus_space_read_1(st, sh, STE_McstFramesRcvdOk); 1118 } 1119 1120 /* 1121 * ste_reset: 1122 * 1123 * Perform a soft reset on the ST-201. 1124 */ 1125 static void 1126 ste_reset(struct ste_softc *sc, u_int32_t rstbits) 1127 { 1128 uint32_t ac; 1129 int i; 1130 1131 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl); 1132 1133 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl, ac | rstbits); 1134 1135 delay(50000); 1136 1137 for (i = 0; i < STE_TIMEOUT; i++) { 1138 delay(1000); 1139 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl) & 1140 AC_ResetBusy) == 0) 1141 break; 1142 } 1143 1144 if (i == STE_TIMEOUT) 1145 printf("%s: reset failed to complete\n", device_xname(&sc->sc_dev)); 1146 1147 delay(1000); 1148 } 1149 1150 /* 1151 * ste_setthresh: 1152 * 1153 * set the various transmit threshold registers 1154 */ 1155 static void 1156 ste_setthresh(struct ste_softc *sc) 1157 { 1158 /* set the TX threhold */ 1159 bus_space_write_2(sc->sc_st, sc->sc_sh, 1160 STE_TxStartThresh, sc->sc_txthresh); 1161 /* Urgent threshold: set to sc_txthresh / 2 */ 1162 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_TxDMAUrgentThresh, 1163 sc->sc_txthresh >> 6); 1164 /* Burst threshold: use default value (256 bytes) */ 1165 } 1166 1167 /* 1168 * restart TX at the given frame ID in the transmitter ring 1169 */ 1170 static void 1171 ste_txrestart(struct ste_softc *sc, u_int8_t id) 1172 { 1173 u_int32_t control; 1174 1175 STE_CDTXSYNC(sc, id, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1176 control = le32toh(sc->sc_txdescs[id].tfd_control); 1177 control &= ~TFD_TxDMAComplete; 1178 sc->sc_txdescs[id].tfd_control = htole32(control); 1179 STE_CDTXSYNC(sc, id, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1180 1181 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 0); 1182 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, MC1_TxEnable); 1183 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAHalt); 1184 ste_dmahalt_wait(sc); 1185 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 1186 STE_CDTXADDR(sc, id)); 1187 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAResume); 1188 } 1189 1190 /* 1191 * ste_init: [ ifnet interface function ] 1192 * 1193 * Initialize the interface. Must be called at splnet(). 1194 */ 1195 static int 1196 ste_init(struct ifnet *ifp) 1197 { 1198 struct ste_softc *sc = ifp->if_softc; 1199 bus_space_tag_t st = sc->sc_st; 1200 bus_space_handle_t sh = sc->sc_sh; 1201 struct ste_descsoft *ds; 1202 int i, error = 0; 1203 1204 /* 1205 * Cancel any pending I/O. 1206 */ 1207 ste_stop(ifp, 0); 1208 1209 /* 1210 * Reset the chip to a known state. 1211 */ 1212 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 1213 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 1214 1215 /* 1216 * Initialize the transmit descriptor ring. 1217 */ 1218 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1219 sc->sc_txpending = 0; 1220 sc->sc_txdirty = 0; 1221 sc->sc_txlast = STE_NTXDESC - 1; 1222 1223 /* 1224 * Initialize the receive descriptor and receive job 1225 * descriptor rings. 1226 */ 1227 for (i = 0; i < STE_NRXDESC; i++) { 1228 ds = &sc->sc_rxsoft[i]; 1229 if (ds->ds_mbuf == NULL) { 1230 if ((error = ste_add_rxbuf(sc, i)) != 0) { 1231 printf("%s: unable to allocate or map rx " 1232 "buffer %d, error = %d\n", 1233 device_xname(&sc->sc_dev), i, error); 1234 /* 1235 * XXX Should attempt to run with fewer receive 1236 * XXX buffers instead of just failing. 1237 */ 1238 ste_rxdrain(sc); 1239 goto out; 1240 } 1241 } else 1242 STE_INIT_RXDESC(sc, i); 1243 } 1244 sc->sc_rxptr = 0; 1245 1246 /* Set the station address. */ 1247 for (i = 0; i < ETHER_ADDR_LEN; i++) 1248 bus_space_write_1(st, sh, STE_StationAddress0 + 1, 1249 CLLADDR(ifp->if_sadl)[i]); 1250 1251 /* Set up the receive filter. */ 1252 ste_set_filter(sc); 1253 1254 /* 1255 * Give the receive ring to the chip. 1256 */ 1257 bus_space_write_4(st, sh, STE_RxDMAListPtr, 1258 STE_CDRXADDR(sc, sc->sc_rxptr)); 1259 1260 /* 1261 * We defer giving the transmit ring to the chip until we 1262 * transmit the first packet. 1263 */ 1264 1265 /* 1266 * Initialize the Tx auto-poll period. It's OK to make this number 1267 * large (127 is the max) -- we explicitly kick the transmit engine 1268 * when there's actually a packet. We are using auto-polling only 1269 * to make the interface to the transmit engine not suck. 1270 */ 1271 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAPollPeriod, 127); 1272 1273 /* ..and the Rx auto-poll period. */ 1274 bus_space_write_1(st, sh, STE_RxDMAPollPeriod, 64); 1275 1276 /* Initialize the Tx start threshold. */ 1277 ste_setthresh(sc); 1278 1279 /* Set the FIFO release threshold to 512 bytes. */ 1280 bus_space_write_1(st, sh, STE_TxReleaseThresh, 512 >> 4); 1281 1282 /* Set maximum packet size for VLAN. */ 1283 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1284 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN + 4); 1285 else 1286 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN); 1287 1288 /* 1289 * Initialize the interrupt mask. 1290 */ 1291 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1292 IE_TxDMAComplete | IE_RxDMAComplete; 1293 1294 bus_space_write_2(st, sh, STE_IntStatus, 0xffff); 1295 bus_space_write_2(st, sh, STE_IntEnable, sc->sc_IntEnable); 1296 1297 /* 1298 * Start the receive DMA engine. 1299 */ 1300 bus_space_write_4(st, sh, STE_DMACtrl, sc->sc_DMACtrl | DC_RxDMAResume); 1301 1302 /* 1303 * Initialize MacCtrl0 -- do it before setting the media, 1304 * as setting the media will actually program the register. 1305 */ 1306 sc->sc_MacCtrl0 = MC0_IFSSelect(0); 1307 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1308 sc->sc_MacCtrl0 |= MC0_RcvLargeFrames; 1309 1310 /* 1311 * Set the current media. 1312 */ 1313 if ((error = ether_mediachange(ifp)) != 0) 1314 goto out; 1315 1316 /* 1317 * Start the MAC. 1318 */ 1319 bus_space_write_2(st, sh, STE_MacCtrl1, 1320 MC1_StatisticsEnable | MC1_TxEnable | MC1_RxEnable); 1321 1322 /* 1323 * Start the one second MII clock. 1324 */ 1325 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1326 1327 /* 1328 * ...all done! 1329 */ 1330 ifp->if_flags |= IFF_RUNNING; 1331 ifp->if_flags &= ~IFF_OACTIVE; 1332 1333 out: 1334 if (error) 1335 printf("%s: interface not running\n", device_xname(&sc->sc_dev)); 1336 return (error); 1337 } 1338 1339 /* 1340 * ste_drain: 1341 * 1342 * Drain the receive queue. 1343 */ 1344 static void 1345 ste_rxdrain(struct ste_softc *sc) 1346 { 1347 struct ste_descsoft *ds; 1348 int i; 1349 1350 for (i = 0; i < STE_NRXDESC; i++) { 1351 ds = &sc->sc_rxsoft[i]; 1352 if (ds->ds_mbuf != NULL) { 1353 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1354 m_freem(ds->ds_mbuf); 1355 ds->ds_mbuf = NULL; 1356 } 1357 } 1358 } 1359 1360 /* 1361 * ste_stop: [ ifnet interface function ] 1362 * 1363 * Stop transmission on the interface. 1364 */ 1365 static void 1366 ste_stop(struct ifnet *ifp, int disable) 1367 { 1368 struct ste_softc *sc = ifp->if_softc; 1369 struct ste_descsoft *ds; 1370 int i; 1371 1372 /* 1373 * Stop the one second clock. 1374 */ 1375 callout_stop(&sc->sc_tick_ch); 1376 1377 /* Down the MII. */ 1378 mii_down(&sc->sc_mii); 1379 1380 /* 1381 * Disable interrupts. 1382 */ 1383 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 0); 1384 1385 /* 1386 * Stop receiver, transmitter, and stats update. 1387 */ 1388 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, 1389 MC1_StatisticsDisable | MC1_TxDisable | MC1_RxDisable); 1390 1391 /* 1392 * Stop the transmit and receive DMA. 1393 */ 1394 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, 1395 DC_RxDMAHalt | DC_TxDMAHalt); 1396 ste_dmahalt_wait(sc); 1397 1398 /* 1399 * Release any queued transmit buffers. 1400 */ 1401 for (i = 0; i < STE_NTXDESC; i++) { 1402 ds = &sc->sc_txsoft[i]; 1403 if (ds->ds_mbuf != NULL) { 1404 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1405 m_freem(ds->ds_mbuf); 1406 ds->ds_mbuf = NULL; 1407 } 1408 } 1409 1410 /* 1411 * Mark the interface down and cancel the watchdog timer. 1412 */ 1413 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1414 ifp->if_timer = 0; 1415 1416 if (disable) 1417 ste_rxdrain(sc); 1418 } 1419 1420 static int 1421 ste_eeprom_wait(struct ste_softc *sc) 1422 { 1423 int i; 1424 1425 for (i = 0; i < STE_TIMEOUT; i++) { 1426 delay(1000); 1427 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl) & 1428 EC_EepromBusy) == 0) 1429 return (0); 1430 } 1431 return (1); 1432 } 1433 1434 /* 1435 * ste_read_eeprom: 1436 * 1437 * Read data from the serial EEPROM. 1438 */ 1439 static void 1440 ste_read_eeprom(struct ste_softc *sc, int offset, uint16_t *data) 1441 { 1442 1443 if (ste_eeprom_wait(sc)) 1444 printf("%s: EEPROM failed to come ready\n", 1445 device_xname(&sc->sc_dev)); 1446 1447 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl, 1448 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_R)); 1449 if (ste_eeprom_wait(sc)) 1450 printf("%s: EEPROM read timed out\n", 1451 device_xname(&sc->sc_dev)); 1452 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromData); 1453 } 1454 1455 /* 1456 * ste_add_rxbuf: 1457 * 1458 * Add a receive buffer to the indicated descriptor. 1459 */ 1460 static int 1461 ste_add_rxbuf(struct ste_softc *sc, int idx) 1462 { 1463 struct ste_descsoft *ds = &sc->sc_rxsoft[idx]; 1464 struct mbuf *m; 1465 int error; 1466 1467 MGETHDR(m, M_DONTWAIT, MT_DATA); 1468 if (m == NULL) 1469 return (ENOBUFS); 1470 1471 MCLGET(m, M_DONTWAIT); 1472 if ((m->m_flags & M_EXT) == 0) { 1473 m_freem(m); 1474 return (ENOBUFS); 1475 } 1476 1477 if (ds->ds_mbuf != NULL) 1478 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1479 1480 ds->ds_mbuf = m; 1481 1482 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1483 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1484 BUS_DMA_READ|BUS_DMA_NOWAIT); 1485 if (error) { 1486 printf("%s: can't load rx DMA map %d, error = %d\n", 1487 device_xname(&sc->sc_dev), idx, error); 1488 panic("ste_add_rxbuf"); /* XXX */ 1489 } 1490 1491 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1492 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1493 1494 STE_INIT_RXDESC(sc, idx); 1495 1496 return (0); 1497 } 1498 1499 /* 1500 * ste_set_filter: 1501 * 1502 * Set up the receive filter. 1503 */ 1504 static void 1505 ste_set_filter(struct ste_softc *sc) 1506 { 1507 struct ethercom *ec = &sc->sc_ethercom; 1508 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1509 struct ether_multi *enm; 1510 struct ether_multistep step; 1511 uint32_t crc; 1512 uint16_t mchash[4]; 1513 1514 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1515 if (ifp->if_flags & IFF_BROADCAST) 1516 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1517 1518 if (ifp->if_flags & IFF_PROMISC) { 1519 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1520 goto allmulti; 1521 } 1522 1523 /* 1524 * Set up the multicast address filter by passing all multicast 1525 * addresses through a CRC generator, and then using the low-order 1526 * 6 bits as an index into the 64 bit multicast hash table. The 1527 * high order bits select the register, while the rest of the bits 1528 * select the bit within the register. 1529 */ 1530 1531 memset(mchash, 0, sizeof(mchash)); 1532 1533 ETHER_FIRST_MULTI(step, ec, enm); 1534 if (enm == NULL) 1535 goto done; 1536 1537 while (enm != NULL) { 1538 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1539 /* 1540 * We must listen to a range of multicast addresses. 1541 * For now, just accept all multicasts, rather than 1542 * trying to set only those filter bits needed to match 1543 * the range. (At this time, the only use of address 1544 * ranges is for IP multicast routing, for which the 1545 * range is big enough to require all bits set.) 1546 */ 1547 goto allmulti; 1548 } 1549 1550 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1551 1552 /* Just want the 6 least significant bits. */ 1553 crc &= 0x3f; 1554 1555 /* Set the corresponding bit in the hash table. */ 1556 mchash[crc >> 4] |= 1 << (crc & 0xf); 1557 1558 ETHER_NEXT_MULTI(step, enm); 1559 } 1560 1561 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1562 1563 ifp->if_flags &= ~IFF_ALLMULTI; 1564 goto done; 1565 1566 allmulti: 1567 ifp->if_flags |= IFF_ALLMULTI; 1568 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1569 1570 done: 1571 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1572 /* 1573 * Program the multicast hash table. 1574 */ 1575 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable0, 1576 mchash[0]); 1577 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable1, 1578 mchash[1]); 1579 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable2, 1580 mchash[2]); 1581 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable3, 1582 mchash[3]); 1583 } 1584 1585 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_ReceiveMode, 1586 sc->sc_ReceiveMode); 1587 } 1588 1589 /* 1590 * ste_mii_readreg: [mii interface function] 1591 * 1592 * Read a PHY register on the MII of the ST-201. 1593 */ 1594 static int 1595 ste_mii_readreg(device_t self, int phy, int reg) 1596 { 1597 1598 return (mii_bitbang_readreg(self, &ste_mii_bitbang_ops, phy, reg)); 1599 } 1600 1601 /* 1602 * ste_mii_writereg: [mii interface function] 1603 * 1604 * Write a PHY register on the MII of the ST-201. 1605 */ 1606 static void 1607 ste_mii_writereg(device_t self, int phy, int reg, int val) 1608 { 1609 1610 mii_bitbang_writereg(self, &ste_mii_bitbang_ops, phy, reg, val); 1611 } 1612 1613 /* 1614 * ste_mii_statchg: [mii interface function] 1615 * 1616 * Callback from MII layer when media changes. 1617 */ 1618 static void 1619 ste_mii_statchg(device_t self) 1620 { 1621 struct ste_softc *sc = device_private(self); 1622 1623 if (sc->sc_mii.mii_media_active & IFM_FDX) 1624 sc->sc_MacCtrl0 |= MC0_FullDuplexEnable; 1625 else 1626 sc->sc_MacCtrl0 &= ~MC0_FullDuplexEnable; 1627 1628 /* XXX 802.1x flow-control? */ 1629 1630 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl0, sc->sc_MacCtrl0); 1631 } 1632 1633 /* 1634 * ste_mii_bitbang_read: [mii bit-bang interface function] 1635 * 1636 * Read the MII serial port for the MII bit-bang module. 1637 */ 1638 static uint32_t 1639 ste_mii_bitbang_read(device_t self) 1640 { 1641 struct ste_softc *sc = device_private(self); 1642 1643 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl)); 1644 } 1645 1646 /* 1647 * ste_mii_bitbang_write: [mii big-bang interface function] 1648 * 1649 * Write the MII serial port for the MII bit-bang module. 1650 */ 1651 static void 1652 ste_mii_bitbang_write(device_t self, uint32_t val) 1653 { 1654 struct ste_softc *sc = device_private(self); 1655 1656 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl, val); 1657 } 1658