1 /* $NetBSD: if_ste.c,v 1.7 2001/11/13 07:48:44 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the Sundance Tech. ST-201 10/100 41 * Ethernet controller. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_ste.c,v 1.7 2001/11/13 07:48:44 lukem Exp $"); 46 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/callout.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 #include <sys/queue.h> 60 61 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/if_ether.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 72 #include <machine/bus.h> 73 #include <machine/intr.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 #include <dev/mii/mii_bitbang.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcidevs.h> 82 83 #include <dev/pci/if_stereg.h> 84 85 /* 86 * Transmit descriptor list size. 87 */ 88 #define STE_NTXDESC 256 89 #define STE_NTXDESC_MASK (STE_NTXDESC - 1) 90 #define STE_NEXTTX(x) (((x) + 1) & STE_NTXDESC_MASK) 91 92 /* 93 * Receive descriptor list size. 94 */ 95 #define STE_NRXDESC 128 96 #define STE_NRXDESC_MASK (STE_NRXDESC - 1) 97 #define STE_NEXTRX(x) (((x) + 1) & STE_NRXDESC_MASK) 98 99 /* 100 * Control structures are DMA'd to the ST-201 chip. We allocate them in 101 * a single clump that maps to a single DMA segment to make several things 102 * easier. 103 */ 104 struct ste_control_data { 105 /* 106 * The transmit descriptors. 107 */ 108 struct ste_tfd scd_txdescs[STE_NTXDESC]; 109 110 /* 111 * The receive descriptors. 112 */ 113 struct ste_rfd scd_rxdescs[STE_NRXDESC]; 114 }; 115 116 #define STE_CDOFF(x) offsetof(struct ste_control_data, x) 117 #define STE_CDTXOFF(x) STE_CDOFF(scd_txdescs[(x)]) 118 #define STE_CDRXOFF(x) STE_CDOFF(scd_rxdescs[(x)]) 119 120 /* 121 * Software state for transmit and receive jobs. 122 */ 123 struct ste_descsoft { 124 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 125 bus_dmamap_t ds_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct ste_softc { 132 struct device sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 void *sc_sdhook; /* shutdown hook */ 138 139 void *sc_ih; /* interrupt cookie */ 140 141 struct mii_data sc_mii; /* MII/media information */ 142 143 struct callout sc_tick_ch; /* tick callout */ 144 145 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* 149 * Software state for transmit and receive descriptors. 150 */ 151 struct ste_descsoft sc_txsoft[STE_NTXDESC]; 152 struct ste_descsoft sc_rxsoft[STE_NRXDESC]; 153 154 /* 155 * Control data structures. 156 */ 157 struct ste_control_data *sc_control_data; 158 #define sc_txdescs sc_control_data->scd_txdescs 159 #define sc_rxdescs sc_control_data->scd_rxdescs 160 161 int sc_txpending; /* number of Tx requests pending */ 162 int sc_txdirty; /* first dirty Tx descriptor */ 163 int sc_txlast; /* last used Tx descriptor */ 164 165 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 166 167 int sc_txthresh; /* Tx threshold */ 168 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 169 uint16_t sc_IntEnable; /* prototype IntEnable register */ 170 uint16_t sc_MacCtrl0; /* prototype MacCtrl0 register */ 171 uint8_t sc_ReceiveMode; /* prototype ReceiveMode register */ 172 }; 173 174 #define STE_CDTXADDR(sc, x) ((sc)->sc_cddma + STE_CDTXOFF((x))) 175 #define STE_CDRXADDR(sc, x) ((sc)->sc_cddma + STE_CDRXOFF((x))) 176 177 #define STE_CDTXSYNC(sc, x, ops) \ 178 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 179 STE_CDTXOFF((x)), sizeof(struct ste_tfd), (ops)) 180 181 #define STE_CDRXSYNC(sc, x, ops) \ 182 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 183 STE_CDRXOFF((x)), sizeof(struct ste_rfd), (ops)) 184 185 #define STE_INIT_RXDESC(sc, x) \ 186 do { \ 187 struct ste_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 188 struct ste_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 189 struct mbuf *__m = __ds->ds_mbuf; \ 190 \ 191 /* \ 192 * Note: We scoot the packet forward 2 bytes in the buffer \ 193 * so that the payload after the Ethernet header is aligned \ 194 * to a 4-byte boundary. \ 195 */ \ 196 __m->m_data = __m->m_ext.ext_buf + 2; \ 197 __rfd->rfd_frag.frag_addr = \ 198 htole32(__ds->ds_dmamap->dm_segs[0].ds_addr + 2); \ 199 __rfd->rfd_frag.frag_len = htole32((MCLBYTES - 2) | FRAG_LAST); \ 200 __rfd->rfd_next = htole32(STE_CDRXADDR((sc), STE_NEXTRX((x)))); \ 201 __rfd->rfd_status = 0; \ 202 STE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 203 } while (/*CONSTCOND*/0) 204 205 #define STE_TIMEOUT 1000 206 207 void ste_start(struct ifnet *); 208 void ste_watchdog(struct ifnet *); 209 int ste_ioctl(struct ifnet *, u_long, caddr_t); 210 int ste_init(struct ifnet *); 211 void ste_stop(struct ifnet *, int); 212 213 void ste_shutdown(void *); 214 215 void ste_reset(struct ste_softc *); 216 void ste_rxdrain(struct ste_softc *); 217 int ste_add_rxbuf(struct ste_softc *, int); 218 void ste_read_eeprom(struct ste_softc *, int, uint16_t *); 219 void ste_tick(void *); 220 221 void ste_stats_update(struct ste_softc *); 222 223 void ste_set_filter(struct ste_softc *); 224 225 int ste_intr(void *); 226 void ste_txintr(struct ste_softc *); 227 void ste_rxintr(struct ste_softc *); 228 229 int ste_mii_readreg(struct device *, int, int); 230 void ste_mii_writereg(struct device *, int, int, int); 231 void ste_mii_statchg(struct device *); 232 233 int ste_mediachange(struct ifnet *); 234 void ste_mediastatus(struct ifnet *, struct ifmediareq *); 235 236 int ste_match(struct device *, struct cfdata *, void *); 237 void ste_attach(struct device *, struct device *, void *); 238 239 int ste_copy_small = 0; 240 241 struct cfattach ste_ca = { 242 sizeof(struct ste_softc), ste_match, ste_attach, 243 }; 244 245 uint32_t ste_mii_bitbang_read(struct device *); 246 void ste_mii_bitbang_write(struct device *, uint32_t); 247 248 const struct mii_bitbang_ops ste_mii_bitbang_ops = { 249 ste_mii_bitbang_read, 250 ste_mii_bitbang_write, 251 { 252 PC_MgmtData, /* MII_BIT_MDO */ 253 PC_MgmtData, /* MII_BIT_MDI */ 254 PC_MgmtClk, /* MII_BIT_MDC */ 255 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 256 0, /* MII_BIT_DIR_PHY_HOST */ 257 } 258 }; 259 260 /* 261 * Devices supported by this driver. 262 */ 263 const struct ste_product { 264 pci_vendor_id_t ste_vendor; 265 pci_product_id_t ste_product; 266 const char *ste_name; 267 } ste_products[] = { 268 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 269 "Sundance ST-201 10/100 Ethernet" }, 270 271 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 272 "D-Link DL-1002 10/100 Ethernet" }, 273 274 { 0, 0, 275 NULL }, 276 }; 277 278 static const struct ste_product * 279 ste_lookup(const struct pci_attach_args *pa) 280 { 281 const struct ste_product *sp; 282 283 for (sp = ste_products; sp->ste_name != NULL; sp++) { 284 if (PCI_VENDOR(pa->pa_id) == sp->ste_vendor && 285 PCI_PRODUCT(pa->pa_id) == sp->ste_product) 286 return (sp); 287 } 288 return (NULL); 289 } 290 291 int 292 ste_match(struct device *parent, struct cfdata *cf, void *aux) 293 { 294 struct pci_attach_args *pa = aux; 295 296 if (ste_lookup(pa) != NULL) 297 return (1); 298 299 return (0); 300 } 301 302 void 303 ste_attach(struct device *parent, struct device *self, void *aux) 304 { 305 struct ste_softc *sc = (struct ste_softc *) self; 306 struct pci_attach_args *pa = aux; 307 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 308 pci_chipset_tag_t pc = pa->pa_pc; 309 pci_intr_handle_t ih; 310 const char *intrstr = NULL; 311 bus_space_tag_t iot, memt; 312 bus_space_handle_t ioh, memh; 313 bus_dma_segment_t seg; 314 int ioh_valid, memh_valid; 315 int i, rseg, error; 316 const struct ste_product *sp; 317 pcireg_t pmode; 318 uint8_t enaddr[ETHER_ADDR_LEN]; 319 uint16_t myea[ETHER_ADDR_LEN / 2]; 320 int pmreg; 321 322 callout_init(&sc->sc_tick_ch); 323 324 sp = ste_lookup(pa); 325 if (sp == NULL) { 326 printf("\n"); 327 panic("ste_attach: impossible"); 328 } 329 330 printf(": %s\n", sp->ste_name); 331 332 /* 333 * Map the device. 334 */ 335 ioh_valid = (pci_mapreg_map(pa, STE_PCI_IOBA, 336 PCI_MAPREG_TYPE_IO, 0, 337 &iot, &ioh, NULL, NULL) == 0); 338 memh_valid = (pci_mapreg_map(pa, STE_PCI_MMBA, 339 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 340 &memt, &memh, NULL, NULL) == 0); 341 342 if (memh_valid) { 343 sc->sc_st = memt; 344 sc->sc_sh = memh; 345 } else if (ioh_valid) { 346 sc->sc_st = iot; 347 sc->sc_sh = ioh; 348 } else { 349 printf("%s: unable to map device registers\n", 350 sc->sc_dev.dv_xname); 351 return; 352 } 353 354 sc->sc_dmat = pa->pa_dmat; 355 356 /* Enable bus mastering. */ 357 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 358 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 359 PCI_COMMAND_MASTER_ENABLE); 360 361 /* Get it out of power save mode if needed. */ 362 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 363 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 364 if (pmode == 3) { 365 /* 366 * The card has lost all configuration data in 367 * this state, so punt. 368 */ 369 printf("%s: unable to wake up from power state D3\n", 370 sc->sc_dev.dv_xname); 371 return; 372 } 373 if (pmode != 0) { 374 printf("%s: waking up from power state D%d\n", 375 sc->sc_dev.dv_xname, pmode); 376 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 377 } 378 } 379 380 /* 381 * Map and establish our interrupt. 382 */ 383 if (pci_intr_map(pa, &ih)) { 384 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 385 return; 386 } 387 intrstr = pci_intr_string(pc, ih); 388 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ste_intr, sc); 389 if (sc->sc_ih == NULL) { 390 printf("%s: unable to establish interrupt", 391 sc->sc_dev.dv_xname); 392 if (intrstr != NULL) 393 printf(" at %s", intrstr); 394 printf("\n"); 395 return; 396 } 397 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 398 399 /* 400 * Allocate the control data structures, and create and load the 401 * DMA map for it. 402 */ 403 if ((error = bus_dmamem_alloc(sc->sc_dmat, 404 sizeof(struct ste_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 405 0)) != 0) { 406 printf("%s: unable to allocate control data, error = %d\n", 407 sc->sc_dev.dv_xname, error); 408 goto fail_0; 409 } 410 411 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 412 sizeof(struct ste_control_data), (caddr_t *)&sc->sc_control_data, 413 BUS_DMA_COHERENT)) != 0) { 414 printf("%s: unable to map control data, error = %d\n", 415 sc->sc_dev.dv_xname, error); 416 goto fail_1; 417 } 418 419 if ((error = bus_dmamap_create(sc->sc_dmat, 420 sizeof(struct ste_control_data), 1, 421 sizeof(struct ste_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 422 printf("%s: unable to create control data DMA map, " 423 "error = %d\n", sc->sc_dev.dv_xname, error); 424 goto fail_2; 425 } 426 427 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 428 sc->sc_control_data, sizeof(struct ste_control_data), NULL, 429 0)) != 0) { 430 printf("%s: unable to load control data DMA map, error = %d\n", 431 sc->sc_dev.dv_xname, error); 432 goto fail_3; 433 } 434 435 /* 436 * Create the transmit buffer DMA maps. 437 */ 438 for (i = 0; i < STE_NTXDESC; i++) { 439 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 440 STE_NTXFRAGS, MCLBYTES, 0, 0, 441 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 442 printf("%s: unable to create tx DMA map %d, " 443 "error = %d\n", sc->sc_dev.dv_xname, i, error); 444 goto fail_4; 445 } 446 } 447 448 /* 449 * Create the receive buffer DMA maps. 450 */ 451 for (i = 0; i < STE_NRXDESC; i++) { 452 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 453 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 454 printf("%s: unable to create rx DMA map %d, " 455 "error = %d\n", sc->sc_dev.dv_xname, i, error); 456 goto fail_5; 457 } 458 sc->sc_rxsoft[i].ds_mbuf = NULL; 459 } 460 461 /* 462 * Reset the chip to a known state. 463 */ 464 ste_reset(sc); 465 466 /* 467 * Read the Ethernet address from the EEPROM. 468 */ 469 for (i = 0; i < 3; i++) { 470 ste_read_eeprom(sc, STE_EEPROM_StationAddress0 + i, &myea[i]); 471 myea[i] = le16toh(myea[i]); 472 } 473 memcpy(enaddr, myea, sizeof(enaddr)); 474 475 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 476 ether_sprintf(enaddr)); 477 478 /* 479 * Initialize our media structures and probe the MII. 480 */ 481 sc->sc_mii.mii_ifp = ifp; 482 sc->sc_mii.mii_readreg = ste_mii_readreg; 483 sc->sc_mii.mii_writereg = ste_mii_writereg; 484 sc->sc_mii.mii_statchg = ste_mii_statchg; 485 ifmedia_init(&sc->sc_mii.mii_media, 0, ste_mediachange, 486 ste_mediastatus); 487 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 488 MII_OFFSET_ANY, 0); 489 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 490 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 491 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 492 } else 493 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 494 495 ifp = &sc->sc_ethercom.ec_if; 496 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 497 ifp->if_softc = sc; 498 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 499 ifp->if_ioctl = ste_ioctl; 500 ifp->if_start = ste_start; 501 ifp->if_watchdog = ste_watchdog; 502 ifp->if_init = ste_init; 503 ifp->if_stop = ste_stop; 504 IFQ_SET_READY(&ifp->if_snd); 505 506 /* 507 * Default the transmit threshold to 128 bytes. 508 */ 509 sc->sc_txthresh = 128; 510 511 /* 512 * Disable MWI if the PCI layer tells us to. 513 */ 514 sc->sc_DMACtrl = 0; 515 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 516 sc->sc_DMACtrl |= DC_MWIDisable; 517 518 /* 519 * We can support 802.1Q VLAN-sized frames. 520 */ 521 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 522 523 /* 524 * Attach the interface. 525 */ 526 if_attach(ifp); 527 ether_ifattach(ifp, enaddr); 528 529 /* 530 * Make sure the interface is shutdown during reboot. 531 */ 532 sc->sc_sdhook = shutdownhook_establish(ste_shutdown, sc); 533 if (sc->sc_sdhook == NULL) 534 printf("%s: WARNING: unable to establish shutdown hook\n", 535 sc->sc_dev.dv_xname); 536 return; 537 538 /* 539 * Free any resources we've allocated during the failed attach 540 * attempt. Do this in reverse order and fall through. 541 */ 542 fail_5: 543 for (i = 0; i < STE_NRXDESC; i++) { 544 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 545 bus_dmamap_destroy(sc->sc_dmat, 546 sc->sc_rxsoft[i].ds_dmamap); 547 } 548 fail_4: 549 for (i = 0; i < STE_NTXDESC; i++) { 550 if (sc->sc_txsoft[i].ds_dmamap != NULL) 551 bus_dmamap_destroy(sc->sc_dmat, 552 sc->sc_txsoft[i].ds_dmamap); 553 } 554 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 555 fail_3: 556 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 557 fail_2: 558 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 559 sizeof(struct ste_control_data)); 560 fail_1: 561 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 562 fail_0: 563 return; 564 } 565 566 /* 567 * ste_shutdown: 568 * 569 * Make sure the interface is stopped at reboot time. 570 */ 571 void 572 ste_shutdown(void *arg) 573 { 574 struct ste_softc *sc = arg; 575 576 ste_stop(&sc->sc_ethercom.ec_if, 1); 577 } 578 579 static void 580 ste_dmahalt_wait(struct ste_softc *sc) 581 { 582 int i; 583 584 for (i = 0; i < STE_TIMEOUT; i++) { 585 delay(2); 586 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_DMACtrl) & 587 DC_DMAHaltBusy) == 0) 588 break; 589 } 590 591 if (i == STE_TIMEOUT) 592 printf("%s: DMA halt timed out\n", sc->sc_dev.dv_xname); 593 } 594 595 /* 596 * ste_start: [ifnet interface function] 597 * 598 * Start packet transmission on the interface. 599 */ 600 void 601 ste_start(struct ifnet *ifp) 602 { 603 struct ste_softc *sc = ifp->if_softc; 604 struct mbuf *m0, *m; 605 struct ste_descsoft *ds; 606 struct ste_tfd *tfd; 607 bus_dmamap_t dmamap; 608 int error, olasttx, nexttx, opending, seg, totlen; 609 610 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 611 return; 612 613 /* 614 * Remember the previous number of pending transmissions 615 * and the current last descriptor in the list. 616 */ 617 opending = sc->sc_txpending; 618 olasttx = sc->sc_txlast; 619 620 /* 621 * Loop through the send queue, setting up transmit descriptors 622 * until we drain the queue, or use up all available transmit 623 * descriptors. 624 */ 625 while (sc->sc_txpending < STE_NTXDESC) { 626 /* 627 * Grab a packet off the queue. 628 */ 629 IFQ_POLL(&ifp->if_snd, m0); 630 if (m0 == NULL) 631 break; 632 m = NULL; 633 634 /* 635 * Get the last and next available transmit descriptor. 636 */ 637 nexttx = STE_NEXTTX(sc->sc_txlast); 638 tfd = &sc->sc_txdescs[nexttx]; 639 ds = &sc->sc_txsoft[nexttx]; 640 641 dmamap = ds->ds_dmamap; 642 643 /* 644 * Load the DMA map. If this fails, the packet either 645 * didn't fit in the alloted number of segments, or we 646 * were short on resources. In this case, we'll copy 647 * and try again. 648 */ 649 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 650 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 651 MGETHDR(m, M_DONTWAIT, MT_DATA); 652 if (m == NULL) { 653 printf("%s: unable to allocate Tx mbuf\n", 654 sc->sc_dev.dv_xname); 655 break; 656 } 657 if (m0->m_pkthdr.len > MHLEN) { 658 MCLGET(m, M_DONTWAIT); 659 if ((m->m_flags & M_EXT) == 0) { 660 printf("%s: unable to allocate Tx " 661 "cluster\n", sc->sc_dev.dv_xname); 662 m_freem(m); 663 break; 664 } 665 } 666 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 667 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 668 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 669 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 670 if (error) { 671 printf("%s: unable to load Tx buffer, " 672 "error = %d\n", sc->sc_dev.dv_xname, error); 673 break; 674 } 675 } 676 677 IFQ_DEQUEUE(&ifp->if_snd, m0); 678 if (m != NULL) { 679 m_freem(m0); 680 m0 = m; 681 } 682 683 /* 684 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 685 */ 686 687 /* Sync the DMA map. */ 688 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 689 BUS_DMASYNC_PREWRITE); 690 691 /* Initialize the fragment list. */ 692 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 693 tfd->tfd_frags[seg].frag_addr = 694 htole32(dmamap->dm_segs[seg].ds_addr); 695 tfd->tfd_frags[seg].frag_len = 696 htole32(dmamap->dm_segs[seg].ds_len); 697 totlen += dmamap->dm_segs[seg].ds_len; 698 } 699 tfd->tfd_frags[seg - 1].frag_len |= htole32(FRAG_LAST); 700 701 /* Initialize the descriptor. */ 702 tfd->tfd_next = htole32(STE_CDTXADDR(sc, nexttx)); 703 tfd->tfd_control = htole32(TFD_FrameId(nexttx) | (totlen & 3)); 704 705 /* Sync the descriptor. */ 706 STE_CDTXSYNC(sc, nexttx, 707 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 708 709 /* 710 * Store a pointer to the packet so we can free it later, 711 * and remember what txdirty will be once the packet is 712 * done. 713 */ 714 ds->ds_mbuf = m0; 715 716 /* Advance the tx pointer. */ 717 sc->sc_txpending++; 718 sc->sc_txlast = nexttx; 719 720 #if NBPFILTER > 0 721 /* 722 * Pass the packet to any BPF listeners. 723 */ 724 if (ifp->if_bpf) 725 bpf_mtap(ifp->if_bpf, m0); 726 #endif /* NBPFILTER > 0 */ 727 } 728 729 if (sc->sc_txpending == STE_NTXDESC) { 730 /* No more slots left; notify upper layer. */ 731 ifp->if_flags |= IFF_OACTIVE; 732 } 733 734 if (sc->sc_txpending != opending) { 735 /* 736 * We enqueued packets. If the transmitter was idle, 737 * reset the txdirty pointer. 738 */ 739 if (opending == 0) 740 sc->sc_txdirty = STE_NEXTTX(olasttx); 741 742 /* 743 * Cause a descriptor interrupt to happen on the 744 * last packet we enqueued, and also cause the 745 * DMA engine to wait after is has finished processing 746 * it. 747 */ 748 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0; 749 sc->sc_txdescs[sc->sc_txlast].tfd_control |= 750 htole32(TFD_TxDMAIndicate); 751 STE_CDTXSYNC(sc, sc->sc_txlast, 752 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 753 754 /* 755 * Link up the new chain of descriptors to the 756 * last. 757 */ 758 sc->sc_txdescs[olasttx].tfd_next = 759 STE_CDTXADDR(sc, STE_NEXTTX(olasttx)); 760 STE_CDTXSYNC(sc, olasttx, 761 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 762 763 /* 764 * Kick the transmit DMA logic. Note that since we're 765 * using auto-polling, reading the Tx desc pointer will 766 * give it the nudge it needs to get going. 767 */ 768 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 769 STE_TxDMAListPtr) == 0) { 770 bus_space_write_4(sc->sc_st, sc->sc_sh, 771 STE_DMACtrl, DC_TxDMAHalt); 772 ste_dmahalt_wait(sc); 773 bus_space_write_4(sc->sc_st, sc->sc_sh, 774 STE_TxDMAListPtr, 775 STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 776 bus_space_write_4(sc->sc_st, sc->sc_sh, 777 STE_DMACtrl, DC_TxDMAResume); 778 } 779 780 /* Set a watchdog timer in case the chip flakes out. */ 781 ifp->if_timer = 5; 782 } 783 } 784 785 /* 786 * ste_watchdog: [ifnet interface function] 787 * 788 * Watchdog timer handler. 789 */ 790 void 791 ste_watchdog(struct ifnet *ifp) 792 { 793 struct ste_softc *sc = ifp->if_softc; 794 795 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 796 ifp->if_oerrors++; 797 798 (void) ste_init(ifp); 799 800 /* Try to get more packets going. */ 801 ste_start(ifp); 802 } 803 804 /* 805 * ste_ioctl: [ifnet interface function] 806 * 807 * Handle control requests from the operator. 808 */ 809 int 810 ste_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 811 { 812 struct ste_softc *sc = ifp->if_softc; 813 struct ifreq *ifr = (struct ifreq *)data; 814 int s, error; 815 816 s = splnet(); 817 818 switch (cmd) { 819 case SIOCSIFMEDIA: 820 case SIOCGIFMEDIA: 821 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 822 break; 823 824 default: 825 error = ether_ioctl(ifp, cmd, data); 826 if (error == ENETRESET) { 827 /* 828 * Multicast list has changed; set the hardware filter 829 * accordingly. 830 */ 831 ste_set_filter(sc); 832 error = 0; 833 } 834 break; 835 } 836 837 /* Try to get more packets going. */ 838 ste_start(ifp); 839 840 splx(s); 841 return (error); 842 } 843 844 /* 845 * ste_intr: 846 * 847 * Interrupt service routine. 848 */ 849 int 850 ste_intr(void *arg) 851 { 852 struct ste_softc *sc = arg; 853 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 854 uint16_t isr; 855 uint8_t txstat; 856 int wantinit; 857 858 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatus) & 859 IS_InterruptStatus) == 0) 860 return (0); 861 862 for (wantinit = 0; wantinit == 0;) { 863 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatusAck); 864 if ((isr & sc->sc_IntEnable) == 0) 865 break; 866 867 /* Receive interrupts. */ 868 if (isr & IE_RxDMAComplete) 869 ste_rxintr(sc); 870 871 /* Transmit interrupts. */ 872 if (isr & (IE_TxDMAComplete|IE_TxComplete)) 873 ste_txintr(sc); 874 875 /* Statistics overflow. */ 876 if (isr & IE_UpdateStats) 877 ste_stats_update(sc); 878 879 /* Transmission errors. */ 880 if (isr & IE_TxComplete) { 881 for (;;) { 882 txstat = bus_space_read_1(sc->sc_st, sc->sc_sh, 883 STE_TxStatus); 884 if ((txstat & TS_TxComplete) == 0) 885 break; 886 if (txstat & TS_TxUnderrun) { 887 sc->sc_txthresh += 32; 888 if (sc->sc_txthresh > 0x1ffc) 889 sc->sc_txthresh = 0x1ffc; 890 printf("%s: transmit underrun, new " 891 "threshold: %d bytes\n", 892 sc->sc_dev.dv_xname, 893 sc->sc_txthresh); 894 } 895 if (txstat & TS_TxReleaseError) 896 printf("%s: Tx FIFO release error\n", 897 sc->sc_dev.dv_xname); 898 if (txstat & TS_MaxCollisions) 899 printf("%s: excessive collisions\n", 900 sc->sc_dev.dv_xname); 901 bus_space_write_2(sc->sc_st, sc->sc_sh, 902 STE_TxStatus, 0); 903 } 904 wantinit = 1; 905 } 906 907 /* Host interface errors. */ 908 if (isr & IE_HostError) { 909 printf("%s: Host interface error\n", 910 sc->sc_dev.dv_xname); 911 wantinit = 1; 912 } 913 } 914 915 if (wantinit) 916 ste_init(ifp); 917 918 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 919 sc->sc_IntEnable); 920 921 /* Try to get more packets going. */ 922 ste_start(ifp); 923 924 return (1); 925 } 926 927 /* 928 * ste_txintr: 929 * 930 * Helper; handle transmit interrupts. 931 */ 932 void 933 ste_txintr(struct ste_softc *sc) 934 { 935 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 936 struct ste_descsoft *ds; 937 uint32_t control; 938 int i; 939 940 ifp->if_flags &= ~IFF_OACTIVE; 941 942 /* 943 * Go through our Tx list and free mbufs for those 944 * frames which have been transmitted. 945 */ 946 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 947 i = STE_NEXTTX(i), sc->sc_txpending--) { 948 ds = &sc->sc_txsoft[i]; 949 950 STE_CDTXSYNC(sc, i, 951 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 952 953 control = le32toh(sc->sc_txdescs[i].tfd_control); 954 if ((control & TFD_TxDMAComplete) == 0) 955 break; 956 957 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 958 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 959 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 960 m_freem(ds->ds_mbuf); 961 ds->ds_mbuf = NULL; 962 } 963 964 /* Update the dirty transmit buffer pointer. */ 965 sc->sc_txdirty = i; 966 967 /* 968 * If there are no more pending transmissions, cancel the watchdog 969 * timer. 970 */ 971 if (sc->sc_txpending == 0) 972 ifp->if_timer = 0; 973 } 974 975 /* 976 * ste_rxintr: 977 * 978 * Helper; handle receive interrupts. 979 */ 980 void 981 ste_rxintr(struct ste_softc *sc) 982 { 983 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 984 struct ste_descsoft *ds; 985 struct mbuf *m; 986 uint32_t status; 987 int i, len; 988 989 for (i = sc->sc_rxptr;; i = STE_NEXTRX(i)) { 990 ds = &sc->sc_rxsoft[i]; 991 992 STE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 993 994 status = le32toh(sc->sc_rxdescs[i].rfd_status); 995 996 if ((status & RFD_RxDMAComplete) == 0) 997 break; 998 999 /* 1000 * If the packet had an error, simply recycle the 1001 * buffer. Note, we count the error later in the 1002 * periodic stats update. 1003 */ 1004 if (status & RFD_RxFrameError) { 1005 STE_INIT_RXDESC(sc, i); 1006 continue; 1007 } 1008 1009 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1010 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1011 1012 /* 1013 * No errors; receive the packet. Note, we have 1014 * configured the chip to not include the CRC at 1015 * the end of the packet. 1016 */ 1017 len = RFD_RxDMAFrameLen(status); 1018 1019 /* 1020 * If the packet is small enough to fit in a 1021 * single header mbuf, allocate one and copy 1022 * the data into it. This greatly reduces 1023 * memory consumption when we receive lots 1024 * of small packets. 1025 * 1026 * Otherwise, we add a new buffer to the receive 1027 * chain. If this fails, we drop the packet and 1028 * recycle the old buffer. 1029 */ 1030 if (ste_copy_small != 0 && len <= (MHLEN - 2)) { 1031 MGETHDR(m, M_DONTWAIT, MT_DATA); 1032 if (m == NULL) 1033 goto dropit; 1034 m->m_data += 2; 1035 memcpy(mtod(m, caddr_t), 1036 mtod(ds->ds_mbuf, caddr_t), len); 1037 STE_INIT_RXDESC(sc, i); 1038 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1039 ds->ds_dmamap->dm_mapsize, 1040 BUS_DMASYNC_PREREAD); 1041 } else { 1042 m = ds->ds_mbuf; 1043 if (ste_add_rxbuf(sc, i) != 0) { 1044 dropit: 1045 ifp->if_ierrors++; 1046 STE_INIT_RXDESC(sc, i); 1047 bus_dmamap_sync(sc->sc_dmat, 1048 ds->ds_dmamap, 0, 1049 ds->ds_dmamap->dm_mapsize, 1050 BUS_DMASYNC_PREREAD); 1051 continue; 1052 } 1053 } 1054 1055 m->m_pkthdr.rcvif = ifp; 1056 m->m_pkthdr.len = m->m_len = len; 1057 1058 #if NBPFILTER > 0 1059 /* 1060 * Pass this up to any BPF listeners, but only 1061 * pass if up the stack if it's for us. 1062 */ 1063 if (ifp->if_bpf) 1064 bpf_mtap(ifp->if_bpf, m); 1065 #endif /* NBPFILTER > 0 */ 1066 1067 /* Pass it on. */ 1068 (*ifp->if_input)(ifp, m); 1069 } 1070 1071 /* Update the receive pointer. */ 1072 sc->sc_rxptr = i; 1073 } 1074 1075 /* 1076 * ste_tick: 1077 * 1078 * One second timer, used to tick the MII. 1079 */ 1080 void 1081 ste_tick(void *arg) 1082 { 1083 struct ste_softc *sc = arg; 1084 int s; 1085 1086 s = splnet(); 1087 mii_tick(&sc->sc_mii); 1088 ste_stats_update(sc); 1089 splx(s); 1090 1091 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1092 } 1093 1094 /* 1095 * ste_stats_update: 1096 * 1097 * Read the ST-201 statistics counters. 1098 */ 1099 void 1100 ste_stats_update(struct ste_softc *sc) 1101 { 1102 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1103 bus_space_tag_t st = sc->sc_st; 1104 bus_space_handle_t sh = sc->sc_sh; 1105 1106 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk0); 1107 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk1); 1108 1109 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk0); 1110 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk1); 1111 1112 ifp->if_opackets += 1113 (u_int) bus_space_read_2(st, sh, STE_FramesTransmittedOK); 1114 ifp->if_ipackets += 1115 (u_int) bus_space_read_2(st, sh, STE_FramesReceivedOK); 1116 1117 (void) bus_space_read_2(st, sh, STE_CarrierSenseErrors); 1118 1119 ifp->if_collisions += 1120 (u_int) bus_space_read_1(st, sh, STE_LateCollisions) + 1121 (u_int) bus_space_read_1(st, sh, STE_MultipleColFrames) + 1122 (u_int) bus_space_read_1(st, sh, STE_SingleColFrames); 1123 1124 (void) bus_space_read_1(st, sh, STE_FramesWDeferredXmt); 1125 1126 ifp->if_ierrors += 1127 (u_int) bus_space_read_1(st, sh, STE_FramesLostRxErrors); 1128 1129 ifp->if_oerrors += 1130 (u_int) bus_space_read_1(st, sh, STE_FramesWExDeferral) + 1131 (u_int) bus_space_read_1(st, sh, STE_FramesXbortXSColls); 1132 1133 (void) bus_space_read_1(st, sh, STE_BcstFramesXmtdOk); 1134 (void) bus_space_read_1(st, sh, STE_BcstFramesRcvdOk); 1135 (void) bus_space_read_1(st, sh, STE_McstFramesXmtdOk); 1136 (void) bus_space_read_1(st, sh, STE_McstFramesRcvdOk); 1137 } 1138 1139 /* 1140 * ste_reset: 1141 * 1142 * Perform a soft reset on the ST-201. 1143 */ 1144 void 1145 ste_reset(struct ste_softc *sc) 1146 { 1147 uint32_t ac; 1148 int i; 1149 1150 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl); 1151 1152 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl, 1153 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1154 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1155 AC_RstOut); 1156 1157 delay(50000); 1158 1159 for (i = 0; i < STE_TIMEOUT; i++) { 1160 delay(1000); 1161 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl) & 1162 AC_ResetBusy) == 0) 1163 break; 1164 } 1165 1166 if (i == STE_TIMEOUT) 1167 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1168 1169 delay(1000); 1170 } 1171 1172 /* 1173 * ste_init: [ ifnet interface function ] 1174 * 1175 * Initialize the interface. Must be called at splnet(). 1176 */ 1177 int 1178 ste_init(struct ifnet *ifp) 1179 { 1180 struct ste_softc *sc = ifp->if_softc; 1181 bus_space_tag_t st = sc->sc_st; 1182 bus_space_handle_t sh = sc->sc_sh; 1183 struct ste_descsoft *ds; 1184 int i, error = 0; 1185 1186 /* 1187 * Cancel any pending I/O. 1188 */ 1189 ste_stop(ifp, 0); 1190 1191 /* 1192 * Reset the chip to a known state. 1193 */ 1194 ste_reset(sc); 1195 1196 /* 1197 * Initialize the transmit descriptor ring. 1198 */ 1199 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1200 sc->sc_txpending = 0; 1201 sc->sc_txdirty = 0; 1202 sc->sc_txlast = STE_NTXDESC - 1; 1203 1204 /* 1205 * Initialize the receive descriptor and receive job 1206 * descriptor rings. 1207 */ 1208 for (i = 0; i < STE_NRXDESC; i++) { 1209 ds = &sc->sc_rxsoft[i]; 1210 if (ds->ds_mbuf == NULL) { 1211 if ((error = ste_add_rxbuf(sc, i)) != 0) { 1212 printf("%s: unable to allocate or map rx " 1213 "buffer %d, error = %d\n", 1214 sc->sc_dev.dv_xname, i, error); 1215 /* 1216 * XXX Should attempt to run with fewer receive 1217 * XXX buffers instead of just failing. 1218 */ 1219 ste_rxdrain(sc); 1220 goto out; 1221 } 1222 } else 1223 STE_INIT_RXDESC(sc, i); 1224 } 1225 sc->sc_rxptr = 0; 1226 1227 /* Set the station address. */ 1228 for (i = 0; i < ETHER_ADDR_LEN; i++) 1229 bus_space_write_1(st, sh, STE_StationAddress0 + 1, 1230 LLADDR(ifp->if_sadl)[i]); 1231 1232 /* Set up the receive filter. */ 1233 ste_set_filter(sc); 1234 1235 /* 1236 * Give the receive ring to the chip. 1237 */ 1238 bus_space_write_4(st, sh, STE_RxDMAListPtr, 1239 STE_CDRXADDR(sc, sc->sc_rxptr)); 1240 1241 /* 1242 * We defer giving the transmit ring to the chip until we 1243 * transmit the first packet. 1244 */ 1245 1246 /* 1247 * Initialize the Tx auto-poll period. It's OK to make this number 1248 * large (127 is the max) -- we explicitly kick the transmit engine 1249 * when there's actually a packet. We are using auto-polling only 1250 * to make the interface to the transmit engine not suck. 1251 */ 1252 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAPollPeriod, 127); 1253 1254 /* ..and the Rx auto-poll period. */ 1255 bus_space_write_1(st, sh, STE_RxDMAPollPeriod, 64); 1256 1257 /* Initialize the Tx start threshold. */ 1258 bus_space_write_2(st, sh, STE_TxStartThresh, sc->sc_txthresh); 1259 1260 /* Set the FIFO release threshold to 512 bytes. */ 1261 bus_space_write_1(st, sh, STE_TxReleaseThresh, 512 >> 4); 1262 1263 /* 1264 * Initialize the interrupt mask. 1265 */ 1266 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1267 IE_TxDMAComplete | IE_RxDMAComplete; 1268 bus_space_write_2(st, sh, STE_IntStatus, 0xffff); 1269 bus_space_write_2(st, sh, STE_IntEnable, sc->sc_IntEnable); 1270 1271 /* 1272 * Start the receive DMA engine. 1273 */ 1274 bus_space_write_4(st, sh, STE_DMACtrl, sc->sc_DMACtrl | DC_RxDMAResume); 1275 1276 /* 1277 * Initialize MacCtrl0 -- do it before setting the media, 1278 * as setting the media will actually program the register. 1279 */ 1280 sc->sc_MacCtrl0 = MC0_IFSSelect(0); 1281 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1282 sc->sc_MacCtrl0 |= MC0_RcvLargeFrames; 1283 1284 /* 1285 * Set the current media. 1286 */ 1287 mii_mediachg(&sc->sc_mii); 1288 1289 /* 1290 * Start the MAC. 1291 */ 1292 bus_space_write_2(st, sh, STE_MacCtrl1, 1293 MC1_StatisticsEnable | MC1_TxEnable | MC1_RxEnable); 1294 1295 /* 1296 * Start the one second MII clock. 1297 */ 1298 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1299 1300 /* 1301 * ...all done! 1302 */ 1303 ifp->if_flags |= IFF_RUNNING; 1304 ifp->if_flags &= ~IFF_OACTIVE; 1305 1306 out: 1307 if (error) 1308 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1309 return (error); 1310 } 1311 1312 /* 1313 * ste_drain: 1314 * 1315 * Drain the receive queue. 1316 */ 1317 void 1318 ste_rxdrain(struct ste_softc *sc) 1319 { 1320 struct ste_descsoft *ds; 1321 int i; 1322 1323 for (i = 0; i < STE_NRXDESC; i++) { 1324 ds = &sc->sc_rxsoft[i]; 1325 if (ds->ds_mbuf != NULL) { 1326 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1327 m_freem(ds->ds_mbuf); 1328 ds->ds_mbuf = NULL; 1329 } 1330 } 1331 } 1332 1333 /* 1334 * ste_stop: [ ifnet interface function ] 1335 * 1336 * Stop transmission on the interface. 1337 */ 1338 void 1339 ste_stop(struct ifnet *ifp, int disable) 1340 { 1341 struct ste_softc *sc = ifp->if_softc; 1342 struct ste_descsoft *ds; 1343 int i; 1344 1345 /* 1346 * Stop the one second clock. 1347 */ 1348 callout_stop(&sc->sc_tick_ch); 1349 1350 /* Down the MII. */ 1351 mii_down(&sc->sc_mii); 1352 1353 /* 1354 * Disable interrupts. 1355 */ 1356 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 0); 1357 1358 /* 1359 * Stop receiver, transmitter, and stats update. 1360 */ 1361 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, 1362 MC1_StatisticsDisable | MC1_TxDisable | MC1_RxDisable); 1363 1364 /* 1365 * Stop the transmit and receive DMA. 1366 */ 1367 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, 1368 DC_RxDMAHalt | DC_TxDMAHalt); 1369 ste_dmahalt_wait(sc); 1370 1371 /* 1372 * Release any queued transmit buffers. 1373 */ 1374 for (i = 0; i < STE_NTXDESC; i++) { 1375 ds = &sc->sc_txsoft[i]; 1376 if (ds->ds_mbuf != NULL) { 1377 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1378 m_freem(ds->ds_mbuf); 1379 ds->ds_mbuf = NULL; 1380 } 1381 } 1382 1383 if (disable) 1384 ste_rxdrain(sc); 1385 1386 /* 1387 * Mark the interface down and cancel the watchdog timer. 1388 */ 1389 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1390 ifp->if_timer = 0; 1391 } 1392 1393 static int 1394 ste_eeprom_wait(struct ste_softc *sc) 1395 { 1396 int i; 1397 1398 for (i = 0; i < STE_TIMEOUT; i++) { 1399 delay(1000); 1400 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl) & 1401 EC_EepromBusy) == 0) 1402 return (0); 1403 } 1404 return (1); 1405 } 1406 1407 /* 1408 * ste_read_eeprom: 1409 * 1410 * Read data from the serial EEPROM. 1411 */ 1412 void 1413 ste_read_eeprom(struct ste_softc *sc, int offset, uint16_t *data) 1414 { 1415 1416 if (ste_eeprom_wait(sc)) 1417 printf("%s: EEPROM failed to come ready\n", 1418 sc->sc_dev.dv_xname); 1419 1420 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl, 1421 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_R)); 1422 if (ste_eeprom_wait(sc)) 1423 printf("%s: EEPROM read timed out\n", 1424 sc->sc_dev.dv_xname); 1425 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromData); 1426 } 1427 1428 /* 1429 * ste_add_rxbuf: 1430 * 1431 * Add a receive buffer to the indicated descriptor. 1432 */ 1433 int 1434 ste_add_rxbuf(struct ste_softc *sc, int idx) 1435 { 1436 struct ste_descsoft *ds = &sc->sc_rxsoft[idx]; 1437 struct mbuf *m; 1438 int error; 1439 1440 MGETHDR(m, M_DONTWAIT, MT_DATA); 1441 if (m == NULL) 1442 return (ENOBUFS); 1443 1444 MCLGET(m, M_DONTWAIT); 1445 if ((m->m_flags & M_EXT) == 0) { 1446 m_freem(m); 1447 return (ENOBUFS); 1448 } 1449 1450 if (ds->ds_mbuf != NULL) 1451 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1452 1453 ds->ds_mbuf = m; 1454 1455 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1456 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1457 BUS_DMA_READ|BUS_DMA_NOWAIT); 1458 if (error) { 1459 printf("%s: can't load rx DMA map %d, error = %d\n", 1460 sc->sc_dev.dv_xname, idx, error); 1461 panic("ste_add_rxbuf"); /* XXX */ 1462 } 1463 1464 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1465 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1466 1467 STE_INIT_RXDESC(sc, idx); 1468 1469 return (0); 1470 } 1471 1472 /* 1473 * ste_set_filter: 1474 * 1475 * Set up the receive filter. 1476 */ 1477 void 1478 ste_set_filter(struct ste_softc *sc) 1479 { 1480 struct ethercom *ec = &sc->sc_ethercom; 1481 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1482 struct ether_multi *enm; 1483 struct ether_multistep step; 1484 uint32_t crc; 1485 uint16_t mchash[4]; 1486 1487 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1488 if (ifp->if_flags & IFF_BROADCAST) 1489 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1490 1491 if (ifp->if_flags & IFF_PROMISC) { 1492 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1493 goto allmulti; 1494 } 1495 1496 /* 1497 * Set up the multicast address filter by passing all multicast 1498 * addresses through a CRC generator, and then using the low-order 1499 * 6 bits as an index into the 64 bit multicast hash table. The 1500 * high order bits select the register, while the rest of the bits 1501 * select the bit within the register. 1502 */ 1503 1504 memset(mchash, 0, sizeof(mchash)); 1505 1506 ETHER_FIRST_MULTI(step, ec, enm); 1507 if (enm == NULL) 1508 goto done; 1509 1510 while (enm != NULL) { 1511 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1512 /* 1513 * We must listen to a range of multicast addresses. 1514 * For now, just accept all multicasts, rather than 1515 * trying to set only those filter bits needed to match 1516 * the range. (At this time, the only use of address 1517 * ranges is for IP multicast routing, for which the 1518 * range is big enough to require all bits set.) 1519 */ 1520 goto allmulti; 1521 } 1522 1523 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1524 1525 /* Just want the 6 least significant bits. */ 1526 crc &= 0x3f; 1527 1528 /* Set the corresponding bit in the hash table. */ 1529 mchash[crc >> 4] |= 1 << (crc & 0xf); 1530 1531 ETHER_NEXT_MULTI(step, enm); 1532 } 1533 1534 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1535 1536 ifp->if_flags &= ~IFF_ALLMULTI; 1537 goto done; 1538 1539 allmulti: 1540 ifp->if_flags |= IFF_ALLMULTI; 1541 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1542 1543 done: 1544 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1545 /* 1546 * Program the multicast hash table. 1547 */ 1548 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable0, 1549 mchash[0]); 1550 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable1, 1551 mchash[1]); 1552 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable2, 1553 mchash[2]); 1554 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable3, 1555 mchash[3]); 1556 } 1557 1558 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_ReceiveMode, 1559 sc->sc_ReceiveMode); 1560 } 1561 1562 /* 1563 * ste_mii_readreg: [mii interface function] 1564 * 1565 * Read a PHY register on the MII of the ST-201. 1566 */ 1567 int 1568 ste_mii_readreg(struct device *self, int phy, int reg) 1569 { 1570 1571 return (mii_bitbang_readreg(self, &ste_mii_bitbang_ops, phy, reg)); 1572 } 1573 1574 /* 1575 * ste_mii_writereg: [mii interface function] 1576 * 1577 * Write a PHY register on the MII of the ST-201. 1578 */ 1579 void 1580 ste_mii_writereg(struct device *self, int phy, int reg, int val) 1581 { 1582 1583 mii_bitbang_writereg(self, &ste_mii_bitbang_ops, phy, reg, val); 1584 } 1585 1586 /* 1587 * ste_mii_statchg: [mii interface function] 1588 * 1589 * Callback from MII layer when media changes. 1590 */ 1591 void 1592 ste_mii_statchg(struct device *self) 1593 { 1594 struct ste_softc *sc = (struct ste_softc *) self; 1595 1596 if (sc->sc_mii.mii_media_active & IFM_FDX) 1597 sc->sc_MacCtrl0 |= MC0_FullDuplexEnable; 1598 else 1599 sc->sc_MacCtrl0 &= ~MC0_FullDuplexEnable; 1600 1601 /* XXX 802.1x flow-control? */ 1602 1603 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl0, sc->sc_MacCtrl0); 1604 } 1605 1606 /* 1607 * ste_mii_bitbang_read: [mii bit-bang interface function] 1608 * 1609 * Read the MII serial port for the MII bit-bang module. 1610 */ 1611 uint32_t 1612 ste_mii_bitbang_read(struct device *self) 1613 { 1614 struct ste_softc *sc = (void *) self; 1615 1616 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl)); 1617 } 1618 1619 /* 1620 * ste_mii_bitbang_write: [mii big-bang interface function] 1621 * 1622 * Write the MII serial port for the MII bit-bang module. 1623 */ 1624 void 1625 ste_mii_bitbang_write(struct device *self, uint32_t val) 1626 { 1627 struct ste_softc *sc = (void *) self; 1628 1629 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl, val); 1630 } 1631 1632 /* 1633 * ste_mediastatus: [ifmedia interface function] 1634 * 1635 * Get the current interface media status. 1636 */ 1637 void 1638 ste_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1639 { 1640 struct ste_softc *sc = ifp->if_softc; 1641 1642 mii_pollstat(&sc->sc_mii); 1643 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1644 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1645 } 1646 1647 /* 1648 * ste_mediachange: [ifmedia interface function] 1649 * 1650 * Set hardware to newly-selected media. 1651 */ 1652 int 1653 ste_mediachange(struct ifnet *ifp) 1654 { 1655 struct ste_softc *sc = ifp->if_softc; 1656 1657 if (ifp->if_flags & IFF_UP) 1658 mii_mediachg(&sc->sc_mii); 1659 return (0); 1660 } 1661