1 /* $NetBSD: if_stereg.h,v 1.2 2002/05/03 00:19:12 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _DEV_PCI_IF_STEREG_H_ 40 #define _DEV_PCI_IF_STEREG_H_ 41 42 /* 43 * Register description for the Sundance Tech. ST-201 10/100 44 * Ethernet controller. 45 */ 46 47 /* 48 * ST-201 buffer fragment descriptor. 49 */ 50 struct ste_frag { 51 uint32_t frag_addr; /* buffer address */ 52 uint32_t frag_len; /* buffer length */ 53 } __attribute__((__packed__)); 54 55 #define FRAG_LEN 0x00001fff /* length mask */ 56 #define FRAG_LAST (1U << 31) /* last frag in list */ 57 58 /* 59 * ST-201 Transmit Frame Descriptor. Note the number of fragments 60 * here is arbitrary, but we can't exceed 512 bytes of TFD. 61 */ 62 #define STE_NTXFRAGS 16 63 struct ste_tfd { 64 uint32_t tfd_next; /* next TFD in list */ 65 uint32_t tfd_control; /* control bits */ 66 /* the buffer fragments */ 67 struct ste_frag tfd_frags[STE_NTXFRAGS]; 68 } __attribute__((__packed__)); 69 70 #define TFD_WordAlign_dword 0 /* align to dword in TxFIFO */ 71 #define TFD_WordAlign_word 2 /* align to word in TxFIFO */ 72 #define TFD_WordAlign_disable 1 /* disable alignment */ 73 #define TFD_FrameId(x) ((x) << 2) 74 #define TFD_FrameId_MAX 0xff 75 #define TFD_FcsAppendDisable (1U << 13) 76 #define TFD_TxIndicate (1U << 15) 77 #define TFD_TxDMAComplete (1U << 16) 78 #define TFD_TxDMAIndicate (1U << 31) 79 80 /* 81 * ST-201 Receive Frame Descriptor. Note the number of fragments 82 * here is arbitrary (we only use one), but we can't exceed 512 83 * bytes of RFD. 84 */ 85 struct ste_rfd { 86 uint32_t rfd_next; /* next RFD in list */ 87 uint32_t rfd_status; /* status bits */ 88 struct ste_frag rfd_frag; /* the buffer */ 89 } __attribute__((__packed__)); 90 91 #define RFD_RxDMAFrameLen(x) ((x) & FRAG_LEN) 92 #define RFD_RxFrameError (1U << 14) 93 #define RFD_RxDMAComplete (1U << 15) 94 #define RFD_RxFIFOOverrun (1U << 16) 95 #define RFD_RxRuntFrame (1U << 17) 96 #define RFD_RxAlignmentError (1U << 18) 97 #define RFD_RxFCSError (1U << 19) 98 #define RFD_RxOversizedFrame (1U << 20) 99 #define RFD_DribbleBits (1U << 23) 100 #define RFD_RxDMAOverflow (1U << 24) 101 #define RFD_ImpliedBufferEnable (1U << 28) 102 103 /* 104 * PCI configuration registers used by the ST-201. 105 */ 106 107 #define STE_PCI_IOBA (PCI_MAPREG_START + 0x00) 108 #define STE_PCI_MMBA (PCI_MAPREG_START + 0x04) 109 110 /* 111 * EEPROM offsets. 112 */ 113 #define STE_EEPROM_ConfigParam 0x00 114 #define STE_EEPROM_AsicCtrl 0x02 115 #define STE_EEPROM_SubSystemVendorId 0x04 116 #define STE_EEPROM_SubSystemId 0x06 117 #define STE_EEPROM_StationAddress0 0x10 118 #define STE_EEPROM_StationAddress1 0x12 119 #define STE_EEPROM_StationAddress2 0x14 120 121 /* 122 * The ST-201 register space. 123 */ 124 125 #define STE_DMACtrl 0x00 /* 32-bit */ 126 #define DC_RxDMAHalted (1U << 0) 127 #define DC_TxDMACmplReq (1U << 1) 128 #define DC_TxDMAHalted (1U << 2) 129 #define DC_RxDMAComplete (1U << 3) 130 #define DC_TxDMAComplete (1U << 4) 131 #define DC_RxDMAHalt (1U << 8) 132 #define DC_RxDMAResume (1U << 9) 133 #define DC_TxDMAHalt (1U << 10) 134 #define DC_TxDMAResume (1U << 11) 135 #define DC_TxDMAInProg (1U << 14) 136 #define DC_DMAHaltBusy (1U << 15) 137 #define DC_RxEarlyEnable (1U << 17) 138 #define DC_CountdownSpeed (1U << 18) 139 #define DC_CountdownMode (1U << 19) 140 #define DC_MWIDisable (1U << 20) 141 #define DC_RxDMAOverrunFrame (1U << 22) 142 #define DC_CountdownIntEnable (1U << 23) 143 #define DC_TargetAbort (1U << 30) 144 #define DC_MasterAbort (1U << 31) 145 146 #define STE_TxDMAListPtr 0x04 /* 32-bit */ 147 148 #define STE_TxDMABurstThresh 0x08 /* 8-bit */ 149 150 #define STE_TxDMAUrgentThresh 0x09 /* 8-bit */ 151 152 #define STE_TxDMAPollPeriod 0x0a /* 8-bit */ 153 154 #define STE_RxDMAStatus 0x0c /* 32-bit */ 155 #define RDS_RxDMAFrameLen(x) ((x) & 0x1fff) 156 #define RDS_RxFrameError (1U << 14) 157 #define RDS_RxDMAComplete (1U << 15) 158 #define RDS_RxFIFOOverrun (1U << 16) 159 #define RDS_RxRuntFrame (1U << 17) 160 #define RDS_RxAlignmentError (1U << 18) 161 #define RDS_RxFCSError (1U << 19) 162 #define RDS_RxOversizedFrame (1U << 20) 163 #define RDS_DribbleBits (1U << 23) 164 #define RDS_RxDMAOverflow (1U << 24) 165 166 #define STE_RxDMAListPtr 0x10 /* 32-bit */ 167 168 #define STE_RxDMABrustThresh 0x14 /* 8-bit */ 169 170 #define STE_RxDMAUrgentThresh 0x15 /* 8-bit */ 171 172 #define STE_RxDMAPollPeriod 0x16 /* 8-bit */ 173 174 #define STE_DebugCtrl 0x1a /* 16-bit */ 175 #define DC_GPIO0Ctrl (1U << 0) /* 1 = input */ 176 #define DC_GPIO1Ctrl (1U << 1) /* 1 = input */ 177 #define DC_GPIO0 (1U << 2) 178 #define DC_GPIO1 (1U << 3) 179 180 #define STE_AsicCtrl 0x30 /* 32-bit */ 181 #define AC_ExpRomSize (1U << 1) /* 0 = 32K, 1 = 64K */ 182 #define AC_TxLargeEnable (1U << 2) /* > 2K */ 183 #define AC_RxLargeEnable (1U << 3) /* > 2K */ 184 #define AC_ExpRomDisable (1U << 4) 185 #define AC_PhySpeed10 (1U << 5) 186 #define AC_PhySpeed100 (1U << 6) 187 #define AC_PhyMedia(x) (((x) >> 7) & 0x7) 188 #define AC_PhyMedia_10T 1 189 #define AC_PhyMedia_100T 2 190 #define AC_PhyMedia_10_100T 3 191 #define AC_PhyMedia_10F 5 192 #define AC_PhyMedia_100F 6 193 #define AC_PhyMedia_10_100F 7 194 #define AC_ForcedConfig(x) (((x) >> 8) & 0x7) 195 #define AC_D3ResetDisable (1U << 11) 196 #define AC_SpeedupMode (1U << 13) 197 #define AC_LEDMode (1U << 14) 198 #define AC_RstOutPolarity (1U << 15) 199 #define AC_GlobalReset (1U << 16) 200 #define AC_RxReset (1U << 17) 201 #define AC_TxReset (1U << 18) 202 #define AC_DMA (1U << 19) 203 #define AC_FIFO (1U << 20) 204 #define AC_Network (1U << 21) 205 #define AC_Host (1U << 22) 206 #define AC_AutoInit (1U << 23) 207 #define AC_RstOut (1U << 24) 208 #define AC_InterruptRequest (1U << 25) 209 #define AC_ResetBusy (1U << 26) 210 211 #define STE_EepromData 0x34 /* 16-bit */ 212 213 #define STE_EepromCtrl 0x36 /* 16-bit */ 214 #define EC_EepromAddress(x) ((x) & 0xff) 215 #define EC_EepromOpcode(x) ((x) << 8) 216 #define EC_OP_WE 0 217 #define EC_OP_W 1 218 #define EC_OP_R 2 219 #define EC_OP_E 3 220 #define EC_EepromBusy (1U << 15) 221 222 #define STE_FIFOCtrl 0x3a /* 16-bit */ 223 #define FC_RAMTestMode (1U << 0) 224 #define FC_RxOverrunFrame (1U << 9) 225 #define FC_RxFIFOFull (1U << 11) 226 #define FC_Transmitting (1U << 14) 227 #define FC_Receiving (1U << 15) 228 229 #define STE_TxStartThresh 0x3c /* 16-bit */ 230 231 #define STE_RxEarlyThresh 0x3e /* 16-bit */ 232 233 #define STE_ExpRomAddr 0x40 /* 32-bit */ 234 235 #define STE_ExpRomData 0x44 /* 8-bit */ 236 237 #define STE_WakeEvent 0x45 /* 8-bit */ 238 #define WE_WakePktEnable (1U << 0) 239 #define WE_MagicPktEnable (1U << 1) 240 #define WE_LinkEventEnable (1U << 2) 241 #define WE_WakePolarity (1U << 3) 242 #define WE_WakePktEvent (1U << 4) 243 #define WE_MagicPktEvent (1U << 5) 244 #define WE_LinkEvent (1U << 6) 245 #define WE_WakeOnLanEnable (1U << 7) 246 247 #define STE_TxStatus 0x46 /* 8-bit */ 248 #define TS_TxReleaseError (1U << 1) 249 #define TS_TxStatusOverflow (1U << 2) 250 #define TS_MaxCollisions (1U << 3) 251 #define TS_TxUnderrun (1U << 4) 252 #define TS_TxIndicateReqd (1U << 6) 253 #define TS_TxComplete (1U << 7) 254 255 #define STE_TxFrameId 0x47 /* 8-bit */ 256 257 #define STE_Countdown 0x48 /* 16-bit */ 258 259 #define STE_IntStatusAck 0x4a /* 16-bit */ 260 261 #define STE_IntEnable 0x4c /* 16-bit */ 262 #define IE_HostError (1U << 1) 263 #define IE_TxComplete (1U << 2) 264 #define IE_MACControlFrame (1U << 3) 265 #define IE_RxComplete (1U << 4) 266 #define IE_RxEarly (1U << 5) 267 #define IE_IntRequested (1U << 6) 268 #define IE_UpdateStats (1U << 7) 269 #define IE_LinkEvent (1U << 8) 270 #define IE_TxDMAComplete (1U << 9) 271 #define IE_RxDMAComplete (1U << 10) 272 273 #define STE_IntStatus 0x4e /* 16-bit */ 274 #define IS_InterruptStatus (1U << 0) 275 276 #define STE_MacCtrl0 0x50 /* 16-bit */ 277 #define MC0_IFSSelect(x) ((x) << 0) 278 #define MC0_FullDuplexEnable (1U << 5) 279 #define MC0_RcvLargeFrames (1U << 6) 280 #define MC0_FlowControlEnable (1U << 8) 281 #define MC0_RcvFCS (1U << 9) 282 #define MC0_FIFOLoopback (1U << 10) 283 #define MC0_MACLoopback (1U << 11) 284 285 #define STE_MacCtrl1 0x52 /* 16-bit */ 286 #define MC1_CollsionDetect (1U << 0) 287 #define MC1_CarrierSense (1U << 1) 288 #define MC1_TxInProg (1U << 2) 289 #define MC1_TxError (1U << 3) 290 #define MC1_StatisticsEnable (1U << 5) 291 #define MC1_StatisticsDisable (1U << 6) 292 #define MC1_StatisticsEnabled (1U << 7) 293 #define MC1_TxEnable (1U << 8) 294 #define MC1_TxDisable (1U << 9) 295 #define MC1_TxEnabled (1U << 10) 296 #define MC1_RxEnable (1U << 11) 297 #define MC1_RxDisable (1U << 12) 298 #define MC1_RxEnabled (1U << 13) 299 #define MC1_Paused (1U << 14) 300 301 #define STE_StationAddress0 0x54 /* 16-bit */ 302 303 #define STE_StationAddress1 0x56 /* 16-bit */ 304 305 #define STE_StationAddress2 0x58 /* 16-bit */ 306 307 #define STE_MaxFrameSize 0x5a /* 16-bit */ 308 309 #define STE_ReceiveMode 0x5c /* 8-bit */ 310 #define RM_ReceiveUnicast (1U << 0) 311 #define RM_ReceiveMulticast (1U << 1) 312 #define RM_ReceiveBroadcast (1U << 2) 313 #define RM_ReceiveAllFrames (1U << 3) 314 #define RM_ReceiveMulticastHash (1U << 4) 315 #define RM_ReceiveIPMulticast (1U << 5) 316 317 #define STE_TxReleaseThresh 0x5d /* 8-bit */ 318 319 #define STE_PhyCtrl 0x5e /* 8-bit */ 320 #define PC_MgmtClk (1U << 0) 321 #define PC_MgmtData (1U << 1) 322 #define PC_MgmtDir (1U << 2) /* 1 = MAC->Phy */ 323 #define PC_DisableClk25 (1U << 3) 324 #define PC_PhyDuplexPolarity (1U << 4) 325 #define PC_PhyDuplexStatus (1U << 5) 326 #define PC_PhySpeedStatus (1U << 6) 327 #define PC_PhyLinkStatus (1U << 7) 328 329 #define STE_HashTable0 0x60 /* 16-bit */ 330 331 #define STE_HashTable1 0x62 /* 16-bit */ 332 333 #define STE_HashTable2 0x64 /* 16-bit */ 334 335 #define STE_HashTable3 0x66 /* 16-bit */ 336 337 #define STE_OctetsReceivedOk0 0x68 /* 16-bit */ 338 339 #define STE_OctetsReceivedOk1 0x6a /* 16-bit */ 340 341 #define STE_OctetsTransmittedOk0 0x6c /* 16-bit */ 342 343 #define STE_OctetsTransmittedOk1 0x6e /* 16-bit */ 344 345 #define STE_FramesTransmittedOK 0x70 /* 16-bit */ 346 347 #define STE_FramesReceivedOK 0x72 /* 16-bit */ 348 349 #define STE_CarrierSenseErrors 0x74 /* 8-bit */ 350 351 #define STE_LateCollisions 0x75 /* 8-bit */ 352 353 #define STE_MultipleColFrames 0x76 /* 8-bit */ 354 355 #define STE_SingleColFrames 0x77 /* 8-bit */ 356 357 #define STE_FramesWDeferredXmt 0x78 /* 8-bit */ 358 359 #define STE_FramesLostRxErrors 0x79 /* 8-bit */ 360 361 #define STE_FramesWExDeferral 0x7a /* 8-bit */ 362 363 #define STE_FramesXbortXSColls 0x7b /* 8-bit */ 364 365 #define STE_BcstFramesXmtdOk 0x7c /* 8-bit */ 366 367 #define STE_BcstFramesRcvdOk 0x7d /* 8-bit */ 368 369 #define STE_McstFramesXmtdOk 0x7e /* 8-bit */ 370 371 #define STE_McstFramesRcvdOk 0x7f /* 8-bit */ 372 373 #endif /* _DEV_PCI_IF_STEREG_H_ */ 374