1 /* $NetBSD: if_stge.c,v 1.9 2001/11/13 07:48:44 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the Sundance Tech. TC9021 10/100/1000 41 * Ethernet controller. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.9 2001/11/13 07:48:44 lukem Exp $"); 46 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/callout.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 #include <sys/queue.h> 60 61 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/if_ether.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 72 #include <machine/bus.h> 73 #include <machine/intr.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 #include <dev/mii/mii_bitbang.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcidevs.h> 82 83 #include <dev/pci/if_stgereg.h> 84 85 /* 86 * Transmit descriptor list size. 87 */ 88 #define STGE_NTXDESC 256 89 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 90 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 91 92 /* 93 * Receive descriptor list size. 94 */ 95 #define STGE_NRXDESC 256 96 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 97 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 98 99 /* 100 * Only interrupt every N frames. Must be a power-of-two. 101 */ 102 #define STGE_TXINTR_SPACING 16 103 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 104 105 /* 106 * Control structures are DMA'd to the TC9021 chip. We allocate them in 107 * a single clump that maps to a single DMA segment to make several things 108 * easier. 109 */ 110 struct stge_control_data { 111 /* 112 * The transmit descriptors. 113 */ 114 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 115 116 /* 117 * The receive descriptors. 118 */ 119 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 120 }; 121 122 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 123 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 124 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 125 126 /* 127 * Software state for transmit and receive jobs. 128 */ 129 struct stge_descsoft { 130 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 131 bus_dmamap_t ds_dmamap; /* our DMA map */ 132 }; 133 134 /* 135 * Software state per device. 136 */ 137 struct stge_softc { 138 struct device sc_dev; /* generic device information */ 139 bus_space_tag_t sc_st; /* bus space tag */ 140 bus_space_handle_t sc_sh; /* bus space handle */ 141 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 142 struct ethercom sc_ethercom; /* ethernet common data */ 143 void *sc_sdhook; /* shutdown hook */ 144 int sc_rev; /* silicon revision */ 145 146 void *sc_ih; /* interrupt cookie */ 147 148 struct mii_data sc_mii; /* MII/media information */ 149 150 struct callout sc_tick_ch; /* tick callout */ 151 152 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 153 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 154 155 /* 156 * Software state for transmit and receive descriptors. 157 */ 158 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 159 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 160 161 /* 162 * Control data structures. 163 */ 164 struct stge_control_data *sc_control_data; 165 #define sc_txdescs sc_control_data->scd_txdescs 166 #define sc_rxdescs sc_control_data->scd_rxdescs 167 168 #ifdef STGE_EVENT_COUNTERS 169 /* 170 * Event counters. 171 */ 172 struct evcnt sc_ev_txstall; /* Tx stalled */ 173 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 174 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 175 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 176 177 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 178 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 179 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 180 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 181 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 182 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 183 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 184 185 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 186 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 187 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 188 189 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 190 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 191 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 192 #endif /* STGE_EVENT_COUNTERS */ 193 194 int sc_txpending; /* number of Tx requests pending */ 195 int sc_txdirty; /* first dirty Tx descriptor */ 196 int sc_txlast; /* last used Tx descriptor */ 197 198 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 199 int sc_rxdiscard; 200 int sc_rxlen; 201 struct mbuf *sc_rxhead; 202 struct mbuf *sc_rxtail; 203 struct mbuf **sc_rxtailp; 204 205 int sc_txthresh; /* Tx threshold */ 206 int sc_usefiber; /* if we're fiber */ 207 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 208 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 209 uint16_t sc_IntEnable; /* prototype IntEnable register */ 210 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 211 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 212 }; 213 214 #define STGE_RXCHAIN_RESET(sc) \ 215 do { \ 216 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 217 *(sc)->sc_rxtailp = NULL; \ 218 (sc)->sc_rxlen = 0; \ 219 } while (/*CONSTCOND*/0) 220 221 #define STGE_RXCHAIN_LINK(sc, m) \ 222 do { \ 223 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 224 (sc)->sc_rxtailp = &(m)->m_next; \ 225 } while (/*CONSTCOND*/0) 226 227 #ifdef STGE_EVENT_COUNTERS 228 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 229 #else 230 #define STGE_EVCNT_INCR(ev) /* nothing */ 231 #endif 232 233 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 234 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 235 236 #define STGE_CDTXSYNC(sc, x, ops) \ 237 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 238 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 239 240 #define STGE_CDRXSYNC(sc, x, ops) \ 241 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 242 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 243 244 #define STGE_INIT_RXDESC(sc, x) \ 245 do { \ 246 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 247 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 248 \ 249 /* \ 250 * Note: We scoot the packet forward 2 bytes in the buffer \ 251 * so that the payload after the Ethernet header is aligned \ 252 * to a 4-byte boundary. \ 253 */ \ 254 __rfd->rfd_frag.frag_word0 = \ 255 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 256 FRAG_LEN(MCLBYTES - 2)); \ 257 __rfd->rfd_next = \ 258 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 259 __rfd->rfd_status = 0; \ 260 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 261 } while (/*CONSTCOND*/0) 262 263 #define STGE_TIMEOUT 1000 264 265 void stge_start(struct ifnet *); 266 void stge_watchdog(struct ifnet *); 267 int stge_ioctl(struct ifnet *, u_long, caddr_t); 268 int stge_init(struct ifnet *); 269 void stge_stop(struct ifnet *, int); 270 271 void stge_shutdown(void *); 272 273 void stge_reset(struct stge_softc *); 274 void stge_rxdrain(struct stge_softc *); 275 int stge_add_rxbuf(struct stge_softc *, int); 276 #if 0 277 void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 278 #endif 279 void stge_tick(void *); 280 281 void stge_stats_update(struct stge_softc *); 282 283 void stge_set_filter(struct stge_softc *); 284 285 int stge_intr(void *); 286 void stge_txintr(struct stge_softc *); 287 void stge_rxintr(struct stge_softc *); 288 289 int stge_mii_readreg(struct device *, int, int); 290 void stge_mii_writereg(struct device *, int, int, int); 291 void stge_mii_statchg(struct device *); 292 293 int stge_mediachange(struct ifnet *); 294 void stge_mediastatus(struct ifnet *, struct ifmediareq *); 295 296 int stge_match(struct device *, struct cfdata *, void *); 297 void stge_attach(struct device *, struct device *, void *); 298 299 int stge_copy_small = 0; 300 301 struct cfattach stge_ca = { 302 sizeof(struct stge_softc), stge_match, stge_attach, 303 }; 304 305 uint32_t stge_mii_bitbang_read(struct device *); 306 void stge_mii_bitbang_write(struct device *, uint32_t); 307 308 const struct mii_bitbang_ops stge_mii_bitbang_ops = { 309 stge_mii_bitbang_read, 310 stge_mii_bitbang_write, 311 { 312 PC_MgmtData, /* MII_BIT_MDO */ 313 PC_MgmtData, /* MII_BIT_MDI */ 314 PC_MgmtClk, /* MII_BIT_MDC */ 315 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 316 0, /* MII_BIT_DIR_PHY_HOST */ 317 } 318 }; 319 320 /* 321 * Devices supported by this driver. 322 */ 323 const struct stge_product { 324 pci_vendor_id_t stge_vendor; 325 pci_product_id_t stge_product; 326 const char *stge_name; 327 } stge_products[] = { 328 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 329 "Sundance ST-2021 Gigabit Ethernet" }, 330 331 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 332 "Tamarack TC9021 Gigabit Ethernet" }, 333 334 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 335 "Tamarack TC9021 Gigabit Ethernet" }, 336 337 /* 338 * The Sundance sample boards use the Sundance vendor ID, 339 * but the Tamarack product ID. 340 */ 341 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 342 "Sundance TC9021 Gigabit Ethernet" }, 343 344 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 345 "Sundance TC9021 Gigabit Ethernet" }, 346 347 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 348 "D-Link DL-4000 Gigabit Ethernet" }, 349 350 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 351 "Antares Gigabit Ethernet" }, 352 353 { 0, 0, 354 NULL }, 355 }; 356 357 static const struct stge_product * 358 stge_lookup(const struct pci_attach_args *pa) 359 { 360 const struct stge_product *sp; 361 362 for (sp = stge_products; sp->stge_name != NULL; sp++) { 363 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 364 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 365 return (sp); 366 } 367 return (NULL); 368 } 369 370 int 371 stge_match(struct device *parent, struct cfdata *cf, void *aux) 372 { 373 struct pci_attach_args *pa = aux; 374 375 if (stge_lookup(pa) != NULL) 376 return (1); 377 378 return (0); 379 } 380 381 void 382 stge_attach(struct device *parent, struct device *self, void *aux) 383 { 384 struct stge_softc *sc = (struct stge_softc *) self; 385 struct pci_attach_args *pa = aux; 386 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 387 pci_chipset_tag_t pc = pa->pa_pc; 388 pci_intr_handle_t ih; 389 const char *intrstr = NULL; 390 bus_space_tag_t iot, memt; 391 bus_space_handle_t ioh, memh; 392 bus_dma_segment_t seg; 393 int ioh_valid, memh_valid; 394 int i, rseg, error; 395 const struct stge_product *sp; 396 pcireg_t pmode; 397 uint8_t enaddr[ETHER_ADDR_LEN]; 398 int pmreg; 399 400 callout_init(&sc->sc_tick_ch); 401 402 sp = stge_lookup(pa); 403 if (sp == NULL) { 404 printf("\n"); 405 panic("ste_attach: impossible"); 406 } 407 408 sc->sc_rev = PCI_REVISION(pa->pa_class); 409 410 printf(": %s, rev. %d\n", sp->stge_name, sc->sc_rev); 411 412 /* 413 * Map the device. 414 */ 415 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 416 PCI_MAPREG_TYPE_IO, 0, 417 &iot, &ioh, NULL, NULL) == 0); 418 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 419 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 420 &memt, &memh, NULL, NULL) == 0); 421 422 if (memh_valid) { 423 sc->sc_st = memt; 424 sc->sc_sh = memh; 425 } else if (ioh_valid) { 426 sc->sc_st = iot; 427 sc->sc_sh = ioh; 428 } else { 429 printf("%s: unable to map device registers\n", 430 sc->sc_dev.dv_xname); 431 return; 432 } 433 434 sc->sc_dmat = pa->pa_dmat; 435 436 /* Enable bus mastering. */ 437 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 438 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 439 PCI_COMMAND_MASTER_ENABLE); 440 441 /* Get it out of power save mode if needed. */ 442 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 443 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 444 if (pmode == 3) { 445 /* 446 * The card has lost all configuration data in 447 * this state, so punt. 448 */ 449 printf("%s: unable to wake up from power state D3\n", 450 sc->sc_dev.dv_xname); 451 return; 452 } 453 if (pmode != 0) { 454 printf("%s: waking up from power state D%d\n", 455 sc->sc_dev.dv_xname, pmode); 456 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 457 } 458 } 459 460 /* 461 * Map and establish our interrupt. 462 */ 463 if (pci_intr_map(pa, &ih)) { 464 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 465 return; 466 } 467 intrstr = pci_intr_string(pc, ih); 468 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc); 469 if (sc->sc_ih == NULL) { 470 printf("%s: unable to establish interrupt", 471 sc->sc_dev.dv_xname); 472 if (intrstr != NULL) 473 printf(" at %s", intrstr); 474 printf("\n"); 475 return; 476 } 477 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 478 479 /* 480 * Allocate the control data structures, and create and load the 481 * DMA map for it. 482 */ 483 if ((error = bus_dmamem_alloc(sc->sc_dmat, 484 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 485 0)) != 0) { 486 printf("%s: unable to allocate control data, error = %d\n", 487 sc->sc_dev.dv_xname, error); 488 goto fail_0; 489 } 490 491 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 492 sizeof(struct stge_control_data), (caddr_t *)&sc->sc_control_data, 493 BUS_DMA_COHERENT)) != 0) { 494 printf("%s: unable to map control data, error = %d\n", 495 sc->sc_dev.dv_xname, error); 496 goto fail_1; 497 } 498 499 if ((error = bus_dmamap_create(sc->sc_dmat, 500 sizeof(struct stge_control_data), 1, 501 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 502 printf("%s: unable to create control data DMA map, " 503 "error = %d\n", sc->sc_dev.dv_xname, error); 504 goto fail_2; 505 } 506 507 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 508 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 509 0)) != 0) { 510 printf("%s: unable to load control data DMA map, error = %d\n", 511 sc->sc_dev.dv_xname, error); 512 goto fail_3; 513 } 514 515 /* 516 * Create the transmit buffer DMA maps. Note that rev B.3 517 * and earlier seem to have a bug regarding multi-fragment 518 * packets. We need to limit the number of Tx segments on 519 * such chips to 1. 520 */ 521 for (i = 0; i < STGE_NTXDESC; i++) { 522 if ((error = bus_dmamap_create(sc->sc_dmat, 523 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 524 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 525 printf("%s: unable to create tx DMA map %d, " 526 "error = %d\n", sc->sc_dev.dv_xname, i, error); 527 goto fail_4; 528 } 529 } 530 531 /* 532 * Create the receive buffer DMA maps. 533 */ 534 for (i = 0; i < STGE_NRXDESC; i++) { 535 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 536 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 537 printf("%s: unable to create rx DMA map %d, " 538 "error = %d\n", sc->sc_dev.dv_xname, i, error); 539 goto fail_5; 540 } 541 sc->sc_rxsoft[i].ds_mbuf = NULL; 542 } 543 544 /* 545 * Determine if we're copper or fiber. It affects how we 546 * reset the card. 547 */ 548 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 549 AC_PhyMedia) 550 sc->sc_usefiber = 1; 551 else 552 sc->sc_usefiber = 0; 553 554 /* 555 * Reset the chip to a known state. 556 */ 557 stge_reset(sc); 558 559 /* 560 * Reading the station address from the EEPROM doesn't seem 561 * to work, at least on my sample boards. Instread, since 562 * the reset sequence does AutoInit, read it from the station 563 * address registers. 564 */ 565 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh, 566 STGE_StationAddress0) & 0xff; 567 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh, 568 STGE_StationAddress0) >> 8; 569 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh, 570 STGE_StationAddress1) & 0xff; 571 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh, 572 STGE_StationAddress1) >> 8; 573 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh, 574 STGE_StationAddress2) & 0xff; 575 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh, 576 STGE_StationAddress2) >> 8; 577 578 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 579 ether_sprintf(enaddr)); 580 581 /* 582 * Read some important bits from the PhyCtrl register. 583 */ 584 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh, 585 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 586 587 /* 588 * Initialize our media structures and probe the MII. 589 */ 590 sc->sc_mii.mii_ifp = ifp; 591 sc->sc_mii.mii_readreg = stge_mii_readreg; 592 sc->sc_mii.mii_writereg = stge_mii_writereg; 593 sc->sc_mii.mii_statchg = stge_mii_statchg; 594 ifmedia_init(&sc->sc_mii.mii_media, 0, stge_mediachange, 595 stge_mediastatus); 596 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 597 MII_OFFSET_ANY, MIIF_DOPAUSE); 598 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 599 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 600 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 601 } else 602 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 603 604 ifp = &sc->sc_ethercom.ec_if; 605 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 606 ifp->if_softc = sc; 607 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 608 ifp->if_ioctl = stge_ioctl; 609 ifp->if_start = stge_start; 610 ifp->if_watchdog = stge_watchdog; 611 ifp->if_init = stge_init; 612 ifp->if_stop = stge_stop; 613 IFQ_SET_READY(&ifp->if_snd); 614 615 /* 616 * The manual recommends disabling early transmit, so we 617 * do. It's disabled anyway, if using IP checksumming, 618 * since the entire packet must be in the FIFO in order 619 * for the chip to perform the checksum. 620 */ 621 sc->sc_txthresh = 0x0fff; 622 623 /* 624 * Disable MWI if the PCI layer tells us to. 625 */ 626 sc->sc_DMACtrl = 0; 627 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 628 sc->sc_DMACtrl |= DMAC_MWIDisable; 629 630 /* 631 * We can support 802.1Q VLAN-sized frames and jumbo 632 * Ethernet frames. 633 * 634 * XXX Figure out how to do hw-assisted VLAN tagging in 635 * XXX a reasonable way on this chip. 636 */ 637 sc->sc_ethercom.ec_capabilities |= 638 ETHERCAP_VLAN_MTU /* XXX | ETHERCAP_JUMBO_MTU */; 639 640 /* 641 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 642 */ 643 sc->sc_ethercom.ec_if.if_capabilities |= IFCAP_CSUM_IPv4 | 644 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 645 646 /* 647 * Attach the interface. 648 */ 649 if_attach(ifp); 650 ether_ifattach(ifp, enaddr); 651 652 #ifdef STGE_EVENT_COUNTERS 653 /* 654 * Attach event counters. 655 */ 656 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 657 NULL, sc->sc_dev.dv_xname, "txstall"); 658 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 659 NULL, sc->sc_dev.dv_xname, "txdmaintr"); 660 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 661 NULL, sc->sc_dev.dv_xname, "txindintr"); 662 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 663 NULL, sc->sc_dev.dv_xname, "rxintr"); 664 665 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 666 NULL, sc->sc_dev.dv_xname, "txseg1"); 667 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 668 NULL, sc->sc_dev.dv_xname, "txseg2"); 669 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 670 NULL, sc->sc_dev.dv_xname, "txseg3"); 671 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 672 NULL, sc->sc_dev.dv_xname, "txseg4"); 673 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 674 NULL, sc->sc_dev.dv_xname, "txseg5"); 675 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 676 NULL, sc->sc_dev.dv_xname, "txsegmore"); 677 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 678 NULL, sc->sc_dev.dv_xname, "txcopy"); 679 680 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 681 NULL, sc->sc_dev.dv_xname, "rxipsum"); 682 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 683 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 684 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 685 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 686 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 687 NULL, sc->sc_dev.dv_xname, "txipsum"); 688 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 689 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 690 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 691 NULL, sc->sc_dev.dv_xname, "txudpsum"); 692 #endif /* STGE_EVENT_COUNTERS */ 693 694 /* 695 * Make sure the interface is shutdown during reboot. 696 */ 697 sc->sc_sdhook = shutdownhook_establish(stge_shutdown, sc); 698 if (sc->sc_sdhook == NULL) 699 printf("%s: WARNING: unable to establish shutdown hook\n", 700 sc->sc_dev.dv_xname); 701 return; 702 703 /* 704 * Free any resources we've allocated during the failed attach 705 * attempt. Do this in reverse order and fall through. 706 */ 707 fail_5: 708 for (i = 0; i < STGE_NRXDESC; i++) { 709 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 710 bus_dmamap_destroy(sc->sc_dmat, 711 sc->sc_rxsoft[i].ds_dmamap); 712 } 713 fail_4: 714 for (i = 0; i < STGE_NTXDESC; i++) { 715 if (sc->sc_txsoft[i].ds_dmamap != NULL) 716 bus_dmamap_destroy(sc->sc_dmat, 717 sc->sc_txsoft[i].ds_dmamap); 718 } 719 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 720 fail_3: 721 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 722 fail_2: 723 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 724 sizeof(struct stge_control_data)); 725 fail_1: 726 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 727 fail_0: 728 return; 729 } 730 731 /* 732 * stge_shutdown: 733 * 734 * Make sure the interface is stopped at reboot time. 735 */ 736 void 737 stge_shutdown(void *arg) 738 { 739 struct stge_softc *sc = arg; 740 741 stge_stop(&sc->sc_ethercom.ec_if, 1); 742 } 743 744 static void 745 stge_dma_wait(struct stge_softc *sc) 746 { 747 int i; 748 749 for (i = 0; i < STGE_TIMEOUT; i++) { 750 delay(2); 751 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) & 752 DMAC_TxDMAInProg) == 0) 753 break; 754 } 755 756 if (i == STGE_TIMEOUT) 757 printf("%s: DMA wait timed out\n", sc->sc_dev.dv_xname); 758 } 759 760 /* 761 * stge_start: [ifnet interface function] 762 * 763 * Start packet transmission on the interface. 764 */ 765 void 766 stge_start(struct ifnet *ifp) 767 { 768 struct stge_softc *sc = ifp->if_softc; 769 struct mbuf *m0; 770 struct stge_descsoft *ds; 771 struct stge_tfd *tfd; 772 bus_dmamap_t dmamap; 773 int error, firsttx, nexttx, opending, seg, totlen; 774 uint64_t csum_flags; 775 776 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 777 return; 778 779 /* 780 * Remember the previous number of pending transmissions 781 * and the first descriptor we will use. 782 */ 783 opending = sc->sc_txpending; 784 firsttx = STGE_NEXTTX(sc->sc_txlast); 785 786 /* 787 * Loop through the send queue, setting up transmit descriptors 788 * until we drain the queue, or use up all available transmit 789 * descriptors. 790 */ 791 for (;;) { 792 /* 793 * Grab a packet off the queue. 794 */ 795 IFQ_POLL(&ifp->if_snd, m0); 796 if (m0 == NULL) 797 break; 798 799 /* 800 * Leave one unused descriptor at the end of the 801 * list to prevent wrapping completely around. 802 */ 803 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 804 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 805 break; 806 } 807 808 /* 809 * Get the last and next available transmit descriptor. 810 */ 811 nexttx = STGE_NEXTTX(sc->sc_txlast); 812 tfd = &sc->sc_txdescs[nexttx]; 813 ds = &sc->sc_txsoft[nexttx]; 814 815 dmamap = ds->ds_dmamap; 816 817 /* 818 * Load the DMA map. If this fails, the packet either 819 * didn't fit in the alloted number of segments, or we 820 * were short on resources. For the too-may-segments 821 * case, we simply report an error and drop the packet, 822 * since we can't sanely copy a jumbo packet to a single 823 * buffer. 824 */ 825 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 826 BUS_DMA_NOWAIT); 827 if (error) { 828 if (error == EFBIG) { 829 printf("%s: Tx packet consumes too many " 830 "DMA segments, dropping...\n", 831 sc->sc_dev.dv_xname); 832 IFQ_DEQUEUE(&ifp->if_snd, m0); 833 m_freem(m0); 834 continue; 835 } 836 /* 837 * Short on resources, just stop for now. 838 */ 839 break; 840 } 841 842 IFQ_DEQUEUE(&ifp->if_snd, m0); 843 844 /* 845 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 846 */ 847 848 /* Sync the DMA map. */ 849 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 850 BUS_DMASYNC_PREWRITE); 851 852 /* Initialize the fragment list. */ 853 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 854 tfd->tfd_frags[seg].frag_word0 = 855 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 856 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 857 totlen += dmamap->dm_segs[seg].ds_len; 858 } 859 860 #ifdef STGE_EVENT_COUNTERS 861 switch (dmamap->dm_nsegs) { 862 case 1: 863 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 864 break; 865 case 2: 866 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 867 break; 868 case 3: 869 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 870 break; 871 case 4: 872 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 873 break; 874 case 5: 875 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 876 break; 877 default: 878 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 879 break; 880 } 881 #endif /* STGE_EVENT_COUNTERS */ 882 883 /* 884 * Initialize checksumming flags in the descriptor. 885 * Byte-swap constants so the compiler can optimize. 886 */ 887 csum_flags = 0; 888 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 889 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 890 csum_flags |= htole64(TFD_IPChecksumEnable); 891 } 892 893 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 894 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 895 csum_flags |= htole64(TFD_TCPChecksumEnable); 896 } 897 else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 898 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 899 csum_flags |= htole64(TFD_UDPChecksumEnable); 900 } 901 902 /* 903 * Initialize the descriptor and give it to the chip. 904 */ 905 tfd->tfd_control = htole64(TFD_FrameId(nexttx) | 906 TFD_WordAlign(/*totlen & */3) | 907 TFD_FragCount(seg) | csum_flags | 908 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 909 TFD_TxDMAIndicate : 0)); 910 911 /* Sync the descriptor. */ 912 STGE_CDTXSYNC(sc, nexttx, 913 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 914 915 /* 916 * Kick the transmit DMA logic. 917 */ 918 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl, 919 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 920 921 /* 922 * Store a pointer to the packet so we can free it later. 923 */ 924 ds->ds_mbuf = m0; 925 926 /* Advance the tx pointer. */ 927 sc->sc_txpending++; 928 sc->sc_txlast = nexttx; 929 930 #if NBPFILTER > 0 931 /* 932 * Pass the packet to any BPF listeners. 933 */ 934 if (ifp->if_bpf) 935 bpf_mtap(ifp->if_bpf, m0); 936 #endif /* NBPFILTER > 0 */ 937 } 938 939 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 940 /* No more slots left; notify upper layer. */ 941 ifp->if_flags |= IFF_OACTIVE; 942 } 943 944 if (sc->sc_txpending != opending) { 945 /* 946 * We enqueued packets. If the transmitter was idle, 947 * reset the txdirty pointer. 948 */ 949 if (opending == 0) 950 sc->sc_txdirty = firsttx; 951 952 /* Set a watchdog timer in case the chip flakes out. */ 953 ifp->if_timer = 5; 954 } 955 } 956 957 /* 958 * stge_watchdog: [ifnet interface function] 959 * 960 * Watchdog timer handler. 961 */ 962 void 963 stge_watchdog(struct ifnet *ifp) 964 { 965 struct stge_softc *sc = ifp->if_softc; 966 967 /* 968 * Sweep up first, since we don't interrupt every frame. 969 */ 970 stge_txintr(sc); 971 if (sc->sc_txpending != 0) { 972 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 973 ifp->if_oerrors++; 974 975 (void) stge_init(ifp); 976 977 /* Try to get more packets going. */ 978 stge_start(ifp); 979 } 980 } 981 982 /* 983 * stge_ioctl: [ifnet interface function] 984 * 985 * Handle control requests from the operator. 986 */ 987 int 988 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 989 { 990 struct stge_softc *sc = ifp->if_softc; 991 struct ifreq *ifr = (struct ifreq *)data; 992 int s, error; 993 994 s = splnet(); 995 996 switch (cmd) { 997 case SIOCSIFMEDIA: 998 case SIOCGIFMEDIA: 999 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1000 break; 1001 1002 default: 1003 error = ether_ioctl(ifp, cmd, data); 1004 if (error == ENETRESET) { 1005 /* 1006 * Multicast list has changed; set the hardware filter 1007 * accordingly. 1008 */ 1009 stge_set_filter(sc); 1010 error = 0; 1011 } 1012 break; 1013 } 1014 1015 /* Try to get more packets going. */ 1016 stge_start(ifp); 1017 1018 splx(s); 1019 return (error); 1020 } 1021 1022 /* 1023 * stge_intr: 1024 * 1025 * Interrupt service routine. 1026 */ 1027 int 1028 stge_intr(void *arg) 1029 { 1030 struct stge_softc *sc = arg; 1031 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1032 uint32_t txstat; 1033 int wantinit; 1034 uint16_t isr; 1035 1036 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) & 1037 IS_InterruptStatus) == 0) 1038 return (0); 1039 1040 for (wantinit = 0; wantinit == 0;) { 1041 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck); 1042 if ((isr & sc->sc_IntEnable) == 0) 1043 break; 1044 1045 /* Receive interrupts. */ 1046 if (isr & (IE_RxDMAComplete|IE_RFDListEnd)) { 1047 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1048 stge_rxintr(sc); 1049 if (isr & IE_RFDListEnd) { 1050 printf("%s: receive ring overflow\n", 1051 sc->sc_dev.dv_xname); 1052 /* 1053 * XXX Should try to recover from this 1054 * XXX more gracefully. 1055 */ 1056 wantinit = 1; 1057 } 1058 } 1059 1060 /* Transmit interrupts. */ 1061 if (isr & (IE_TxDMAComplete|IE_TxComplete)) { 1062 #ifdef STGE_EVENT_COUNTERS 1063 if (isr & IE_TxDMAComplete) 1064 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1065 #endif 1066 stge_txintr(sc); 1067 } 1068 1069 /* Statistics overflow. */ 1070 if (isr & IE_UpdateStats) 1071 stge_stats_update(sc); 1072 1073 /* Transmission errors. */ 1074 if (isr & IE_TxComplete) { 1075 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1076 for (;;) { 1077 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh, 1078 STGE_TxStatus); 1079 if ((txstat & TS_TxComplete) == 0) 1080 break; 1081 if (txstat & TS_TxUnderrun) { 1082 sc->sc_txthresh++; 1083 if (sc->sc_txthresh > 0x0fff) 1084 sc->sc_txthresh = 0x0fff; 1085 printf("%s: transmit underrun, new " 1086 "threshold: %d bytes\n", 1087 sc->sc_dev.dv_xname, 1088 sc->sc_txthresh << 5); 1089 } 1090 if (txstat & TS_MaxCollisions) 1091 printf("%s: excessive collisions\n", 1092 sc->sc_dev.dv_xname); 1093 } 1094 wantinit = 1; 1095 } 1096 1097 /* Host interface errors. */ 1098 if (isr & IE_HostError) { 1099 printf("%s: Host interface error\n", 1100 sc->sc_dev.dv_xname); 1101 wantinit = 1; 1102 } 1103 } 1104 1105 if (wantinit) 1106 stge_init(ifp); 1107 1108 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 1109 sc->sc_IntEnable); 1110 1111 /* Try to get more packets going. */ 1112 stge_start(ifp); 1113 1114 return (1); 1115 } 1116 1117 /* 1118 * stge_txintr: 1119 * 1120 * Helper; handle transmit interrupts. 1121 */ 1122 void 1123 stge_txintr(struct stge_softc *sc) 1124 { 1125 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1126 struct stge_descsoft *ds; 1127 uint64_t control; 1128 int i; 1129 1130 ifp->if_flags &= ~IFF_OACTIVE; 1131 1132 /* 1133 * Go through our Tx list and free mbufs for those 1134 * frames which have been transmitted. 1135 */ 1136 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1137 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1138 ds = &sc->sc_txsoft[i]; 1139 1140 STGE_CDTXSYNC(sc, i, 1141 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1142 1143 control = le64toh(sc->sc_txdescs[i].tfd_control); 1144 if ((control & TFD_TFDDone) == 0) 1145 break; 1146 1147 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1148 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1149 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1150 m_freem(ds->ds_mbuf); 1151 ds->ds_mbuf = NULL; 1152 } 1153 1154 /* Update the dirty transmit buffer pointer. */ 1155 sc->sc_txdirty = i; 1156 1157 /* 1158 * If there are no more pending transmissions, cancel the watchdog 1159 * timer. 1160 */ 1161 if (sc->sc_txpending == 0) 1162 ifp->if_timer = 0; 1163 } 1164 1165 /* 1166 * stge_rxintr: 1167 * 1168 * Helper; handle receive interrupts. 1169 */ 1170 void 1171 stge_rxintr(struct stge_softc *sc) 1172 { 1173 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1174 struct stge_descsoft *ds; 1175 struct mbuf *m, *tailm; 1176 uint64_t status; 1177 int i, len; 1178 1179 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1180 ds = &sc->sc_rxsoft[i]; 1181 1182 STGE_CDRXSYNC(sc, i, 1183 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1184 1185 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1186 1187 if ((status & RFD_RFDDone) == 0) 1188 break; 1189 1190 if (__predict_false(sc->sc_rxdiscard)) { 1191 STGE_INIT_RXDESC(sc, i); 1192 if (status & RFD_FrameEnd) { 1193 /* Reset our state. */ 1194 sc->sc_rxdiscard = 0; 1195 } 1196 continue; 1197 } 1198 1199 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1200 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1201 1202 m = ds->ds_mbuf; 1203 1204 /* 1205 * Add a new receive buffer to the ring. 1206 */ 1207 if (stge_add_rxbuf(sc, i) != 0) { 1208 /* 1209 * Failed, throw away what we've done so 1210 * far, and discard the rest of the packet. 1211 */ 1212 ifp->if_ierrors++; 1213 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1214 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1215 STGE_INIT_RXDESC(sc, i); 1216 if ((status & RFD_FrameEnd) == 0) 1217 sc->sc_rxdiscard = 1; 1218 if (sc->sc_rxhead != NULL) 1219 m_freem(sc->sc_rxhead); 1220 STGE_RXCHAIN_RESET(sc); 1221 continue; 1222 } 1223 1224 #ifdef DIAGNOSTIC 1225 if (status & RFD_FrameStart) { 1226 KASSERT(sc->sc_rxhead == NULL); 1227 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1228 } 1229 #endif 1230 1231 STGE_RXCHAIN_LINK(sc, m); 1232 1233 /* 1234 * If this is not the end of the packet, keep 1235 * looking. 1236 */ 1237 if ((status & RFD_FrameEnd) == 0) { 1238 sc->sc_rxlen += m->m_len; 1239 continue; 1240 } 1241 1242 /* 1243 * Okay, we have the entire packet now... 1244 */ 1245 *sc->sc_rxtailp = NULL; 1246 m = sc->sc_rxhead; 1247 tailm = sc->sc_rxtail; 1248 1249 STGE_RXCHAIN_RESET(sc); 1250 1251 /* 1252 * If the packet had an error, drop it. Note we 1253 * count the error later in the periodic stats update. 1254 */ 1255 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1256 RFD_RxAlignmentError | RFD_RxFCSError | 1257 RFD_RxLengthError)) { 1258 m_freem(m); 1259 continue; 1260 } 1261 1262 /* 1263 * No errors. 1264 * 1265 * Note we have configured the chip to not include 1266 * the CRC at the end of the packet. 1267 */ 1268 len = RFD_RxDMAFrameLen(status); 1269 tailm->m_len = len - sc->sc_rxlen; 1270 1271 /* 1272 * If the packet is small enough to fit in a 1273 * single header mbuf, allocate one and copy 1274 * the data into it. This greatly reduces 1275 * memory consumption when we receive lots 1276 * of small packets. 1277 */ 1278 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1279 struct mbuf *nm; 1280 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1281 if (nm == NULL) { 1282 ifp->if_ierrors++; 1283 m_freem(m); 1284 continue; 1285 } 1286 nm->m_data += 2; 1287 nm->m_pkthdr.len = nm->m_len = len; 1288 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1289 m_freem(m); 1290 m = nm; 1291 } 1292 1293 /* 1294 * Set the incoming checksum information for the packet. 1295 */ 1296 if (status & RFD_IPDetected) { 1297 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1298 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1299 if (status & RFD_IPError) 1300 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1301 if (status & RFD_TCPDetected) { 1302 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1303 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1304 if (status & RFD_TCPError) 1305 m->m_pkthdr.csum_flags |= 1306 M_CSUM_TCP_UDP_BAD; 1307 } else if (status & RFD_UDPDetected) { 1308 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1309 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1310 if (status & RFD_UDPError) 1311 m->m_pkthdr.csum_flags |= 1312 M_CSUM_TCP_UDP_BAD; 1313 } 1314 } 1315 1316 m->m_pkthdr.rcvif = ifp; 1317 m->m_pkthdr.len = len; 1318 1319 #if NBPFILTER > 0 1320 /* 1321 * Pass this up to any BPF listeners, but only 1322 * pass if up the stack if it's for us. 1323 */ 1324 if (ifp->if_bpf) 1325 bpf_mtap(ifp->if_bpf, m); 1326 #endif /* NBPFILTER > 0 */ 1327 1328 /* Pass it on. */ 1329 (*ifp->if_input)(ifp, m); 1330 } 1331 1332 /* Update the receive pointer. */ 1333 sc->sc_rxptr = i; 1334 } 1335 1336 /* 1337 * stge_tick: 1338 * 1339 * One second timer, used to tick the MII. 1340 */ 1341 void 1342 stge_tick(void *arg) 1343 { 1344 struct stge_softc *sc = arg; 1345 int s; 1346 1347 s = splnet(); 1348 mii_tick(&sc->sc_mii); 1349 stge_stats_update(sc); 1350 splx(s); 1351 1352 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1353 } 1354 1355 /* 1356 * stge_stats_update: 1357 * 1358 * Read the TC9021 statistics counters. 1359 */ 1360 void 1361 stge_stats_update(struct stge_softc *sc) 1362 { 1363 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1364 bus_space_tag_t st = sc->sc_st; 1365 bus_space_handle_t sh = sc->sc_sh; 1366 1367 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk); 1368 1369 ifp->if_ipackets += 1370 bus_space_read_4(st, sh, STGE_FramesRcvdOk); 1371 1372 ifp->if_ierrors += 1373 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors); 1374 1375 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk); 1376 1377 ifp->if_opackets += 1378 bus_space_read_4(st, sh, STGE_FramesXmtdOk); 1379 1380 ifp->if_collisions += 1381 bus_space_read_4(st, sh, STGE_LateCollisions) + 1382 bus_space_read_4(st, sh, STGE_MultiColFrames) + 1383 bus_space_read_4(st, sh, STGE_SingleColFrames); 1384 1385 ifp->if_oerrors += 1386 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) + 1387 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal); 1388 } 1389 1390 /* 1391 * stge_reset: 1392 * 1393 * Perform a soft reset on the TC9021. 1394 */ 1395 void 1396 stge_reset(struct stge_softc *sc) 1397 { 1398 uint32_t ac; 1399 int i; 1400 1401 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl); 1402 1403 /* 1404 * Only assert RstOut if we're fiber. We need GMII clocks 1405 * to be present in order for the reset to complete on fiber 1406 * cards. 1407 */ 1408 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl, 1409 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1410 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1411 (sc->sc_usefiber ? AC_RstOut : 0)); 1412 1413 delay(50000); 1414 1415 for (i = 0; i < STGE_TIMEOUT; i++) { 1416 delay(5000); 1417 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 1418 AC_ResetBusy) == 0) 1419 break; 1420 } 1421 1422 if (i == STGE_TIMEOUT) 1423 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1424 1425 delay(1000); 1426 } 1427 1428 /* 1429 * stge_init: [ ifnet interface function ] 1430 * 1431 * Initialize the interface. Must be called at splnet(). 1432 */ 1433 int 1434 stge_init(struct ifnet *ifp) 1435 { 1436 struct stge_softc *sc = ifp->if_softc; 1437 bus_space_tag_t st = sc->sc_st; 1438 bus_space_handle_t sh = sc->sc_sh; 1439 struct stge_descsoft *ds; 1440 int i, error = 0; 1441 1442 /* 1443 * Cancel any pending I/O. 1444 */ 1445 stge_stop(ifp, 0); 1446 1447 /* 1448 * Reset the chip to a known state. 1449 */ 1450 stge_reset(sc); 1451 1452 /* 1453 * Initialize the transmit descriptor ring. 1454 */ 1455 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1456 for (i = 0; i < STGE_NTXDESC; i++) { 1457 sc->sc_txdescs[i].tfd_next = 1458 (uint64_t) STGE_CDTXADDR(sc, STGE_NEXTTX(i)); 1459 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1460 } 1461 sc->sc_txpending = 0; 1462 sc->sc_txdirty = 0; 1463 sc->sc_txlast = STGE_NTXDESC - 1; 1464 1465 /* 1466 * Initialize the receive descriptor and receive job 1467 * descriptor rings. 1468 */ 1469 for (i = 0; i < STGE_NRXDESC; i++) { 1470 ds = &sc->sc_rxsoft[i]; 1471 if (ds->ds_mbuf == NULL) { 1472 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1473 printf("%s: unable to allocate or map rx " 1474 "buffer %d, error = %d\n", 1475 sc->sc_dev.dv_xname, i, error); 1476 /* 1477 * XXX Should attempt to run with fewer receive 1478 * XXX buffers instead of just failing. 1479 */ 1480 stge_rxdrain(sc); 1481 goto out; 1482 } 1483 } else 1484 STGE_INIT_RXDESC(sc, i); 1485 } 1486 sc->sc_rxptr = 0; 1487 sc->sc_rxdiscard = 0; 1488 STGE_RXCHAIN_RESET(sc); 1489 1490 /* Set the station address. */ 1491 bus_space_write_2(st, sh, STGE_StationAddress0, 1492 LLADDR(ifp->if_sadl)[0] | (LLADDR(ifp->if_sadl)[1] << 8)); 1493 bus_space_write_2(st, sh, STGE_StationAddress1, 1494 LLADDR(ifp->if_sadl)[2] | (LLADDR(ifp->if_sadl)[3] << 8)); 1495 bus_space_write_2(st, sh, STGE_StationAddress2, 1496 LLADDR(ifp->if_sadl)[4] | (LLADDR(ifp->if_sadl)[5] << 8)); 1497 1498 /* 1499 * Set the statistics masks. Disable all the RMON stats, 1500 * and disable selected stats in the non-RMON stats registers. 1501 */ 1502 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff); 1503 bus_space_write_4(st, sh, STGE_StatisticsMask, 1504 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1505 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1506 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1507 (1U << 21)); 1508 1509 /* Set up the receive filter. */ 1510 stge_set_filter(sc); 1511 1512 /* 1513 * Give the transmit and receive ring to the chip. 1514 */ 1515 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1516 bus_space_write_4(st, sh, STGE_TFDListPtrLo, 1517 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1518 1519 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1520 bus_space_write_4(st, sh, STGE_RFDListPtrLo, 1521 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1522 1523 /* 1524 * Initialize the Tx auto-poll period. It's OK to make this number 1525 * large (255 is the max, but we use 127) -- we explicitly kick the 1526 * transmit engine when there's actually a packet. 1527 */ 1528 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127); 1529 1530 /* ..and the Rx auto-poll period. */ 1531 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64); 1532 1533 /* Initialize the Tx start threshold. */ 1534 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh); 1535 1536 /* 1537 * Initialize the Rx DMA interrupt control register. We 1538 * request an interrupt after every incoming packet, but 1539 * defer it for 32us (64 * 512 ns). When the number of 1540 * interrupts pending reaches 8, we stop deferring the 1541 * interrupt, and signal it immediately. 1542 */ 1543 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl, 1544 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1545 1546 /* 1547 * Initialize the interrupt mask. 1548 */ 1549 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1550 IE_TxDMAComplete | IE_RxDMAComplete | IE_RFDListEnd; 1551 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff); 1552 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable); 1553 1554 /* 1555 * Configure the DMA engine. 1556 * XXX Should auto-tune TxBurstLimit. 1557 */ 1558 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl | 1559 DMAC_TxBurstLimit(3)); 1560 1561 /* 1562 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1563 * FIFO, and send an un-PAUSE frame when the FIFO is totally 1564 * empty again. 1565 */ 1566 bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16); 1567 bus_space_write_2(st, sh, STGE_FlowOffThresh, 0); 1568 1569 /* 1570 * Set the maximum frame size. 1571 */ 1572 bus_space_write_2(st, sh, STGE_MaxFrameSize, 1573 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1574 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1575 ETHER_VLAN_ENCAP_LEN : 0)); 1576 1577 /* 1578 * Initialize MacCtrl -- do it before setting the media, 1579 * as setting the media will actually program the register. 1580 * 1581 * Note: We have to poke the IFS value before poking 1582 * anything else. 1583 */ 1584 sc->sc_MACCtrl = MC_IFSSelect(0); 1585 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl); 1586 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1587 1588 if (sc->sc_rev >= 6) { /* >= B.2 */ 1589 /* Multi-frag frame bug work-around. */ 1590 bus_space_write_2(st, sh, STGE_DebugCtrl, 1591 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200); 1592 1593 /* Tx Poll Now bug work-around. */ 1594 bus_space_write_2(st, sh, STGE_DebugCtrl, 1595 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010); 1596 } 1597 1598 /* 1599 * Set the current media. 1600 */ 1601 mii_mediachg(&sc->sc_mii); 1602 1603 /* 1604 * Start the one second MII clock. 1605 */ 1606 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1607 1608 /* 1609 * ...all done! 1610 */ 1611 ifp->if_flags |= IFF_RUNNING; 1612 ifp->if_flags &= ~IFF_OACTIVE; 1613 1614 out: 1615 if (error) 1616 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1617 return (error); 1618 } 1619 1620 /* 1621 * stge_drain: 1622 * 1623 * Drain the receive queue. 1624 */ 1625 void 1626 stge_rxdrain(struct stge_softc *sc) 1627 { 1628 struct stge_descsoft *ds; 1629 int i; 1630 1631 for (i = 0; i < STGE_NRXDESC; i++) { 1632 ds = &sc->sc_rxsoft[i]; 1633 if (ds->ds_mbuf != NULL) { 1634 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1635 ds->ds_mbuf->m_next = NULL; 1636 m_freem(ds->ds_mbuf); 1637 ds->ds_mbuf = NULL; 1638 } 1639 } 1640 } 1641 1642 /* 1643 * stge_stop: [ ifnet interface function ] 1644 * 1645 * Stop transmission on the interface. 1646 */ 1647 void 1648 stge_stop(struct ifnet *ifp, int disable) 1649 { 1650 struct stge_softc *sc = ifp->if_softc; 1651 struct stge_descsoft *ds; 1652 int i; 1653 1654 /* 1655 * Stop the one second clock. 1656 */ 1657 callout_stop(&sc->sc_tick_ch); 1658 1659 /* Down the MII. */ 1660 mii_down(&sc->sc_mii); 1661 1662 /* 1663 * Disable interrupts. 1664 */ 1665 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0); 1666 1667 /* 1668 * Stop receiver, transmitter, and stats update. 1669 */ 1670 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, 1671 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1672 1673 /* 1674 * Stop the transmit and receive DMA. 1675 */ 1676 stge_dma_wait(sc); 1677 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0); 1678 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0); 1679 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0); 1680 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0); 1681 1682 /* 1683 * Release any queued transmit buffers. 1684 */ 1685 for (i = 0; i < STGE_NTXDESC; i++) { 1686 ds = &sc->sc_txsoft[i]; 1687 if (ds->ds_mbuf != NULL) { 1688 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1689 m_freem(ds->ds_mbuf); 1690 ds->ds_mbuf = NULL; 1691 } 1692 } 1693 1694 if (disable) 1695 stge_rxdrain(sc); 1696 1697 /* 1698 * Mark the interface down and cancel the watchdog timer. 1699 */ 1700 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1701 ifp->if_timer = 0; 1702 } 1703 1704 #if 0 1705 static int 1706 stge_eeprom_wait(struct stge_softc *sc) 1707 { 1708 int i; 1709 1710 for (i = 0; i < STGE_TIMEOUT; i++) { 1711 delay(1000); 1712 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) & 1713 EC_EepromBusy) == 0) 1714 return (0); 1715 } 1716 return (1); 1717 } 1718 1719 /* 1720 * stge_read_eeprom: 1721 * 1722 * Read data from the serial EEPROM. 1723 */ 1724 void 1725 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1726 { 1727 1728 if (stge_eeprom_wait(sc)) 1729 printf("%s: EEPROM failed to come ready\n", 1730 sc->sc_dev.dv_xname); 1731 1732 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl, 1733 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1734 if (stge_eeprom_wait(sc)) 1735 printf("%s: EEPROM read timed out\n", 1736 sc->sc_dev.dv_xname); 1737 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData); 1738 } 1739 #endif /* 0 */ 1740 1741 /* 1742 * stge_add_rxbuf: 1743 * 1744 * Add a receive buffer to the indicated descriptor. 1745 */ 1746 int 1747 stge_add_rxbuf(struct stge_softc *sc, int idx) 1748 { 1749 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1750 struct mbuf *m; 1751 int error; 1752 1753 MGETHDR(m, M_DONTWAIT, MT_DATA); 1754 if (m == NULL) 1755 return (ENOBUFS); 1756 1757 MCLGET(m, M_DONTWAIT); 1758 if ((m->m_flags & M_EXT) == 0) { 1759 m_freem(m); 1760 return (ENOBUFS); 1761 } 1762 1763 m->m_data = m->m_ext.ext_buf + 2; 1764 m->m_len = MCLBYTES - 2; 1765 1766 if (ds->ds_mbuf != NULL) 1767 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1768 1769 ds->ds_mbuf = m; 1770 1771 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1772 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1773 if (error) { 1774 printf("%s: can't load rx DMA map %d, error = %d\n", 1775 sc->sc_dev.dv_xname, idx, error); 1776 panic("stge_add_rxbuf"); /* XXX */ 1777 } 1778 1779 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1780 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1781 1782 STGE_INIT_RXDESC(sc, idx); 1783 1784 return (0); 1785 } 1786 1787 /* 1788 * stge_set_filter: 1789 * 1790 * Set up the receive filter. 1791 */ 1792 void 1793 stge_set_filter(struct stge_softc *sc) 1794 { 1795 struct ethercom *ec = &sc->sc_ethercom; 1796 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1797 struct ether_multi *enm; 1798 struct ether_multistep step; 1799 uint32_t crc; 1800 uint32_t mchash[2]; 1801 1802 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1803 if (ifp->if_flags & IFF_BROADCAST) 1804 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1805 1806 if (ifp->if_flags & IFF_PROMISC) { 1807 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1808 goto allmulti; 1809 } 1810 1811 /* 1812 * Set up the multicast address filter by passing all multicast 1813 * addresses through a CRC generator, and then using the low-order 1814 * 6 bits as an index into the 64 bit multicast hash table. The 1815 * high order bits select the register, while the rest of the bits 1816 * select the bit within the register. 1817 */ 1818 1819 memset(mchash, 0, sizeof(mchash)); 1820 1821 ETHER_FIRST_MULTI(step, ec, enm); 1822 if (enm == NULL) 1823 goto done; 1824 1825 while (enm != NULL) { 1826 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1827 /* 1828 * We must listen to a range of multicast addresses. 1829 * For now, just accept all multicasts, rather than 1830 * trying to set only those filter bits needed to match 1831 * the range. (At this time, the only use of address 1832 * ranges is for IP multicast routing, for which the 1833 * range is big enough to require all bits set.) 1834 */ 1835 goto allmulti; 1836 } 1837 1838 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1839 1840 /* Just want the 6 least significant bits. */ 1841 crc &= 0x3f; 1842 1843 /* Set the corresponding bit in the hash table. */ 1844 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1845 1846 ETHER_NEXT_MULTI(step, enm); 1847 } 1848 1849 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1850 1851 ifp->if_flags &= ~IFF_ALLMULTI; 1852 goto done; 1853 1854 allmulti: 1855 ifp->if_flags |= IFF_ALLMULTI; 1856 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1857 1858 done: 1859 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1860 /* 1861 * Program the multicast hash table. 1862 */ 1863 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0, 1864 mchash[0]); 1865 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1, 1866 mchash[1]); 1867 } 1868 1869 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_ReceiveMode, 1870 sc->sc_ReceiveMode); 1871 } 1872 1873 /* 1874 * stge_mii_readreg: [mii interface function] 1875 * 1876 * Read a PHY register on the MII of the TC9021. 1877 */ 1878 int 1879 stge_mii_readreg(struct device *self, int phy, int reg) 1880 { 1881 1882 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg)); 1883 } 1884 1885 /* 1886 * stge_mii_writereg: [mii interface function] 1887 * 1888 * Write a PHY register on the MII of the TC9021. 1889 */ 1890 void 1891 stge_mii_writereg(struct device *self, int phy, int reg, int val) 1892 { 1893 1894 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val); 1895 } 1896 1897 /* 1898 * stge_mii_statchg: [mii interface function] 1899 * 1900 * Callback from MII layer when media changes. 1901 */ 1902 void 1903 stge_mii_statchg(struct device *self) 1904 { 1905 struct stge_softc *sc = (struct stge_softc *) self; 1906 1907 if (sc->sc_mii.mii_media_active & IFM_FDX) 1908 sc->sc_MACCtrl |= MC_DuplexSelect; 1909 else 1910 sc->sc_MACCtrl &= ~MC_DuplexSelect; 1911 1912 /* XXX 802.1x flow-control? */ 1913 1914 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl); 1915 } 1916 1917 /* 1918 * sste_mii_bitbang_read: [mii bit-bang interface function] 1919 * 1920 * Read the MII serial port for the MII bit-bang module. 1921 */ 1922 uint32_t 1923 stge_mii_bitbang_read(struct device *self) 1924 { 1925 struct stge_softc *sc = (void *) self; 1926 1927 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl)); 1928 } 1929 1930 /* 1931 * stge_mii_bitbang_write: [mii big-bang interface function] 1932 * 1933 * Write the MII serial port for the MII bit-bang module. 1934 */ 1935 void 1936 stge_mii_bitbang_write(struct device *self, uint32_t val) 1937 { 1938 struct stge_softc *sc = (void *) self; 1939 1940 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl, 1941 val | sc->sc_PhyCtrl); 1942 } 1943 1944 /* 1945 * stge_mediastatus: [ifmedia interface function] 1946 * 1947 * Get the current interface media status. 1948 */ 1949 void 1950 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1951 { 1952 struct stge_softc *sc = ifp->if_softc; 1953 1954 mii_pollstat(&sc->sc_mii); 1955 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1956 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1957 } 1958 1959 /* 1960 * stge_mediachange: [ifmedia interface function] 1961 * 1962 * Set hardware to newly-selected media. 1963 */ 1964 int 1965 stge_mediachange(struct ifnet *ifp) 1966 { 1967 struct stge_softc *sc = ifp->if_softc; 1968 1969 if (ifp->if_flags & IFF_UP) 1970 mii_mediachg(&sc->sc_mii); 1971 return (0); 1972 } 1973