1 /* $NetBSD: if_stge.c,v 1.13 2002/10/21 23:38:11 fair Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the Sundance Tech. TC9021 10/100/1000 41 * Ethernet controller. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.13 2002/10/21 23:38:11 fair Exp $"); 46 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/callout.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 #include <sys/queue.h> 60 61 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/if_ether.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 72 #include <machine/bus.h> 73 #include <machine/intr.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 #include <dev/mii/mii_bitbang.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcidevs.h> 82 83 #include <dev/pci/if_stgereg.h> 84 85 /* 86 * Transmit descriptor list size. 87 */ 88 #define STGE_NTXDESC 256 89 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 90 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 91 92 /* 93 * Receive descriptor list size. 94 */ 95 #define STGE_NRXDESC 256 96 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 97 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 98 99 /* 100 * Only interrupt every N frames. Must be a power-of-two. 101 */ 102 #define STGE_TXINTR_SPACING 16 103 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 104 105 /* 106 * Control structures are DMA'd to the TC9021 chip. We allocate them in 107 * a single clump that maps to a single DMA segment to make several things 108 * easier. 109 */ 110 struct stge_control_data { 111 /* 112 * The transmit descriptors. 113 */ 114 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 115 116 /* 117 * The receive descriptors. 118 */ 119 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 120 }; 121 122 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 123 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 124 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 125 126 /* 127 * Software state for transmit and receive jobs. 128 */ 129 struct stge_descsoft { 130 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 131 bus_dmamap_t ds_dmamap; /* our DMA map */ 132 }; 133 134 /* 135 * Software state per device. 136 */ 137 struct stge_softc { 138 struct device sc_dev; /* generic device information */ 139 bus_space_tag_t sc_st; /* bus space tag */ 140 bus_space_handle_t sc_sh; /* bus space handle */ 141 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 142 struct ethercom sc_ethercom; /* ethernet common data */ 143 void *sc_sdhook; /* shutdown hook */ 144 int sc_rev; /* silicon revision */ 145 146 void *sc_ih; /* interrupt cookie */ 147 148 struct mii_data sc_mii; /* MII/media information */ 149 150 struct callout sc_tick_ch; /* tick callout */ 151 152 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 153 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 154 155 /* 156 * Software state for transmit and receive descriptors. 157 */ 158 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 159 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 160 161 /* 162 * Control data structures. 163 */ 164 struct stge_control_data *sc_control_data; 165 #define sc_txdescs sc_control_data->scd_txdescs 166 #define sc_rxdescs sc_control_data->scd_rxdescs 167 168 #ifdef STGE_EVENT_COUNTERS 169 /* 170 * Event counters. 171 */ 172 struct evcnt sc_ev_txstall; /* Tx stalled */ 173 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 174 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 175 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 176 177 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 178 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 179 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 180 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 181 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 182 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 183 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 184 185 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 186 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 187 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 188 189 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 190 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 191 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 192 #endif /* STGE_EVENT_COUNTERS */ 193 194 int sc_txpending; /* number of Tx requests pending */ 195 int sc_txdirty; /* first dirty Tx descriptor */ 196 int sc_txlast; /* last used Tx descriptor */ 197 198 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 199 int sc_rxdiscard; 200 int sc_rxlen; 201 struct mbuf *sc_rxhead; 202 struct mbuf *sc_rxtail; 203 struct mbuf **sc_rxtailp; 204 205 int sc_txthresh; /* Tx threshold */ 206 int sc_usefiber; /* if we're fiber */ 207 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 208 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 209 uint16_t sc_IntEnable; /* prototype IntEnable register */ 210 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 211 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 212 }; 213 214 #define STGE_RXCHAIN_RESET(sc) \ 215 do { \ 216 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 217 *(sc)->sc_rxtailp = NULL; \ 218 (sc)->sc_rxlen = 0; \ 219 } while (/*CONSTCOND*/0) 220 221 #define STGE_RXCHAIN_LINK(sc, m) \ 222 do { \ 223 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 224 (sc)->sc_rxtailp = &(m)->m_next; \ 225 } while (/*CONSTCOND*/0) 226 227 #ifdef STGE_EVENT_COUNTERS 228 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 229 #else 230 #define STGE_EVCNT_INCR(ev) /* nothing */ 231 #endif 232 233 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 234 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 235 236 #define STGE_CDTXSYNC(sc, x, ops) \ 237 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 238 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 239 240 #define STGE_CDRXSYNC(sc, x, ops) \ 241 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 242 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 243 244 #define STGE_INIT_RXDESC(sc, x) \ 245 do { \ 246 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 247 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 248 \ 249 /* \ 250 * Note: We scoot the packet forward 2 bytes in the buffer \ 251 * so that the payload after the Ethernet header is aligned \ 252 * to a 4-byte boundary. \ 253 */ \ 254 __rfd->rfd_frag.frag_word0 = \ 255 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 256 FRAG_LEN(MCLBYTES - 2)); \ 257 __rfd->rfd_next = \ 258 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 259 __rfd->rfd_status = 0; \ 260 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 261 } while (/*CONSTCOND*/0) 262 263 #define STGE_TIMEOUT 1000 264 265 void stge_start(struct ifnet *); 266 void stge_watchdog(struct ifnet *); 267 int stge_ioctl(struct ifnet *, u_long, caddr_t); 268 int stge_init(struct ifnet *); 269 void stge_stop(struct ifnet *, int); 270 271 void stge_shutdown(void *); 272 273 void stge_reset(struct stge_softc *); 274 void stge_rxdrain(struct stge_softc *); 275 int stge_add_rxbuf(struct stge_softc *, int); 276 #if 0 277 void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 278 #endif 279 void stge_tick(void *); 280 281 void stge_stats_update(struct stge_softc *); 282 283 void stge_set_filter(struct stge_softc *); 284 285 int stge_intr(void *); 286 void stge_txintr(struct stge_softc *); 287 void stge_rxintr(struct stge_softc *); 288 289 int stge_mii_readreg(struct device *, int, int); 290 void stge_mii_writereg(struct device *, int, int, int); 291 void stge_mii_statchg(struct device *); 292 293 int stge_mediachange(struct ifnet *); 294 void stge_mediastatus(struct ifnet *, struct ifmediareq *); 295 296 int stge_match(struct device *, struct cfdata *, void *); 297 void stge_attach(struct device *, struct device *, void *); 298 299 int stge_copy_small = 0; 300 301 CFATTACH_DECL(stge, sizeof(struct stge_softc), 302 stge_match, stge_attach, NULL, NULL); 303 304 uint32_t stge_mii_bitbang_read(struct device *); 305 void stge_mii_bitbang_write(struct device *, uint32_t); 306 307 const struct mii_bitbang_ops stge_mii_bitbang_ops = { 308 stge_mii_bitbang_read, 309 stge_mii_bitbang_write, 310 { 311 PC_MgmtData, /* MII_BIT_MDO */ 312 PC_MgmtData, /* MII_BIT_MDI */ 313 PC_MgmtClk, /* MII_BIT_MDC */ 314 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 315 0, /* MII_BIT_DIR_PHY_HOST */ 316 } 317 }; 318 319 /* 320 * Devices supported by this driver. 321 */ 322 const struct stge_product { 323 pci_vendor_id_t stge_vendor; 324 pci_product_id_t stge_product; 325 const char *stge_name; 326 } stge_products[] = { 327 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 328 "Sundance ST-2021 Gigabit Ethernet" }, 329 330 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 331 "Tamarack TC9021 Gigabit Ethernet" }, 332 333 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 334 "Tamarack TC9021 Gigabit Ethernet" }, 335 336 /* 337 * The Sundance sample boards use the Sundance vendor ID, 338 * but the Tamarack product ID. 339 */ 340 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 341 "Sundance TC9021 Gigabit Ethernet" }, 342 343 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 344 "Sundance TC9021 Gigabit Ethernet" }, 345 346 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 347 "D-Link DL-4000 Gigabit Ethernet" }, 348 349 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 350 "Antares Gigabit Ethernet" }, 351 352 { 0, 0, 353 NULL }, 354 }; 355 356 static const struct stge_product * 357 stge_lookup(const struct pci_attach_args *pa) 358 { 359 const struct stge_product *sp; 360 361 for (sp = stge_products; sp->stge_name != NULL; sp++) { 362 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 363 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 364 return (sp); 365 } 366 return (NULL); 367 } 368 369 int 370 stge_match(struct device *parent, struct cfdata *cf, void *aux) 371 { 372 struct pci_attach_args *pa = aux; 373 374 if (stge_lookup(pa) != NULL) 375 return (1); 376 377 return (0); 378 } 379 380 void 381 stge_attach(struct device *parent, struct device *self, void *aux) 382 { 383 struct stge_softc *sc = (struct stge_softc *) self; 384 struct pci_attach_args *pa = aux; 385 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 386 pci_chipset_tag_t pc = pa->pa_pc; 387 pci_intr_handle_t ih; 388 const char *intrstr = NULL; 389 bus_space_tag_t iot, memt; 390 bus_space_handle_t ioh, memh; 391 bus_dma_segment_t seg; 392 int ioh_valid, memh_valid; 393 int i, rseg, error; 394 const struct stge_product *sp; 395 pcireg_t pmode; 396 uint8_t enaddr[ETHER_ADDR_LEN]; 397 int pmreg; 398 399 callout_init(&sc->sc_tick_ch); 400 401 sp = stge_lookup(pa); 402 if (sp == NULL) { 403 printf("\n"); 404 panic("ste_attach: impossible"); 405 } 406 407 sc->sc_rev = PCI_REVISION(pa->pa_class); 408 409 printf(": %s, rev. %d\n", sp->stge_name, sc->sc_rev); 410 411 /* 412 * Map the device. 413 */ 414 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 415 PCI_MAPREG_TYPE_IO, 0, 416 &iot, &ioh, NULL, NULL) == 0); 417 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 418 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 419 &memt, &memh, NULL, NULL) == 0); 420 421 if (memh_valid) { 422 sc->sc_st = memt; 423 sc->sc_sh = memh; 424 } else if (ioh_valid) { 425 sc->sc_st = iot; 426 sc->sc_sh = ioh; 427 } else { 428 printf("%s: unable to map device registers\n", 429 sc->sc_dev.dv_xname); 430 return; 431 } 432 433 sc->sc_dmat = pa->pa_dmat; 434 435 /* Enable bus mastering. */ 436 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 437 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 438 PCI_COMMAND_MASTER_ENABLE); 439 440 /* Get it out of power save mode if needed. */ 441 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 442 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 443 if (pmode == 3) { 444 /* 445 * The card has lost all configuration data in 446 * this state, so punt. 447 */ 448 printf("%s: unable to wake up from power state D3\n", 449 sc->sc_dev.dv_xname); 450 return; 451 } 452 if (pmode != 0) { 453 printf("%s: waking up from power state D%d\n", 454 sc->sc_dev.dv_xname, pmode); 455 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 456 } 457 } 458 459 /* 460 * Map and establish our interrupt. 461 */ 462 if (pci_intr_map(pa, &ih)) { 463 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 464 return; 465 } 466 intrstr = pci_intr_string(pc, ih); 467 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc); 468 if (sc->sc_ih == NULL) { 469 printf("%s: unable to establish interrupt", 470 sc->sc_dev.dv_xname); 471 if (intrstr != NULL) 472 printf(" at %s", intrstr); 473 printf("\n"); 474 return; 475 } 476 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 477 478 /* 479 * Allocate the control data structures, and create and load the 480 * DMA map for it. 481 */ 482 if ((error = bus_dmamem_alloc(sc->sc_dmat, 483 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 484 0)) != 0) { 485 printf("%s: unable to allocate control data, error = %d\n", 486 sc->sc_dev.dv_xname, error); 487 goto fail_0; 488 } 489 490 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 491 sizeof(struct stge_control_data), (caddr_t *)&sc->sc_control_data, 492 BUS_DMA_COHERENT)) != 0) { 493 printf("%s: unable to map control data, error = %d\n", 494 sc->sc_dev.dv_xname, error); 495 goto fail_1; 496 } 497 498 if ((error = bus_dmamap_create(sc->sc_dmat, 499 sizeof(struct stge_control_data), 1, 500 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 501 printf("%s: unable to create control data DMA map, " 502 "error = %d\n", sc->sc_dev.dv_xname, error); 503 goto fail_2; 504 } 505 506 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 507 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 508 0)) != 0) { 509 printf("%s: unable to load control data DMA map, error = %d\n", 510 sc->sc_dev.dv_xname, error); 511 goto fail_3; 512 } 513 514 /* 515 * Create the transmit buffer DMA maps. Note that rev B.3 516 * and earlier seem to have a bug regarding multi-fragment 517 * packets. We need to limit the number of Tx segments on 518 * such chips to 1. 519 */ 520 for (i = 0; i < STGE_NTXDESC; i++) { 521 if ((error = bus_dmamap_create(sc->sc_dmat, 522 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 523 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 524 printf("%s: unable to create tx DMA map %d, " 525 "error = %d\n", sc->sc_dev.dv_xname, i, error); 526 goto fail_4; 527 } 528 } 529 530 /* 531 * Create the receive buffer DMA maps. 532 */ 533 for (i = 0; i < STGE_NRXDESC; i++) { 534 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 535 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 536 printf("%s: unable to create rx DMA map %d, " 537 "error = %d\n", sc->sc_dev.dv_xname, i, error); 538 goto fail_5; 539 } 540 sc->sc_rxsoft[i].ds_mbuf = NULL; 541 } 542 543 /* 544 * Determine if we're copper or fiber. It affects how we 545 * reset the card. 546 */ 547 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 548 AC_PhyMedia) 549 sc->sc_usefiber = 1; 550 else 551 sc->sc_usefiber = 0; 552 553 /* 554 * Reset the chip to a known state. 555 */ 556 stge_reset(sc); 557 558 /* 559 * Reading the station address from the EEPROM doesn't seem 560 * to work, at least on my sample boards. Instread, since 561 * the reset sequence does AutoInit, read it from the station 562 * address registers. 563 */ 564 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh, 565 STGE_StationAddress0) & 0xff; 566 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh, 567 STGE_StationAddress0) >> 8; 568 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh, 569 STGE_StationAddress1) & 0xff; 570 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh, 571 STGE_StationAddress1) >> 8; 572 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh, 573 STGE_StationAddress2) & 0xff; 574 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh, 575 STGE_StationAddress2) >> 8; 576 577 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 578 ether_sprintf(enaddr)); 579 580 /* 581 * Read some important bits from the PhyCtrl register. 582 */ 583 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh, 584 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 585 586 /* 587 * Initialize our media structures and probe the MII. 588 */ 589 sc->sc_mii.mii_ifp = ifp; 590 sc->sc_mii.mii_readreg = stge_mii_readreg; 591 sc->sc_mii.mii_writereg = stge_mii_writereg; 592 sc->sc_mii.mii_statchg = stge_mii_statchg; 593 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, stge_mediachange, 594 stge_mediastatus); 595 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 596 MII_OFFSET_ANY, MIIF_DOPAUSE); 597 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 598 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 599 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 600 } else 601 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 602 603 ifp = &sc->sc_ethercom.ec_if; 604 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 605 ifp->if_softc = sc; 606 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 607 ifp->if_ioctl = stge_ioctl; 608 ifp->if_start = stge_start; 609 ifp->if_watchdog = stge_watchdog; 610 ifp->if_init = stge_init; 611 ifp->if_stop = stge_stop; 612 IFQ_SET_READY(&ifp->if_snd); 613 614 /* 615 * The manual recommends disabling early transmit, so we 616 * do. It's disabled anyway, if using IP checksumming, 617 * since the entire packet must be in the FIFO in order 618 * for the chip to perform the checksum. 619 */ 620 sc->sc_txthresh = 0x0fff; 621 622 /* 623 * Disable MWI if the PCI layer tells us to. 624 */ 625 sc->sc_DMACtrl = 0; 626 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 627 sc->sc_DMACtrl |= DMAC_MWIDisable; 628 629 /* 630 * We can support 802.1Q VLAN-sized frames and jumbo 631 * Ethernet frames. 632 * 633 * XXX Figure out how to do hw-assisted VLAN tagging in 634 * XXX a reasonable way on this chip. 635 */ 636 sc->sc_ethercom.ec_capabilities |= 637 ETHERCAP_VLAN_MTU /* XXX | ETHERCAP_JUMBO_MTU */; 638 639 /* 640 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 641 */ 642 sc->sc_ethercom.ec_if.if_capabilities |= IFCAP_CSUM_IPv4 | 643 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 644 645 /* 646 * Attach the interface. 647 */ 648 if_attach(ifp); 649 ether_ifattach(ifp, enaddr); 650 651 #ifdef STGE_EVENT_COUNTERS 652 /* 653 * Attach event counters. 654 */ 655 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 656 NULL, sc->sc_dev.dv_xname, "txstall"); 657 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 658 NULL, sc->sc_dev.dv_xname, "txdmaintr"); 659 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 660 NULL, sc->sc_dev.dv_xname, "txindintr"); 661 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 662 NULL, sc->sc_dev.dv_xname, "rxintr"); 663 664 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 665 NULL, sc->sc_dev.dv_xname, "txseg1"); 666 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 667 NULL, sc->sc_dev.dv_xname, "txseg2"); 668 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 669 NULL, sc->sc_dev.dv_xname, "txseg3"); 670 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 671 NULL, sc->sc_dev.dv_xname, "txseg4"); 672 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 673 NULL, sc->sc_dev.dv_xname, "txseg5"); 674 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 675 NULL, sc->sc_dev.dv_xname, "txsegmore"); 676 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 677 NULL, sc->sc_dev.dv_xname, "txcopy"); 678 679 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 680 NULL, sc->sc_dev.dv_xname, "rxipsum"); 681 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 682 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 683 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 684 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 685 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 686 NULL, sc->sc_dev.dv_xname, "txipsum"); 687 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 688 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 689 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 690 NULL, sc->sc_dev.dv_xname, "txudpsum"); 691 #endif /* STGE_EVENT_COUNTERS */ 692 693 /* 694 * Make sure the interface is shutdown during reboot. 695 */ 696 sc->sc_sdhook = shutdownhook_establish(stge_shutdown, sc); 697 if (sc->sc_sdhook == NULL) 698 printf("%s: WARNING: unable to establish shutdown hook\n", 699 sc->sc_dev.dv_xname); 700 return; 701 702 /* 703 * Free any resources we've allocated during the failed attach 704 * attempt. Do this in reverse order and fall through. 705 */ 706 fail_5: 707 for (i = 0; i < STGE_NRXDESC; i++) { 708 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 709 bus_dmamap_destroy(sc->sc_dmat, 710 sc->sc_rxsoft[i].ds_dmamap); 711 } 712 fail_4: 713 for (i = 0; i < STGE_NTXDESC; i++) { 714 if (sc->sc_txsoft[i].ds_dmamap != NULL) 715 bus_dmamap_destroy(sc->sc_dmat, 716 sc->sc_txsoft[i].ds_dmamap); 717 } 718 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 719 fail_3: 720 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 721 fail_2: 722 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 723 sizeof(struct stge_control_data)); 724 fail_1: 725 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 726 fail_0: 727 return; 728 } 729 730 /* 731 * stge_shutdown: 732 * 733 * Make sure the interface is stopped at reboot time. 734 */ 735 void 736 stge_shutdown(void *arg) 737 { 738 struct stge_softc *sc = arg; 739 740 stge_stop(&sc->sc_ethercom.ec_if, 1); 741 } 742 743 static void 744 stge_dma_wait(struct stge_softc *sc) 745 { 746 int i; 747 748 for (i = 0; i < STGE_TIMEOUT; i++) { 749 delay(2); 750 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) & 751 DMAC_TxDMAInProg) == 0) 752 break; 753 } 754 755 if (i == STGE_TIMEOUT) 756 printf("%s: DMA wait timed out\n", sc->sc_dev.dv_xname); 757 } 758 759 /* 760 * stge_start: [ifnet interface function] 761 * 762 * Start packet transmission on the interface. 763 */ 764 void 765 stge_start(struct ifnet *ifp) 766 { 767 struct stge_softc *sc = ifp->if_softc; 768 struct mbuf *m0; 769 struct stge_descsoft *ds; 770 struct stge_tfd *tfd; 771 bus_dmamap_t dmamap; 772 int error, firsttx, nexttx, opending, seg, totlen; 773 uint64_t csum_flags; 774 775 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 776 return; 777 778 /* 779 * Remember the previous number of pending transmissions 780 * and the first descriptor we will use. 781 */ 782 opending = sc->sc_txpending; 783 firsttx = STGE_NEXTTX(sc->sc_txlast); 784 785 /* 786 * Loop through the send queue, setting up transmit descriptors 787 * until we drain the queue, or use up all available transmit 788 * descriptors. 789 */ 790 for (;;) { 791 /* 792 * Grab a packet off the queue. 793 */ 794 IFQ_POLL(&ifp->if_snd, m0); 795 if (m0 == NULL) 796 break; 797 798 /* 799 * Leave one unused descriptor at the end of the 800 * list to prevent wrapping completely around. 801 */ 802 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 803 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 804 break; 805 } 806 807 /* 808 * Get the last and next available transmit descriptor. 809 */ 810 nexttx = STGE_NEXTTX(sc->sc_txlast); 811 tfd = &sc->sc_txdescs[nexttx]; 812 ds = &sc->sc_txsoft[nexttx]; 813 814 dmamap = ds->ds_dmamap; 815 816 /* 817 * Load the DMA map. If this fails, the packet either 818 * didn't fit in the alloted number of segments, or we 819 * were short on resources. For the too-may-segments 820 * case, we simply report an error and drop the packet, 821 * since we can't sanely copy a jumbo packet to a single 822 * buffer. 823 */ 824 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 825 BUS_DMA_NOWAIT); 826 if (error) { 827 if (error == EFBIG) { 828 printf("%s: Tx packet consumes too many " 829 "DMA segments, dropping...\n", 830 sc->sc_dev.dv_xname); 831 IFQ_DEQUEUE(&ifp->if_snd, m0); 832 m_freem(m0); 833 continue; 834 } 835 /* 836 * Short on resources, just stop for now. 837 */ 838 break; 839 } 840 841 IFQ_DEQUEUE(&ifp->if_snd, m0); 842 843 /* 844 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 845 */ 846 847 /* Sync the DMA map. */ 848 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 849 BUS_DMASYNC_PREWRITE); 850 851 /* Initialize the fragment list. */ 852 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 853 tfd->tfd_frags[seg].frag_word0 = 854 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 855 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 856 totlen += dmamap->dm_segs[seg].ds_len; 857 } 858 859 #ifdef STGE_EVENT_COUNTERS 860 switch (dmamap->dm_nsegs) { 861 case 1: 862 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 863 break; 864 case 2: 865 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 866 break; 867 case 3: 868 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 869 break; 870 case 4: 871 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 872 break; 873 case 5: 874 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 875 break; 876 default: 877 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 878 break; 879 } 880 #endif /* STGE_EVENT_COUNTERS */ 881 882 /* 883 * Initialize checksumming flags in the descriptor. 884 * Byte-swap constants so the compiler can optimize. 885 */ 886 csum_flags = 0; 887 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 888 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 889 csum_flags |= htole64(TFD_IPChecksumEnable); 890 } 891 892 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 893 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 894 csum_flags |= htole64(TFD_TCPChecksumEnable); 895 } 896 else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 897 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 898 csum_flags |= htole64(TFD_UDPChecksumEnable); 899 } 900 901 /* 902 * Initialize the descriptor and give it to the chip. 903 */ 904 tfd->tfd_control = htole64(TFD_FrameId(nexttx) | 905 TFD_WordAlign(/*totlen & */3) | 906 TFD_FragCount(seg) | csum_flags | 907 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 908 TFD_TxDMAIndicate : 0)); 909 910 /* Sync the descriptor. */ 911 STGE_CDTXSYNC(sc, nexttx, 912 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 913 914 /* 915 * Kick the transmit DMA logic. 916 */ 917 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl, 918 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 919 920 /* 921 * Store a pointer to the packet so we can free it later. 922 */ 923 ds->ds_mbuf = m0; 924 925 /* Advance the tx pointer. */ 926 sc->sc_txpending++; 927 sc->sc_txlast = nexttx; 928 929 #if NBPFILTER > 0 930 /* 931 * Pass the packet to any BPF listeners. 932 */ 933 if (ifp->if_bpf) 934 bpf_mtap(ifp->if_bpf, m0); 935 #endif /* NBPFILTER > 0 */ 936 } 937 938 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 939 /* No more slots left; notify upper layer. */ 940 ifp->if_flags |= IFF_OACTIVE; 941 } 942 943 if (sc->sc_txpending != opending) { 944 /* 945 * We enqueued packets. If the transmitter was idle, 946 * reset the txdirty pointer. 947 */ 948 if (opending == 0) 949 sc->sc_txdirty = firsttx; 950 951 /* Set a watchdog timer in case the chip flakes out. */ 952 ifp->if_timer = 5; 953 } 954 } 955 956 /* 957 * stge_watchdog: [ifnet interface function] 958 * 959 * Watchdog timer handler. 960 */ 961 void 962 stge_watchdog(struct ifnet *ifp) 963 { 964 struct stge_softc *sc = ifp->if_softc; 965 966 /* 967 * Sweep up first, since we don't interrupt every frame. 968 */ 969 stge_txintr(sc); 970 if (sc->sc_txpending != 0) { 971 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 972 ifp->if_oerrors++; 973 974 (void) stge_init(ifp); 975 976 /* Try to get more packets going. */ 977 stge_start(ifp); 978 } 979 } 980 981 /* 982 * stge_ioctl: [ifnet interface function] 983 * 984 * Handle control requests from the operator. 985 */ 986 int 987 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 988 { 989 struct stge_softc *sc = ifp->if_softc; 990 struct ifreq *ifr = (struct ifreq *)data; 991 int s, error; 992 993 s = splnet(); 994 995 switch (cmd) { 996 case SIOCSIFMEDIA: 997 case SIOCGIFMEDIA: 998 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 999 break; 1000 1001 default: 1002 error = ether_ioctl(ifp, cmd, data); 1003 if (error == ENETRESET) { 1004 /* 1005 * Multicast list has changed; set the hardware filter 1006 * accordingly. 1007 */ 1008 stge_set_filter(sc); 1009 error = 0; 1010 } 1011 break; 1012 } 1013 1014 /* Try to get more packets going. */ 1015 stge_start(ifp); 1016 1017 splx(s); 1018 return (error); 1019 } 1020 1021 /* 1022 * stge_intr: 1023 * 1024 * Interrupt service routine. 1025 */ 1026 int 1027 stge_intr(void *arg) 1028 { 1029 struct stge_softc *sc = arg; 1030 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1031 uint32_t txstat; 1032 int wantinit; 1033 uint16_t isr; 1034 1035 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) & 1036 IS_InterruptStatus) == 0) 1037 return (0); 1038 1039 for (wantinit = 0; wantinit == 0;) { 1040 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck); 1041 if ((isr & sc->sc_IntEnable) == 0) 1042 break; 1043 1044 /* Receive interrupts. */ 1045 if (isr & (IE_RxDMAComplete|IE_RFDListEnd)) { 1046 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1047 stge_rxintr(sc); 1048 if (isr & IE_RFDListEnd) { 1049 printf("%s: receive ring overflow\n", 1050 sc->sc_dev.dv_xname); 1051 /* 1052 * XXX Should try to recover from this 1053 * XXX more gracefully. 1054 */ 1055 wantinit = 1; 1056 } 1057 } 1058 1059 /* Transmit interrupts. */ 1060 if (isr & (IE_TxDMAComplete|IE_TxComplete)) { 1061 #ifdef STGE_EVENT_COUNTERS 1062 if (isr & IE_TxDMAComplete) 1063 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1064 #endif 1065 stge_txintr(sc); 1066 } 1067 1068 /* Statistics overflow. */ 1069 if (isr & IE_UpdateStats) 1070 stge_stats_update(sc); 1071 1072 /* Transmission errors. */ 1073 if (isr & IE_TxComplete) { 1074 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1075 for (;;) { 1076 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh, 1077 STGE_TxStatus); 1078 if ((txstat & TS_TxComplete) == 0) 1079 break; 1080 if (txstat & TS_TxUnderrun) { 1081 sc->sc_txthresh++; 1082 if (sc->sc_txthresh > 0x0fff) 1083 sc->sc_txthresh = 0x0fff; 1084 printf("%s: transmit underrun, new " 1085 "threshold: %d bytes\n", 1086 sc->sc_dev.dv_xname, 1087 sc->sc_txthresh << 5); 1088 } 1089 if (txstat & TS_MaxCollisions) 1090 printf("%s: excessive collisions\n", 1091 sc->sc_dev.dv_xname); 1092 } 1093 wantinit = 1; 1094 } 1095 1096 /* Host interface errors. */ 1097 if (isr & IE_HostError) { 1098 printf("%s: Host interface error\n", 1099 sc->sc_dev.dv_xname); 1100 wantinit = 1; 1101 } 1102 } 1103 1104 if (wantinit) 1105 stge_init(ifp); 1106 1107 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 1108 sc->sc_IntEnable); 1109 1110 /* Try to get more packets going. */ 1111 stge_start(ifp); 1112 1113 return (1); 1114 } 1115 1116 /* 1117 * stge_txintr: 1118 * 1119 * Helper; handle transmit interrupts. 1120 */ 1121 void 1122 stge_txintr(struct stge_softc *sc) 1123 { 1124 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1125 struct stge_descsoft *ds; 1126 uint64_t control; 1127 int i; 1128 1129 ifp->if_flags &= ~IFF_OACTIVE; 1130 1131 /* 1132 * Go through our Tx list and free mbufs for those 1133 * frames which have been transmitted. 1134 */ 1135 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1136 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1137 ds = &sc->sc_txsoft[i]; 1138 1139 STGE_CDTXSYNC(sc, i, 1140 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1141 1142 control = le64toh(sc->sc_txdescs[i].tfd_control); 1143 if ((control & TFD_TFDDone) == 0) 1144 break; 1145 1146 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1147 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1148 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1149 m_freem(ds->ds_mbuf); 1150 ds->ds_mbuf = NULL; 1151 } 1152 1153 /* Update the dirty transmit buffer pointer. */ 1154 sc->sc_txdirty = i; 1155 1156 /* 1157 * If there are no more pending transmissions, cancel the watchdog 1158 * timer. 1159 */ 1160 if (sc->sc_txpending == 0) 1161 ifp->if_timer = 0; 1162 } 1163 1164 /* 1165 * stge_rxintr: 1166 * 1167 * Helper; handle receive interrupts. 1168 */ 1169 void 1170 stge_rxintr(struct stge_softc *sc) 1171 { 1172 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1173 struct stge_descsoft *ds; 1174 struct mbuf *m, *tailm; 1175 uint64_t status; 1176 int i, len; 1177 1178 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1179 ds = &sc->sc_rxsoft[i]; 1180 1181 STGE_CDRXSYNC(sc, i, 1182 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1183 1184 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1185 1186 if ((status & RFD_RFDDone) == 0) 1187 break; 1188 1189 if (__predict_false(sc->sc_rxdiscard)) { 1190 STGE_INIT_RXDESC(sc, i); 1191 if (status & RFD_FrameEnd) { 1192 /* Reset our state. */ 1193 sc->sc_rxdiscard = 0; 1194 } 1195 continue; 1196 } 1197 1198 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1199 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1200 1201 m = ds->ds_mbuf; 1202 1203 /* 1204 * Add a new receive buffer to the ring. 1205 */ 1206 if (stge_add_rxbuf(sc, i) != 0) { 1207 /* 1208 * Failed, throw away what we've done so 1209 * far, and discard the rest of the packet. 1210 */ 1211 ifp->if_ierrors++; 1212 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1213 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1214 STGE_INIT_RXDESC(sc, i); 1215 if ((status & RFD_FrameEnd) == 0) 1216 sc->sc_rxdiscard = 1; 1217 if (sc->sc_rxhead != NULL) 1218 m_freem(sc->sc_rxhead); 1219 STGE_RXCHAIN_RESET(sc); 1220 continue; 1221 } 1222 1223 #ifdef DIAGNOSTIC 1224 if (status & RFD_FrameStart) { 1225 KASSERT(sc->sc_rxhead == NULL); 1226 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1227 } 1228 #endif 1229 1230 STGE_RXCHAIN_LINK(sc, m); 1231 1232 /* 1233 * If this is not the end of the packet, keep 1234 * looking. 1235 */ 1236 if ((status & RFD_FrameEnd) == 0) { 1237 sc->sc_rxlen += m->m_len; 1238 continue; 1239 } 1240 1241 /* 1242 * Okay, we have the entire packet now... 1243 */ 1244 *sc->sc_rxtailp = NULL; 1245 m = sc->sc_rxhead; 1246 tailm = sc->sc_rxtail; 1247 1248 STGE_RXCHAIN_RESET(sc); 1249 1250 /* 1251 * If the packet had an error, drop it. Note we 1252 * count the error later in the periodic stats update. 1253 */ 1254 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1255 RFD_RxAlignmentError | RFD_RxFCSError | 1256 RFD_RxLengthError)) { 1257 m_freem(m); 1258 continue; 1259 } 1260 1261 /* 1262 * No errors. 1263 * 1264 * Note we have configured the chip to not include 1265 * the CRC at the end of the packet. 1266 */ 1267 len = RFD_RxDMAFrameLen(status); 1268 tailm->m_len = len - sc->sc_rxlen; 1269 1270 /* 1271 * If the packet is small enough to fit in a 1272 * single header mbuf, allocate one and copy 1273 * the data into it. This greatly reduces 1274 * memory consumption when we receive lots 1275 * of small packets. 1276 */ 1277 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1278 struct mbuf *nm; 1279 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1280 if (nm == NULL) { 1281 ifp->if_ierrors++; 1282 m_freem(m); 1283 continue; 1284 } 1285 nm->m_data += 2; 1286 nm->m_pkthdr.len = nm->m_len = len; 1287 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1288 m_freem(m); 1289 m = nm; 1290 } 1291 1292 /* 1293 * Set the incoming checksum information for the packet. 1294 */ 1295 if (status & RFD_IPDetected) { 1296 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1297 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1298 if (status & RFD_IPError) 1299 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1300 if (status & RFD_TCPDetected) { 1301 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1302 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1303 if (status & RFD_TCPError) 1304 m->m_pkthdr.csum_flags |= 1305 M_CSUM_TCP_UDP_BAD; 1306 } else if (status & RFD_UDPDetected) { 1307 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1308 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1309 if (status & RFD_UDPError) 1310 m->m_pkthdr.csum_flags |= 1311 M_CSUM_TCP_UDP_BAD; 1312 } 1313 } 1314 1315 m->m_pkthdr.rcvif = ifp; 1316 m->m_pkthdr.len = len; 1317 1318 #if NBPFILTER > 0 1319 /* 1320 * Pass this up to any BPF listeners, but only 1321 * pass if up the stack if it's for us. 1322 */ 1323 if (ifp->if_bpf) 1324 bpf_mtap(ifp->if_bpf, m); 1325 #endif /* NBPFILTER > 0 */ 1326 1327 /* Pass it on. */ 1328 (*ifp->if_input)(ifp, m); 1329 } 1330 1331 /* Update the receive pointer. */ 1332 sc->sc_rxptr = i; 1333 } 1334 1335 /* 1336 * stge_tick: 1337 * 1338 * One second timer, used to tick the MII. 1339 */ 1340 void 1341 stge_tick(void *arg) 1342 { 1343 struct stge_softc *sc = arg; 1344 int s; 1345 1346 s = splnet(); 1347 mii_tick(&sc->sc_mii); 1348 stge_stats_update(sc); 1349 splx(s); 1350 1351 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1352 } 1353 1354 /* 1355 * stge_stats_update: 1356 * 1357 * Read the TC9021 statistics counters. 1358 */ 1359 void 1360 stge_stats_update(struct stge_softc *sc) 1361 { 1362 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1363 bus_space_tag_t st = sc->sc_st; 1364 bus_space_handle_t sh = sc->sc_sh; 1365 1366 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk); 1367 1368 ifp->if_ipackets += 1369 bus_space_read_4(st, sh, STGE_FramesRcvdOk); 1370 1371 ifp->if_ierrors += 1372 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors); 1373 1374 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk); 1375 1376 ifp->if_opackets += 1377 bus_space_read_4(st, sh, STGE_FramesXmtdOk); 1378 1379 ifp->if_collisions += 1380 bus_space_read_4(st, sh, STGE_LateCollisions) + 1381 bus_space_read_4(st, sh, STGE_MultiColFrames) + 1382 bus_space_read_4(st, sh, STGE_SingleColFrames); 1383 1384 ifp->if_oerrors += 1385 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) + 1386 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal); 1387 } 1388 1389 /* 1390 * stge_reset: 1391 * 1392 * Perform a soft reset on the TC9021. 1393 */ 1394 void 1395 stge_reset(struct stge_softc *sc) 1396 { 1397 uint32_t ac; 1398 int i; 1399 1400 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl); 1401 1402 /* 1403 * Only assert RstOut if we're fiber. We need GMII clocks 1404 * to be present in order for the reset to complete on fiber 1405 * cards. 1406 */ 1407 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl, 1408 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1409 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1410 (sc->sc_usefiber ? AC_RstOut : 0)); 1411 1412 delay(50000); 1413 1414 for (i = 0; i < STGE_TIMEOUT; i++) { 1415 delay(5000); 1416 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 1417 AC_ResetBusy) == 0) 1418 break; 1419 } 1420 1421 if (i == STGE_TIMEOUT) 1422 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1423 1424 delay(1000); 1425 } 1426 1427 /* 1428 * stge_init: [ ifnet interface function ] 1429 * 1430 * Initialize the interface. Must be called at splnet(). 1431 */ 1432 int 1433 stge_init(struct ifnet *ifp) 1434 { 1435 struct stge_softc *sc = ifp->if_softc; 1436 bus_space_tag_t st = sc->sc_st; 1437 bus_space_handle_t sh = sc->sc_sh; 1438 struct stge_descsoft *ds; 1439 int i, error = 0; 1440 1441 /* 1442 * Cancel any pending I/O. 1443 */ 1444 stge_stop(ifp, 0); 1445 1446 /* 1447 * Reset the chip to a known state. 1448 */ 1449 stge_reset(sc); 1450 1451 /* 1452 * Initialize the transmit descriptor ring. 1453 */ 1454 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1455 for (i = 0; i < STGE_NTXDESC; i++) { 1456 sc->sc_txdescs[i].tfd_next = 1457 (uint64_t) STGE_CDTXADDR(sc, STGE_NEXTTX(i)); 1458 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1459 } 1460 sc->sc_txpending = 0; 1461 sc->sc_txdirty = 0; 1462 sc->sc_txlast = STGE_NTXDESC - 1; 1463 1464 /* 1465 * Initialize the receive descriptor and receive job 1466 * descriptor rings. 1467 */ 1468 for (i = 0; i < STGE_NRXDESC; i++) { 1469 ds = &sc->sc_rxsoft[i]; 1470 if (ds->ds_mbuf == NULL) { 1471 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1472 printf("%s: unable to allocate or map rx " 1473 "buffer %d, error = %d\n", 1474 sc->sc_dev.dv_xname, i, error); 1475 /* 1476 * XXX Should attempt to run with fewer receive 1477 * XXX buffers instead of just failing. 1478 */ 1479 stge_rxdrain(sc); 1480 goto out; 1481 } 1482 } else 1483 STGE_INIT_RXDESC(sc, i); 1484 } 1485 sc->sc_rxptr = 0; 1486 sc->sc_rxdiscard = 0; 1487 STGE_RXCHAIN_RESET(sc); 1488 1489 /* Set the station address. */ 1490 bus_space_write_2(st, sh, STGE_StationAddress0, 1491 LLADDR(ifp->if_sadl)[0] | (LLADDR(ifp->if_sadl)[1] << 8)); 1492 bus_space_write_2(st, sh, STGE_StationAddress1, 1493 LLADDR(ifp->if_sadl)[2] | (LLADDR(ifp->if_sadl)[3] << 8)); 1494 bus_space_write_2(st, sh, STGE_StationAddress2, 1495 LLADDR(ifp->if_sadl)[4] | (LLADDR(ifp->if_sadl)[5] << 8)); 1496 1497 /* 1498 * Set the statistics masks. Disable all the RMON stats, 1499 * and disable selected stats in the non-RMON stats registers. 1500 */ 1501 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff); 1502 bus_space_write_4(st, sh, STGE_StatisticsMask, 1503 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1504 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1505 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1506 (1U << 21)); 1507 1508 /* Set up the receive filter. */ 1509 stge_set_filter(sc); 1510 1511 /* 1512 * Give the transmit and receive ring to the chip. 1513 */ 1514 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1515 bus_space_write_4(st, sh, STGE_TFDListPtrLo, 1516 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1517 1518 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1519 bus_space_write_4(st, sh, STGE_RFDListPtrLo, 1520 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1521 1522 /* 1523 * Initialize the Tx auto-poll period. It's OK to make this number 1524 * large (255 is the max, but we use 127) -- we explicitly kick the 1525 * transmit engine when there's actually a packet. 1526 */ 1527 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127); 1528 1529 /* ..and the Rx auto-poll period. */ 1530 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64); 1531 1532 /* Initialize the Tx start threshold. */ 1533 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh); 1534 1535 /* 1536 * Initialize the Rx DMA interrupt control register. We 1537 * request an interrupt after every incoming packet, but 1538 * defer it for 32us (64 * 512 ns). When the number of 1539 * interrupts pending reaches 8, we stop deferring the 1540 * interrupt, and signal it immediately. 1541 */ 1542 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl, 1543 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1544 1545 /* 1546 * Initialize the interrupt mask. 1547 */ 1548 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1549 IE_TxDMAComplete | IE_RxDMAComplete | IE_RFDListEnd; 1550 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff); 1551 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable); 1552 1553 /* 1554 * Configure the DMA engine. 1555 * XXX Should auto-tune TxBurstLimit. 1556 */ 1557 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl | 1558 DMAC_TxBurstLimit(3)); 1559 1560 /* 1561 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1562 * FIFO, and send an un-PAUSE frame when the FIFO is totally 1563 * empty again. 1564 */ 1565 bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16); 1566 bus_space_write_2(st, sh, STGE_FlowOffThresh, 0); 1567 1568 /* 1569 * Set the maximum frame size. 1570 */ 1571 bus_space_write_2(st, sh, STGE_MaxFrameSize, 1572 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1573 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1574 ETHER_VLAN_ENCAP_LEN : 0)); 1575 1576 /* 1577 * Initialize MacCtrl -- do it before setting the media, 1578 * as setting the media will actually program the register. 1579 * 1580 * Note: We have to poke the IFS value before poking 1581 * anything else. 1582 */ 1583 sc->sc_MACCtrl = MC_IFSSelect(0); 1584 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl); 1585 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1586 1587 if (sc->sc_rev >= 6) { /* >= B.2 */ 1588 /* Multi-frag frame bug work-around. */ 1589 bus_space_write_2(st, sh, STGE_DebugCtrl, 1590 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200); 1591 1592 /* Tx Poll Now bug work-around. */ 1593 bus_space_write_2(st, sh, STGE_DebugCtrl, 1594 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010); 1595 } 1596 1597 /* 1598 * Set the current media. 1599 */ 1600 mii_mediachg(&sc->sc_mii); 1601 1602 /* 1603 * Start the one second MII clock. 1604 */ 1605 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1606 1607 /* 1608 * ...all done! 1609 */ 1610 ifp->if_flags |= IFF_RUNNING; 1611 ifp->if_flags &= ~IFF_OACTIVE; 1612 1613 out: 1614 if (error) 1615 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1616 return (error); 1617 } 1618 1619 /* 1620 * stge_drain: 1621 * 1622 * Drain the receive queue. 1623 */ 1624 void 1625 stge_rxdrain(struct stge_softc *sc) 1626 { 1627 struct stge_descsoft *ds; 1628 int i; 1629 1630 for (i = 0; i < STGE_NRXDESC; i++) { 1631 ds = &sc->sc_rxsoft[i]; 1632 if (ds->ds_mbuf != NULL) { 1633 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1634 ds->ds_mbuf->m_next = NULL; 1635 m_freem(ds->ds_mbuf); 1636 ds->ds_mbuf = NULL; 1637 } 1638 } 1639 } 1640 1641 /* 1642 * stge_stop: [ ifnet interface function ] 1643 * 1644 * Stop transmission on the interface. 1645 */ 1646 void 1647 stge_stop(struct ifnet *ifp, int disable) 1648 { 1649 struct stge_softc *sc = ifp->if_softc; 1650 struct stge_descsoft *ds; 1651 int i; 1652 1653 /* 1654 * Stop the one second clock. 1655 */ 1656 callout_stop(&sc->sc_tick_ch); 1657 1658 /* Down the MII. */ 1659 mii_down(&sc->sc_mii); 1660 1661 /* 1662 * Disable interrupts. 1663 */ 1664 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0); 1665 1666 /* 1667 * Stop receiver, transmitter, and stats update. 1668 */ 1669 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, 1670 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1671 1672 /* 1673 * Stop the transmit and receive DMA. 1674 */ 1675 stge_dma_wait(sc); 1676 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0); 1677 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0); 1678 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0); 1679 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0); 1680 1681 /* 1682 * Release any queued transmit buffers. 1683 */ 1684 for (i = 0; i < STGE_NTXDESC; i++) { 1685 ds = &sc->sc_txsoft[i]; 1686 if (ds->ds_mbuf != NULL) { 1687 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1688 m_freem(ds->ds_mbuf); 1689 ds->ds_mbuf = NULL; 1690 } 1691 } 1692 1693 if (disable) 1694 stge_rxdrain(sc); 1695 1696 /* 1697 * Mark the interface down and cancel the watchdog timer. 1698 */ 1699 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1700 ifp->if_timer = 0; 1701 } 1702 1703 #if 0 1704 static int 1705 stge_eeprom_wait(struct stge_softc *sc) 1706 { 1707 int i; 1708 1709 for (i = 0; i < STGE_TIMEOUT; i++) { 1710 delay(1000); 1711 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) & 1712 EC_EepromBusy) == 0) 1713 return (0); 1714 } 1715 return (1); 1716 } 1717 1718 /* 1719 * stge_read_eeprom: 1720 * 1721 * Read data from the serial EEPROM. 1722 */ 1723 void 1724 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1725 { 1726 1727 if (stge_eeprom_wait(sc)) 1728 printf("%s: EEPROM failed to come ready\n", 1729 sc->sc_dev.dv_xname); 1730 1731 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl, 1732 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1733 if (stge_eeprom_wait(sc)) 1734 printf("%s: EEPROM read timed out\n", 1735 sc->sc_dev.dv_xname); 1736 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData); 1737 } 1738 #endif /* 0 */ 1739 1740 /* 1741 * stge_add_rxbuf: 1742 * 1743 * Add a receive buffer to the indicated descriptor. 1744 */ 1745 int 1746 stge_add_rxbuf(struct stge_softc *sc, int idx) 1747 { 1748 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1749 struct mbuf *m; 1750 int error; 1751 1752 MGETHDR(m, M_DONTWAIT, MT_DATA); 1753 if (m == NULL) 1754 return (ENOBUFS); 1755 1756 MCLGET(m, M_DONTWAIT); 1757 if ((m->m_flags & M_EXT) == 0) { 1758 m_freem(m); 1759 return (ENOBUFS); 1760 } 1761 1762 m->m_data = m->m_ext.ext_buf + 2; 1763 m->m_len = MCLBYTES - 2; 1764 1765 if (ds->ds_mbuf != NULL) 1766 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1767 1768 ds->ds_mbuf = m; 1769 1770 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1771 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1772 if (error) { 1773 printf("%s: can't load rx DMA map %d, error = %d\n", 1774 sc->sc_dev.dv_xname, idx, error); 1775 panic("stge_add_rxbuf"); /* XXX */ 1776 } 1777 1778 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1779 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1780 1781 STGE_INIT_RXDESC(sc, idx); 1782 1783 return (0); 1784 } 1785 1786 /* 1787 * stge_set_filter: 1788 * 1789 * Set up the receive filter. 1790 */ 1791 void 1792 stge_set_filter(struct stge_softc *sc) 1793 { 1794 struct ethercom *ec = &sc->sc_ethercom; 1795 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1796 struct ether_multi *enm; 1797 struct ether_multistep step; 1798 uint32_t crc; 1799 uint32_t mchash[2]; 1800 1801 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1802 if (ifp->if_flags & IFF_BROADCAST) 1803 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1804 1805 if (ifp->if_flags & IFF_PROMISC) { 1806 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1807 goto allmulti; 1808 } 1809 1810 /* 1811 * Set up the multicast address filter by passing all multicast 1812 * addresses through a CRC generator, and then using the low-order 1813 * 6 bits as an index into the 64 bit multicast hash table. The 1814 * high order bits select the register, while the rest of the bits 1815 * select the bit within the register. 1816 */ 1817 1818 memset(mchash, 0, sizeof(mchash)); 1819 1820 ETHER_FIRST_MULTI(step, ec, enm); 1821 if (enm == NULL) 1822 goto done; 1823 1824 while (enm != NULL) { 1825 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1826 /* 1827 * We must listen to a range of multicast addresses. 1828 * For now, just accept all multicasts, rather than 1829 * trying to set only those filter bits needed to match 1830 * the range. (At this time, the only use of address 1831 * ranges is for IP multicast routing, for which the 1832 * range is big enough to require all bits set.) 1833 */ 1834 goto allmulti; 1835 } 1836 1837 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1838 1839 /* Just want the 6 least significant bits. */ 1840 crc &= 0x3f; 1841 1842 /* Set the corresponding bit in the hash table. */ 1843 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1844 1845 ETHER_NEXT_MULTI(step, enm); 1846 } 1847 1848 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1849 1850 ifp->if_flags &= ~IFF_ALLMULTI; 1851 goto done; 1852 1853 allmulti: 1854 ifp->if_flags |= IFF_ALLMULTI; 1855 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1856 1857 done: 1858 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1859 /* 1860 * Program the multicast hash table. 1861 */ 1862 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0, 1863 mchash[0]); 1864 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1, 1865 mchash[1]); 1866 } 1867 1868 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_ReceiveMode, 1869 sc->sc_ReceiveMode); 1870 } 1871 1872 /* 1873 * stge_mii_readreg: [mii interface function] 1874 * 1875 * Read a PHY register on the MII of the TC9021. 1876 */ 1877 int 1878 stge_mii_readreg(struct device *self, int phy, int reg) 1879 { 1880 1881 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg)); 1882 } 1883 1884 /* 1885 * stge_mii_writereg: [mii interface function] 1886 * 1887 * Write a PHY register on the MII of the TC9021. 1888 */ 1889 void 1890 stge_mii_writereg(struct device *self, int phy, int reg, int val) 1891 { 1892 1893 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val); 1894 } 1895 1896 /* 1897 * stge_mii_statchg: [mii interface function] 1898 * 1899 * Callback from MII layer when media changes. 1900 */ 1901 void 1902 stge_mii_statchg(struct device *self) 1903 { 1904 struct stge_softc *sc = (struct stge_softc *) self; 1905 1906 if (sc->sc_mii.mii_media_active & IFM_FDX) 1907 sc->sc_MACCtrl |= MC_DuplexSelect; 1908 else 1909 sc->sc_MACCtrl &= ~MC_DuplexSelect; 1910 1911 /* XXX 802.1x flow-control? */ 1912 1913 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl); 1914 } 1915 1916 /* 1917 * sste_mii_bitbang_read: [mii bit-bang interface function] 1918 * 1919 * Read the MII serial port for the MII bit-bang module. 1920 */ 1921 uint32_t 1922 stge_mii_bitbang_read(struct device *self) 1923 { 1924 struct stge_softc *sc = (void *) self; 1925 1926 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl)); 1927 } 1928 1929 /* 1930 * stge_mii_bitbang_write: [mii big-bang interface function] 1931 * 1932 * Write the MII serial port for the MII bit-bang module. 1933 */ 1934 void 1935 stge_mii_bitbang_write(struct device *self, uint32_t val) 1936 { 1937 struct stge_softc *sc = (void *) self; 1938 1939 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl, 1940 val | sc->sc_PhyCtrl); 1941 } 1942 1943 /* 1944 * stge_mediastatus: [ifmedia interface function] 1945 * 1946 * Get the current interface media status. 1947 */ 1948 void 1949 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1950 { 1951 struct stge_softc *sc = ifp->if_softc; 1952 1953 mii_pollstat(&sc->sc_mii); 1954 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1955 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1956 } 1957 1958 /* 1959 * stge_mediachange: [ifmedia interface function] 1960 * 1961 * Set hardware to newly-selected media. 1962 */ 1963 int 1964 stge_mediachange(struct ifnet *ifp) 1965 { 1966 struct stge_softc *sc = ifp->if_softc; 1967 1968 if (ifp->if_flags & IFF_UP) 1969 mii_mediachg(&sc->sc_mii); 1970 return (0); 1971 } 1972