1 /* $NetBSD: if_ti.c,v 1.90 2010/11/13 13:52:07 uebayasi Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.90 2010/11/13 13:52:07 uebayasi Exp $"); 85 86 #include "opt_inet.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/queue.h> 96 #include <sys/device.h> 97 #include <sys/reboot.h> 98 99 #include <net/if.h> 100 #include <net/if_arp.h> 101 #include <net/if_ether.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 105 #include <net/bpf.h> 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/if_inarp.h> 110 #include <netinet/in_systm.h> 111 #include <netinet/ip.h> 112 #endif 113 114 115 #include <sys/bus.h> 116 117 #include <dev/pci/pcireg.h> 118 #include <dev/pci/pcivar.h> 119 #include <dev/pci/pcidevs.h> 120 121 #include <dev/pci/if_tireg.h> 122 123 #include <dev/microcode/tigon/ti_fw.h> 124 #include <dev/microcode/tigon/ti_fw2.h> 125 126 /* 127 * Various supported device vendors/types and their names. 128 */ 129 130 static const struct ti_type ti_devs[] = { 131 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 132 "Alteon AceNIC 1000BASE-SX Ethernet" }, 133 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 134 "Alteon AceNIC 1000BASE-T Ethernet" }, 135 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 136 "3Com 3c985-SX Gigabit Ethernet" }, 137 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 138 "Netgear GA620 1000BASE-SX Ethernet" }, 139 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 140 "Netgear GA620 1000BASE-T Ethernet" }, 141 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 142 "Silicon Graphics Gigabit Ethernet" }, 143 { 0, 0, NULL } 144 }; 145 146 static const struct ti_type *ti_type_match(struct pci_attach_args *); 147 static int ti_probe(device_t, cfdata_t, void *); 148 static void ti_attach(device_t, device_t, void *); 149 static bool ti_shutdown(device_t, int); 150 static void ti_txeof_tigon1(struct ti_softc *); 151 static void ti_txeof_tigon2(struct ti_softc *); 152 static void ti_rxeof(struct ti_softc *); 153 154 static void ti_stats_update(struct ti_softc *); 155 static int ti_encap_tigon1(struct ti_softc *, struct mbuf *, u_int32_t *); 156 static int ti_encap_tigon2(struct ti_softc *, struct mbuf *, u_int32_t *); 157 158 static int ti_intr(void *); 159 static void ti_start(struct ifnet *); 160 static int ti_ioctl(struct ifnet *, u_long, void *); 161 static void ti_init(void *); 162 static void ti_init2(struct ti_softc *); 163 static void ti_stop(struct ti_softc *); 164 static void ti_watchdog(struct ifnet *); 165 static int ti_ifmedia_upd(struct ifnet *); 166 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 167 168 static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int); 169 static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *); 170 static int ti_read_eeprom(struct ti_softc *, void *, int, int); 171 172 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 173 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 174 static void ti_setmulti(struct ti_softc *); 175 176 static void ti_mem(struct ti_softc *, u_int32_t, u_int32_t, const void *); 177 static void ti_loadfw(struct ti_softc *); 178 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 179 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, void *, int); 180 static void ti_handle_events(struct ti_softc *); 181 static int ti_alloc_jumbo_mem(struct ti_softc *); 182 static void *ti_jalloc(struct ti_softc *); 183 static void ti_jfree(struct mbuf *, void *, size_t, void *); 184 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 185 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 186 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 187 static int ti_init_rx_ring_std(struct ti_softc *); 188 static void ti_free_rx_ring_std(struct ti_softc *); 189 static int ti_init_rx_ring_jumbo(struct ti_softc *); 190 static void ti_free_rx_ring_jumbo(struct ti_softc *); 191 static int ti_init_rx_ring_mini(struct ti_softc *); 192 static void ti_free_rx_ring_mini(struct ti_softc *); 193 static void ti_free_tx_ring(struct ti_softc *); 194 static int ti_init_tx_ring(struct ti_softc *); 195 196 static int ti_64bitslot_war(struct ti_softc *); 197 static int ti_chipinit(struct ti_softc *); 198 static int ti_gibinit(struct ti_softc *); 199 200 static int ti_ether_ioctl(struct ifnet *, u_long, void *); 201 202 CFATTACH_DECL(ti, sizeof(struct ti_softc), 203 ti_probe, ti_attach, NULL, NULL); 204 205 /* 206 * Send an instruction or address to the EEPROM, check for ACK. 207 */ 208 static u_int32_t 209 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 210 { 211 int i, ack = 0; 212 213 /* 214 * Make sure we're in TX mode. 215 */ 216 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 217 218 /* 219 * Feed in each bit and stobe the clock. 220 */ 221 for (i = 0x80; i; i >>= 1) { 222 if (byte & i) { 223 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 224 } else { 225 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 226 } 227 DELAY(1); 228 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 229 DELAY(1); 230 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 231 } 232 233 /* 234 * Turn off TX mode. 235 */ 236 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 237 238 /* 239 * Check for ack. 240 */ 241 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 242 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 243 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 244 245 return (ack); 246 } 247 248 /* 249 * Read a byte of data stored in the EEPROM at address 'addr.' 250 * We have to send two address bytes since the EEPROM can hold 251 * more than 256 bytes of data. 252 */ 253 static u_int8_t 254 ti_eeprom_getbyte(struct ti_softc *sc, int addr, u_int8_t *dest) 255 { 256 int i; 257 u_int8_t byte = 0; 258 259 EEPROM_START(); 260 261 /* 262 * Send write control code to EEPROM. 263 */ 264 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 265 printf("%s: failed to send write command, status: %x\n", 266 device_xname(&sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 267 return (1); 268 } 269 270 /* 271 * Send first byte of address of byte we want to read. 272 */ 273 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 274 printf("%s: failed to send address, status: %x\n", 275 device_xname(&sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 276 return (1); 277 } 278 /* 279 * Send second byte address of byte we want to read. 280 */ 281 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 282 printf("%s: failed to send address, status: %x\n", 283 device_xname(&sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 284 return (1); 285 } 286 287 EEPROM_STOP(); 288 EEPROM_START(); 289 /* 290 * Send read control code to EEPROM. 291 */ 292 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 293 printf("%s: failed to send read command, status: %x\n", 294 device_xname(&sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 295 return (1); 296 } 297 298 /* 299 * Start reading bits from EEPROM. 300 */ 301 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 302 for (i = 0x80; i; i >>= 1) { 303 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 304 DELAY(1); 305 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 306 byte |= i; 307 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 308 DELAY(1); 309 } 310 311 EEPROM_STOP(); 312 313 /* 314 * No ACK generated for read, so just return byte. 315 */ 316 317 *dest = byte; 318 319 return (0); 320 } 321 322 /* 323 * Read a sequence of bytes from the EEPROM. 324 */ 325 static int 326 ti_read_eeprom(struct ti_softc *sc, void *destv, int off, int cnt) 327 { 328 char *dest = destv; 329 int err = 0, i; 330 u_int8_t byte = 0; 331 332 for (i = 0; i < cnt; i++) { 333 err = ti_eeprom_getbyte(sc, off + i, &byte); 334 if (err) 335 break; 336 *(dest + i) = byte; 337 } 338 339 return (err ? 1 : 0); 340 } 341 342 /* 343 * NIC memory access function. Can be used to either clear a section 344 * of NIC local memory or (if tbuf is non-NULL) copy data into it. 345 */ 346 static void 347 ti_mem(struct ti_softc *sc, u_int32_t addr, u_int32_t len, const void *xbuf) 348 { 349 int segptr, segsize, cnt; 350 const void *ptr; 351 352 segptr = addr; 353 cnt = len; 354 ptr = xbuf; 355 356 while (cnt) { 357 if (cnt < TI_WINLEN) 358 segsize = cnt; 359 else 360 segsize = TI_WINLEN - (segptr % TI_WINLEN); 361 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 362 if (xbuf == NULL) { 363 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 364 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 365 segsize / 4); 366 } else { 367 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 368 bus_space_write_region_stream_4(sc->ti_btag, 369 sc->ti_bhandle, 370 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 371 (const u_int32_t *)ptr, segsize / 4); 372 #else 373 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 374 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 375 (const u_int32_t *)ptr, segsize / 4); 376 #endif 377 ptr = (const char *)ptr + segsize; 378 } 379 segptr += segsize; 380 cnt -= segsize; 381 } 382 383 return; 384 } 385 386 /* 387 * Load firmware image into the NIC. Check that the firmware revision 388 * is acceptable and see if we want the firmware for the Tigon 1 or 389 * Tigon 2. 390 */ 391 static void 392 ti_loadfw(struct ti_softc *sc) 393 { 394 switch (sc->ti_hwrev) { 395 case TI_HWREV_TIGON: 396 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 397 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 398 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 399 printf("%s: firmware revision mismatch; want " 400 "%d.%d.%d, got %d.%d.%d\n", device_xname(&sc->sc_dev), 401 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 402 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 403 tigonFwReleaseMinor, tigonFwReleaseFix); 404 return; 405 } 406 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 407 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 408 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, tigonFwRodata); 409 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 410 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 411 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 412 break; 413 case TI_HWREV_TIGON_II: 414 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 415 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 416 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 417 printf("%s: firmware revision mismatch; want " 418 "%d.%d.%d, got %d.%d.%d\n", device_xname(&sc->sc_dev), 419 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 420 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 421 tigon2FwReleaseMinor, tigon2FwReleaseFix); 422 return; 423 } 424 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, tigon2FwText); 425 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, tigon2FwData); 426 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 427 tigon2FwRodata); 428 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 429 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 430 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 431 break; 432 default: 433 printf("%s: can't load firmware: unknown hardware rev\n", 434 device_xname(&sc->sc_dev)); 435 break; 436 } 437 438 return; 439 } 440 441 /* 442 * Send the NIC a command via the command ring. 443 */ 444 static void 445 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 446 { 447 u_int32_t index; 448 449 index = sc->ti_cmd_saved_prodidx; 450 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 451 TI_INC(index, TI_CMD_RING_CNT); 452 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 453 sc->ti_cmd_saved_prodidx = index; 454 } 455 456 /* 457 * Send the NIC an extended command. The 'len' parameter specifies the 458 * number of command slots to include after the initial command. 459 */ 460 static void 461 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, void *argv, int len) 462 { 463 char *arg = argv; 464 u_int32_t index; 465 int i; 466 467 index = sc->ti_cmd_saved_prodidx; 468 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 469 TI_INC(index, TI_CMD_RING_CNT); 470 for (i = 0; i < len; i++) { 471 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 472 *(u_int32_t *)(&arg[i * 4])); 473 TI_INC(index, TI_CMD_RING_CNT); 474 } 475 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 476 sc->ti_cmd_saved_prodidx = index; 477 } 478 479 /* 480 * Handle events that have triggered interrupts. 481 */ 482 static void 483 ti_handle_events(struct ti_softc *sc) 484 { 485 struct ti_event_desc *e; 486 487 if (sc->ti_rdata->ti_event_ring == NULL) 488 return; 489 490 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 491 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 492 switch (TI_EVENT_EVENT(e)) { 493 case TI_EV_LINKSTAT_CHANGED: 494 sc->ti_linkstat = TI_EVENT_CODE(e); 495 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) 496 printf("%s: 10/100 link up\n", 497 device_xname(&sc->sc_dev)); 498 else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 499 printf("%s: gigabit link up\n", 500 device_xname(&sc->sc_dev)); 501 else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 502 printf("%s: link down\n", 503 device_xname(&sc->sc_dev)); 504 break; 505 case TI_EV_ERROR: 506 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 507 printf("%s: invalid command\n", 508 device_xname(&sc->sc_dev)); 509 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 510 printf("%s: unknown command\n", 511 device_xname(&sc->sc_dev)); 512 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 513 printf("%s: bad config data\n", 514 device_xname(&sc->sc_dev)); 515 break; 516 case TI_EV_FIRMWARE_UP: 517 ti_init2(sc); 518 break; 519 case TI_EV_STATS_UPDATED: 520 ti_stats_update(sc); 521 break; 522 case TI_EV_RESET_JUMBO_RING: 523 case TI_EV_MCAST_UPDATED: 524 /* Who cares. */ 525 break; 526 default: 527 printf("%s: unknown event: %d\n", 528 device_xname(&sc->sc_dev), TI_EVENT_EVENT(e)); 529 break; 530 } 531 /* Advance the consumer index. */ 532 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 533 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 534 } 535 536 return; 537 } 538 539 /* 540 * Memory management for the jumbo receive ring is a pain in the 541 * butt. We need to allocate at least 9018 bytes of space per frame, 542 * _and_ it has to be contiguous (unless you use the extended 543 * jumbo descriptor format). Using malloc() all the time won't 544 * work: malloc() allocates memory in powers of two, which means we 545 * would end up wasting a considerable amount of space by allocating 546 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 547 * to do our own memory management. 548 * 549 * The driver needs to allocate a contiguous chunk of memory at boot 550 * time. We then chop this up ourselves into 9K pieces and use them 551 * as external mbuf storage. 552 * 553 * One issue here is how much memory to allocate. The jumbo ring has 554 * 256 slots in it, but at 9K per slot than can consume over 2MB of 555 * RAM. This is a bit much, especially considering we also need 556 * RAM for the standard ring and mini ring (on the Tigon 2). To 557 * save space, we only actually allocate enough memory for 64 slots 558 * by default, which works out to between 500 and 600K. This can 559 * be tuned by changing a #define in if_tireg.h. 560 */ 561 562 static int 563 ti_alloc_jumbo_mem(struct ti_softc *sc) 564 { 565 char *ptr; 566 int i; 567 struct ti_jpool_entry *entry; 568 bus_dma_segment_t dmaseg; 569 int error, dmanseg; 570 571 /* Grab a big chunk o' storage. */ 572 if ((error = bus_dmamem_alloc(sc->sc_dmat, 573 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 574 BUS_DMA_NOWAIT)) != 0) { 575 aprint_error_dev(&sc->sc_dev, "can't allocate jumbo buffer, error = %d\n", 576 error); 577 return (error); 578 } 579 580 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 581 TI_JMEM, (void **)&sc->ti_cdata.ti_jumbo_buf, 582 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 583 aprint_error_dev(&sc->sc_dev, "can't map jumbo buffer, error = %d\n", 584 error); 585 return (error); 586 } 587 588 if ((error = bus_dmamap_create(sc->sc_dmat, 589 TI_JMEM, 1, 590 TI_JMEM, 0, BUS_DMA_NOWAIT, 591 &sc->jumbo_dmamap)) != 0) { 592 aprint_error_dev(&sc->sc_dev, "can't create jumbo buffer DMA map, error = %d\n", 593 error); 594 return (error); 595 } 596 597 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 598 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 599 BUS_DMA_NOWAIT)) != 0) { 600 aprint_error_dev(&sc->sc_dev, "can't load jumbo buffer DMA map, error = %d\n", 601 error); 602 return (error); 603 } 604 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 605 606 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 607 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 608 609 /* 610 * Now divide it up into 9K pieces and save the addresses 611 * in an array. 612 */ 613 ptr = sc->ti_cdata.ti_jumbo_buf; 614 for (i = 0; i < TI_JSLOTS; i++) { 615 sc->ti_cdata.ti_jslots[i] = ptr; 616 ptr += TI_JLEN; 617 entry = malloc(sizeof(struct ti_jpool_entry), 618 M_DEVBUF, M_NOWAIT); 619 if (entry == NULL) { 620 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 621 sc->ti_cdata.ti_jumbo_buf = NULL; 622 printf("%s: no memory for jumbo " 623 "buffer queue!\n", device_xname(&sc->sc_dev)); 624 return (ENOBUFS); 625 } 626 entry->slot = i; 627 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 628 jpool_entries); 629 } 630 631 return (0); 632 } 633 634 /* 635 * Allocate a jumbo buffer. 636 */ 637 static void * 638 ti_jalloc(struct ti_softc *sc) 639 { 640 struct ti_jpool_entry *entry; 641 642 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 643 644 if (entry == NULL) { 645 printf("%s: no free jumbo buffers\n", device_xname(&sc->sc_dev)); 646 return (NULL); 647 } 648 649 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 650 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 651 652 return (sc->ti_cdata.ti_jslots[entry->slot]); 653 } 654 655 /* 656 * Release a jumbo buffer. 657 */ 658 static void 659 ti_jfree(struct mbuf *m, void *tbuf, size_t size, void *arg) 660 { 661 struct ti_softc *sc; 662 int i, s; 663 struct ti_jpool_entry *entry; 664 665 /* Extract the softc struct pointer. */ 666 sc = (struct ti_softc *)arg; 667 668 if (sc == NULL) 669 panic("ti_jfree: didn't get softc pointer!"); 670 671 /* calculate the slot this buffer belongs to */ 672 673 i = ((char *)tbuf 674 - (char *)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 675 676 if ((i < 0) || (i >= TI_JSLOTS)) 677 panic("ti_jfree: asked to free buffer that we don't manage!"); 678 679 s = splvm(); 680 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 681 if (entry == NULL) 682 panic("ti_jfree: buffer not in use!"); 683 entry->slot = i; 684 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 685 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 686 687 if (__predict_true(m != NULL)) 688 pool_cache_put(mb_cache, m); 689 splx(s); 690 } 691 692 693 /* 694 * Intialize a standard receive ring descriptor. 695 */ 696 static int 697 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 698 { 699 struct mbuf *m_new = NULL; 700 struct ti_rx_desc *r; 701 int error; 702 703 if (dmamap == NULL) { 704 /* if (m) panic() */ 705 706 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 707 MCLBYTES, 0, BUS_DMA_NOWAIT, 708 &dmamap)) != 0) { 709 aprint_error_dev(&sc->sc_dev, "can't create recv map, error = %d\n", 710 error); 711 return (ENOMEM); 712 } 713 } 714 sc->std_dmamap[i] = dmamap; 715 716 if (m == NULL) { 717 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 718 if (m_new == NULL) { 719 aprint_error_dev(&sc->sc_dev, "mbuf allocation failed " 720 "-- packet dropped!\n"); 721 return (ENOBUFS); 722 } 723 724 MCLGET(m_new, M_DONTWAIT); 725 if (!(m_new->m_flags & M_EXT)) { 726 aprint_error_dev(&sc->sc_dev, "cluster allocation failed " 727 "-- packet dropped!\n"); 728 m_freem(m_new); 729 return (ENOBUFS); 730 } 731 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 732 m_adj(m_new, ETHER_ALIGN); 733 734 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 735 mtod(m_new, void *), m_new->m_len, NULL, 736 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 737 aprint_error_dev(&sc->sc_dev, "can't load recv map, error = %d\n", 738 error); 739 return (ENOMEM); 740 } 741 } else { 742 m_new = m; 743 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 744 m_new->m_data = m_new->m_ext.ext_buf; 745 m_adj(m_new, ETHER_ALIGN); 746 747 /* reuse the dmamap */ 748 } 749 750 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 751 r = &sc->ti_rdata->ti_rx_std_ring[i]; 752 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 753 r->ti_type = TI_BDTYPE_RECV_BD; 754 r->ti_flags = 0; 755 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 756 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 757 if (sc->ethercom.ec_if.if_capenable & 758 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 759 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 760 r->ti_len = m_new->m_len; /* == ds_len */ 761 r->ti_idx = i; 762 763 return (0); 764 } 765 766 /* 767 * Intialize a mini receive ring descriptor. This only applies to 768 * the Tigon 2. 769 */ 770 static int 771 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 772 { 773 struct mbuf *m_new = NULL; 774 struct ti_rx_desc *r; 775 int error; 776 777 if (dmamap == NULL) { 778 /* if (m) panic() */ 779 780 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 781 MHLEN, 0, BUS_DMA_NOWAIT, 782 &dmamap)) != 0) { 783 aprint_error_dev(&sc->sc_dev, "can't create recv map, error = %d\n", 784 error); 785 return (ENOMEM); 786 } 787 } 788 sc->mini_dmamap[i] = dmamap; 789 790 if (m == NULL) { 791 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 792 if (m_new == NULL) { 793 aprint_error_dev(&sc->sc_dev, "mbuf allocation failed " 794 "-- packet dropped!\n"); 795 return (ENOBUFS); 796 } 797 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 798 m_adj(m_new, ETHER_ALIGN); 799 800 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 801 mtod(m_new, void *), m_new->m_len, NULL, 802 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 803 aprint_error_dev(&sc->sc_dev, "can't load recv map, error = %d\n", 804 error); 805 return (ENOMEM); 806 } 807 } else { 808 m_new = m; 809 m_new->m_data = m_new->m_pktdat; 810 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 811 m_adj(m_new, ETHER_ALIGN); 812 813 /* reuse the dmamap */ 814 } 815 816 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 817 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 818 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 819 r->ti_type = TI_BDTYPE_RECV_BD; 820 r->ti_flags = TI_BDFLAG_MINI_RING; 821 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 822 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 823 if (sc->ethercom.ec_if.if_capenable & 824 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 825 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 826 r->ti_len = m_new->m_len; /* == ds_len */ 827 r->ti_idx = i; 828 829 return (0); 830 } 831 832 /* 833 * Initialize a jumbo receive ring descriptor. This allocates 834 * a jumbo buffer from the pool managed internally by the driver. 835 */ 836 static int 837 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m) 838 { 839 struct mbuf *m_new = NULL; 840 struct ti_rx_desc *r; 841 842 if (m == NULL) { 843 void * tbuf = NULL; 844 845 /* Allocate the mbuf. */ 846 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 847 if (m_new == NULL) { 848 aprint_error_dev(&sc->sc_dev, "mbuf allocation failed " 849 "-- packet dropped!\n"); 850 return (ENOBUFS); 851 } 852 853 /* Allocate the jumbo buffer */ 854 tbuf = ti_jalloc(sc); 855 if (tbuf == NULL) { 856 m_freem(m_new); 857 aprint_error_dev(&sc->sc_dev, "jumbo allocation failed " 858 "-- packet dropped!\n"); 859 return (ENOBUFS); 860 } 861 862 /* Attach the buffer to the mbuf. */ 863 MEXTADD(m_new, tbuf, ETHER_MAX_LEN_JUMBO, 864 M_DEVBUF, ti_jfree, sc); 865 m_new->m_flags |= M_EXT_RW; 866 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 867 } else { 868 m_new = m; 869 m_new->m_data = m_new->m_ext.ext_buf; 870 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 871 } 872 873 m_adj(m_new, ETHER_ALIGN); 874 /* Set up the descriptor. */ 875 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 876 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 877 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 878 (mtod(m_new, char *) - (char *)sc->ti_cdata.ti_jumbo_buf); 879 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 880 r->ti_flags = TI_BDFLAG_JUMBO_RING; 881 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 882 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 883 if (sc->ethercom.ec_if.if_capenable & 884 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 885 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 886 r->ti_len = m_new->m_len; 887 r->ti_idx = i; 888 889 return (0); 890 } 891 892 /* 893 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 894 * that's 1MB or memory, which is a lot. For now, we fill only the first 895 * 256 ring entries and hope that our CPU is fast enough to keep up with 896 * the NIC. 897 */ 898 static int 899 ti_init_rx_ring_std(struct ti_softc *sc) 900 { 901 int i; 902 struct ti_cmd_desc cmd; 903 904 for (i = 0; i < TI_SSLOTS; i++) { 905 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 906 return (ENOBUFS); 907 }; 908 909 TI_UPDATE_STDPROD(sc, i - 1); 910 sc->ti_std = i - 1; 911 912 return (0); 913 } 914 915 static void 916 ti_free_rx_ring_std(struct ti_softc *sc) 917 { 918 int i; 919 920 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 921 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 922 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 923 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 924 925 /* if (sc->std_dmamap[i] == 0) panic() */ 926 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 927 sc->std_dmamap[i] = 0; 928 } 929 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 930 sizeof(struct ti_rx_desc)); 931 } 932 933 return; 934 } 935 936 static int 937 ti_init_rx_ring_jumbo(struct ti_softc *sc) 938 { 939 int i; 940 struct ti_cmd_desc cmd; 941 942 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 943 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 944 return (ENOBUFS); 945 }; 946 947 TI_UPDATE_JUMBOPROD(sc, i - 1); 948 sc->ti_jumbo = i - 1; 949 950 return (0); 951 } 952 953 static void 954 ti_free_rx_ring_jumbo(struct ti_softc *sc) 955 { 956 int i; 957 958 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 959 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 960 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 961 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 962 } 963 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 964 sizeof(struct ti_rx_desc)); 965 } 966 967 return; 968 } 969 970 static int 971 ti_init_rx_ring_mini(struct ti_softc *sc) 972 { 973 int i; 974 975 for (i = 0; i < TI_MSLOTS; i++) { 976 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 977 return (ENOBUFS); 978 }; 979 980 TI_UPDATE_MINIPROD(sc, i - 1); 981 sc->ti_mini = i - 1; 982 983 return (0); 984 } 985 986 static void 987 ti_free_rx_ring_mini(struct ti_softc *sc) 988 { 989 int i; 990 991 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 992 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 993 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 994 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 995 996 /* if (sc->mini_dmamap[i] == 0) panic() */ 997 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 998 sc->mini_dmamap[i] = 0; 999 } 1000 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 1001 sizeof(struct ti_rx_desc)); 1002 } 1003 1004 return; 1005 } 1006 1007 static void 1008 ti_free_tx_ring(struct ti_softc *sc) 1009 { 1010 int i; 1011 struct txdmamap_pool_entry *dma; 1012 1013 if (sc->ti_rdata->ti_tx_ring == NULL) 1014 return; 1015 1016 for (i = 0; i < TI_TX_RING_CNT; i++) { 1017 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1018 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1019 sc->ti_cdata.ti_tx_chain[i] = NULL; 1020 1021 /* if (sc->txdma[i] == 0) panic() */ 1022 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1023 link); 1024 sc->txdma[i] = 0; 1025 } 1026 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1027 sizeof(struct ti_tx_desc)); 1028 } 1029 1030 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1031 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 1032 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1033 free(dma, M_DEVBUF); 1034 } 1035 1036 return; 1037 } 1038 1039 static int 1040 ti_init_tx_ring(struct ti_softc *sc) 1041 { 1042 int i, error; 1043 bus_dmamap_t dmamap; 1044 struct txdmamap_pool_entry *dma; 1045 1046 sc->ti_txcnt = 0; 1047 sc->ti_tx_saved_considx = 0; 1048 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1049 1050 SIMPLEQ_INIT(&sc->txdma_list); 1051 for (i = 0; i < TI_RSLOTS; i++) { 1052 /* I've seen mbufs with 30 fragments. */ 1053 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO, 1054 40, ETHER_MAX_LEN_JUMBO, 0, 1055 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1056 aprint_error_dev(&sc->sc_dev, "can't create tx map, error = %d\n", 1057 error); 1058 return (ENOMEM); 1059 } 1060 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1061 if (!dma) { 1062 aprint_error_dev(&sc->sc_dev, "can't alloc txdmamap_pool_entry\n"); 1063 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1064 return (ENOMEM); 1065 } 1066 dma->dmamap = dmamap; 1067 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1068 } 1069 1070 return (0); 1071 } 1072 1073 /* 1074 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1075 * but we have to support the old way too so that Tigon 1 cards will 1076 * work. 1077 */ 1078 static void 1079 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 1080 { 1081 struct ti_cmd_desc cmd; 1082 u_int16_t *m; 1083 u_int32_t ext[2] = {0, 0}; 1084 1085 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1086 1087 switch (sc->ti_hwrev) { 1088 case TI_HWREV_TIGON: 1089 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1090 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1091 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1092 break; 1093 case TI_HWREV_TIGON_II: 1094 ext[0] = htons(m[0]); 1095 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1096 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (void *)&ext, 2); 1097 break; 1098 default: 1099 printf("%s: unknown hwrev\n", device_xname(&sc->sc_dev)); 1100 break; 1101 } 1102 1103 return; 1104 } 1105 1106 static void 1107 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 1108 { 1109 struct ti_cmd_desc cmd; 1110 u_int16_t *m; 1111 u_int32_t ext[2] = {0, 0}; 1112 1113 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1114 1115 switch (sc->ti_hwrev) { 1116 case TI_HWREV_TIGON: 1117 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1118 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1119 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1120 break; 1121 case TI_HWREV_TIGON_II: 1122 ext[0] = htons(m[0]); 1123 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1124 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (void *)&ext, 2); 1125 break; 1126 default: 1127 printf("%s: unknown hwrev\n", device_xname(&sc->sc_dev)); 1128 break; 1129 } 1130 1131 return; 1132 } 1133 1134 /* 1135 * Configure the Tigon's multicast address filter. 1136 * 1137 * The actual multicast table management is a bit of a pain, thanks to 1138 * slight brain damage on the part of both Alteon and us. With our 1139 * multicast code, we are only alerted when the multicast address table 1140 * changes and at that point we only have the current list of addresses: 1141 * we only know the current state, not the previous state, so we don't 1142 * actually know what addresses were removed or added. The firmware has 1143 * state, but we can't get our grubby mits on it, and there is no 'delete 1144 * all multicast addresses' command. Hence, we have to maintain our own 1145 * state so we know what addresses have been programmed into the NIC at 1146 * any given time. 1147 */ 1148 static void 1149 ti_setmulti(struct ti_softc *sc) 1150 { 1151 struct ifnet *ifp; 1152 struct ti_cmd_desc cmd; 1153 struct ti_mc_entry *mc; 1154 u_int32_t intrs; 1155 struct ether_multi *enm; 1156 struct ether_multistep step; 1157 1158 ifp = &sc->ethercom.ec_if; 1159 1160 /* Disable interrupts. */ 1161 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1162 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1163 1164 /* First, zot all the existing filters. */ 1165 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1166 ti_del_mcast(sc, &mc->mc_addr); 1167 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1168 free(mc, M_DEVBUF); 1169 } 1170 1171 /* 1172 * Remember all multicast addresses so that we can delete them 1173 * later. Punt if there is a range of addresses or memory shortage. 1174 */ 1175 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 1176 while (enm != NULL) { 1177 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1178 ETHER_ADDR_LEN) != 0) 1179 goto allmulti; 1180 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1181 M_NOWAIT)) == NULL) 1182 goto allmulti; 1183 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1184 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1185 ETHER_NEXT_MULTI(step, enm); 1186 } 1187 1188 /* Accept only programmed multicast addresses */ 1189 ifp->if_flags &= ~IFF_ALLMULTI; 1190 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1191 1192 /* Now program new ones. */ 1193 SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries) 1194 ti_add_mcast(sc, &mc->mc_addr); 1195 1196 /* Re-enable interrupts. */ 1197 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1198 1199 return; 1200 1201 allmulti: 1202 /* No need to keep individual multicast addresses */ 1203 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1204 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1205 free(mc, M_DEVBUF); 1206 } 1207 1208 /* Accept all multicast addresses */ 1209 ifp->if_flags |= IFF_ALLMULTI; 1210 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1211 1212 /* Re-enable interrupts. */ 1213 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1214 } 1215 1216 /* 1217 * Check to see if the BIOS has configured us for a 64 bit slot when 1218 * we aren't actually in one. If we detect this condition, we can work 1219 * around it on the Tigon 2 by setting a bit in the PCI state register, 1220 * but for the Tigon 1 we must give up and abort the interface attach. 1221 */ 1222 static int 1223 ti_64bitslot_war(struct ti_softc *sc) 1224 { 1225 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1226 CSR_WRITE_4(sc, 0x600, 0); 1227 CSR_WRITE_4(sc, 0x604, 0); 1228 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1229 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1230 if (sc->ti_hwrev == TI_HWREV_TIGON) 1231 return (EINVAL); 1232 else { 1233 TI_SETBIT(sc, TI_PCI_STATE, 1234 TI_PCISTATE_32BIT_BUS); 1235 return (0); 1236 } 1237 } 1238 } 1239 1240 return (0); 1241 } 1242 1243 /* 1244 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1245 * self-test results. 1246 */ 1247 static int 1248 ti_chipinit(struct ti_softc *sc) 1249 { 1250 u_int32_t cacheline; 1251 u_int32_t pci_writemax = 0; 1252 u_int32_t rev; 1253 1254 /* Initialize link to down state. */ 1255 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1256 1257 /* Set endianness before we access any non-PCI registers. */ 1258 #if BYTE_ORDER == BIG_ENDIAN 1259 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1260 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1261 #else 1262 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1263 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1264 #endif 1265 1266 /* Check the ROM failed bit to see if self-tests passed. */ 1267 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1268 printf("%s: board self-diagnostics failed!\n", 1269 device_xname(&sc->sc_dev)); 1270 return (ENODEV); 1271 } 1272 1273 /* Halt the CPU. */ 1274 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1275 1276 /* Figure out the hardware revision. */ 1277 rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK; 1278 switch (rev) { 1279 case TI_REV_TIGON_I: 1280 sc->ti_hwrev = TI_HWREV_TIGON; 1281 break; 1282 case TI_REV_TIGON_II: 1283 sc->ti_hwrev = TI_HWREV_TIGON_II; 1284 break; 1285 default: 1286 printf("%s: unsupported chip revision 0x%x\n", 1287 device_xname(&sc->sc_dev), rev); 1288 return (ENODEV); 1289 } 1290 1291 /* Do special setup for Tigon 2. */ 1292 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1293 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1294 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1295 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1296 } 1297 1298 /* Set up the PCI state register. */ 1299 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1300 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1301 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1302 } 1303 1304 /* Clear the read/write max DMA parameters. */ 1305 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1306 TI_PCISTATE_READ_MAXDMA)); 1307 1308 /* Get cache line size. */ 1309 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1310 1311 /* 1312 * If the system has set enabled the PCI memory write 1313 * and invalidate command in the command register, set 1314 * the write max parameter accordingly. This is necessary 1315 * to use MWI with the Tigon 2. 1316 */ 1317 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1318 & PCI_COMMAND_INVALIDATE_ENABLE) { 1319 switch (cacheline) { 1320 case 1: 1321 case 4: 1322 case 8: 1323 case 16: 1324 case 32: 1325 case 64: 1326 break; 1327 default: 1328 /* Disable PCI memory write and invalidate. */ 1329 if (bootverbose) 1330 printf("%s: cache line size %d not " 1331 "supported; disabling PCI MWI\n", 1332 device_xname(&sc->sc_dev), cacheline); 1333 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1334 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1335 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1336 break; 1337 } 1338 } 1339 1340 #ifdef __brokenalpha__ 1341 /* 1342 * From the Alteon sample driver: 1343 * Must insure that we do not cross an 8K (bytes) boundary 1344 * for DMA reads. Our highest limit is 1K bytes. This is a 1345 * restriction on some ALPHA platforms with early revision 1346 * 21174 PCI chipsets, such as the AlphaPC 164lx 1347 */ 1348 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1349 #else 1350 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1351 #endif 1352 1353 /* This sets the min dma param all the way up (0xff). */ 1354 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1355 1356 /* Configure DMA variables. */ 1357 #if BYTE_ORDER == BIG_ENDIAN 1358 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1359 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1360 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1361 TI_OPMODE_DONT_FRAG_JUMBO); 1362 #else 1363 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1364 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1365 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1366 #endif 1367 1368 /* 1369 * Only allow 1 DMA channel to be active at a time. 1370 * I don't think this is a good idea, but without it 1371 * the firmware racks up lots of nicDmaReadRingFull 1372 * errors. 1373 * Incompatible with hardware assisted checksums. 1374 */ 1375 if ((sc->ethercom.ec_if.if_capenable & 1376 (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1377 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1378 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx)) == 0) 1379 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1380 1381 /* Recommended settings from Tigon manual. */ 1382 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1383 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1384 1385 if (ti_64bitslot_war(sc)) { 1386 printf("%s: bios thinks we're in a 64 bit slot, " 1387 "but we aren't", device_xname(&sc->sc_dev)); 1388 return (EINVAL); 1389 } 1390 1391 return (0); 1392 } 1393 1394 /* 1395 * Initialize the general information block and firmware, and 1396 * start the CPU(s) running. 1397 */ 1398 static int 1399 ti_gibinit(struct ti_softc *sc) 1400 { 1401 struct ti_rcb *rcb; 1402 int i; 1403 struct ifnet *ifp; 1404 1405 ifp = &sc->ethercom.ec_if; 1406 1407 /* Disable interrupts for now. */ 1408 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1409 1410 /* Tell the chip where to find the general information block. */ 1411 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1412 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1413 1414 /* Load the firmware into SRAM. */ 1415 ti_loadfw(sc); 1416 1417 /* Set up the contents of the general info and ring control blocks. */ 1418 1419 /* Set up the event ring and producer pointer. */ 1420 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1421 1422 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0); 1423 rcb->ti_flags = 0; 1424 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1425 TI_CDEVPRODADDR(sc); 1426 1427 sc->ti_ev_prodidx.ti_idx = 0; 1428 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1429 sc->ti_ev_saved_considx = 0; 1430 1431 /* Set up the command ring and producer mailbox. */ 1432 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1433 1434 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1435 rcb->ti_flags = 0; 1436 rcb->ti_max_len = 0; 1437 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1438 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1439 } 1440 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1441 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1442 sc->ti_cmd_saved_prodidx = 0; 1443 1444 /* 1445 * Assign the address of the stats refresh buffer. 1446 * We re-use the current stats buffer for this to 1447 * conserve memory. 1448 */ 1449 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1450 TI_CDSTATSADDR(sc); 1451 1452 /* Set up the standard receive ring. */ 1453 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1454 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0); 1455 rcb->ti_max_len = ETHER_MAX_LEN; 1456 rcb->ti_flags = 0; 1457 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1458 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1459 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 1460 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1461 if (VLAN_ATTACHED(&sc->ethercom)) 1462 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1463 1464 /* Set up the jumbo receive ring. */ 1465 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1466 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0); 1467 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1468 rcb->ti_flags = 0; 1469 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1470 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1471 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 1472 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1473 if (VLAN_ATTACHED(&sc->ethercom)) 1474 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1475 1476 /* 1477 * Set up the mini ring. Only activated on the 1478 * Tigon 2 but the slot in the config block is 1479 * still there on the Tigon 1. 1480 */ 1481 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1482 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0); 1483 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1484 if (sc->ti_hwrev == TI_HWREV_TIGON) 1485 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1486 else 1487 rcb->ti_flags = 0; 1488 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1489 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1490 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 1491 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1492 if (VLAN_ATTACHED(&sc->ethercom)) 1493 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1494 1495 /* 1496 * Set up the receive return ring. 1497 */ 1498 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1499 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0); 1500 rcb->ti_flags = 0; 1501 rcb->ti_max_len = TI_RETURN_RING_CNT; 1502 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1503 TI_CDRTNPRODADDR(sc); 1504 1505 /* 1506 * Set up the tx ring. Note: for the Tigon 2, we have the option 1507 * of putting the transmit ring in the host's address space and 1508 * letting the chip DMA it instead of leaving the ring in the NIC's 1509 * memory and accessing it through the shared memory region. We 1510 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1511 * so we have to revert to the shared memory scheme if we detect 1512 * a Tigon 1 chip. 1513 */ 1514 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1515 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1516 sc->ti_tx_ring_nic = 1517 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1518 } 1519 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1520 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1521 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1522 if (sc->ti_hwrev == TI_HWREV_TIGON) 1523 rcb->ti_flags = 0; 1524 else 1525 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1526 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) 1527 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1528 /* 1529 * When we get the packet, there is a pseudo-header seed already 1530 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1531 * compute the pseudo-header checksum again! 1532 */ 1533 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 1534 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM| 1535 TI_RCB_FLAG_NO_PHDR_CKSUM; 1536 if (VLAN_ATTACHED(&sc->ethercom)) 1537 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1538 rcb->ti_max_len = TI_TX_RING_CNT; 1539 if (sc->ti_hwrev == TI_HWREV_TIGON) 1540 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1541 else 1542 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0); 1543 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1544 TI_CDTXCONSADDR(sc); 1545 1546 /* 1547 * We're done frobbing the General Information Block. Sync 1548 * it. Note we take care of the first stats sync here, as 1549 * well. 1550 */ 1551 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1552 1553 /* Set up tuneables */ 1554 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1555 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1556 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1557 (sc->ti_rx_coal_ticks / 10)); 1558 else 1559 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1560 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1561 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1562 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1563 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1564 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1565 1566 /* Turn interrupts on. */ 1567 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1568 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1569 1570 /* Start CPU. */ 1571 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1572 1573 return (0); 1574 } 1575 1576 /* 1577 * look for id in the device list, returning the first match 1578 */ 1579 static const struct ti_type * 1580 ti_type_match(struct pci_attach_args *pa) 1581 { 1582 const struct ti_type *t; 1583 1584 t = ti_devs; 1585 while (t->ti_name != NULL) { 1586 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1587 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1588 return (t); 1589 } 1590 t++; 1591 } 1592 1593 return (NULL); 1594 } 1595 1596 /* 1597 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1598 * against our list and return its name if we find a match. 1599 */ 1600 static int 1601 ti_probe(device_t parent, cfdata_t match, void *aux) 1602 { 1603 struct pci_attach_args *pa = aux; 1604 const struct ti_type *t; 1605 1606 t = ti_type_match(pa); 1607 1608 return ((t == NULL) ? 0 : 1); 1609 } 1610 1611 static void 1612 ti_attach(device_t parent, device_t self, void *aux) 1613 { 1614 u_int32_t command; 1615 struct ifnet *ifp; 1616 struct ti_softc *sc; 1617 u_int8_t eaddr[ETHER_ADDR_LEN]; 1618 struct pci_attach_args *pa = aux; 1619 pci_chipset_tag_t pc = pa->pa_pc; 1620 pci_intr_handle_t ih; 1621 const char *intrstr = NULL; 1622 bus_dma_segment_t dmaseg; 1623 int error, dmanseg, nolinear; 1624 const struct ti_type *t; 1625 1626 t = ti_type_match(pa); 1627 if (t == NULL) { 1628 printf("ti_attach: were did the card go ?\n"); 1629 return; 1630 } 1631 1632 printf(": %s (rev. 0x%02x)\n", t->ti_name, PCI_REVISION(pa->pa_class)); 1633 1634 sc = device_private(self); 1635 1636 /* 1637 * Map control/status registers. 1638 */ 1639 nolinear = 0; 1640 if (pci_mapreg_map(pa, 0x10, 1641 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1642 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1643 NULL, NULL)) { 1644 nolinear = 1; 1645 if (pci_mapreg_map(pa, 0x10, 1646 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1647 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1648 printf(": can't map memory space\n"); 1649 return; 1650 } 1651 } 1652 if (nolinear == 0) 1653 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle); 1654 else 1655 sc->ti_vhandle = NULL; 1656 1657 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1658 command |= PCI_COMMAND_MASTER_ENABLE; 1659 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1660 1661 /* Allocate interrupt */ 1662 if (pci_intr_map(pa, &ih)) { 1663 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n"); 1664 return; 1665 } 1666 intrstr = pci_intr_string(pc, ih); 1667 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc); 1668 if (sc->sc_ih == NULL) { 1669 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt"); 1670 if (intrstr != NULL) 1671 aprint_error(" at %s", intrstr); 1672 aprint_error("\n"); 1673 return; 1674 } 1675 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 1676 1677 if (ti_chipinit(sc)) { 1678 aprint_error_dev(self, "chip initialization failed\n"); 1679 goto fail2; 1680 } 1681 1682 /* 1683 * Deal with some chip diffrences. 1684 */ 1685 switch (sc->ti_hwrev) { 1686 case TI_HWREV_TIGON: 1687 sc->sc_tx_encap = ti_encap_tigon1; 1688 sc->sc_tx_eof = ti_txeof_tigon1; 1689 if (nolinear == 1) 1690 aprint_error_dev(self, "memory space not mapped linear\n"); 1691 break; 1692 1693 case TI_HWREV_TIGON_II: 1694 sc->sc_tx_encap = ti_encap_tigon2; 1695 sc->sc_tx_eof = ti_txeof_tigon2; 1696 break; 1697 1698 default: 1699 printf("%s: Unknown chip version: %d\n", device_xname(self), 1700 sc->ti_hwrev); 1701 goto fail2; 1702 } 1703 1704 /* Zero out the NIC's on-board SRAM. */ 1705 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1706 1707 /* Init again -- zeroing memory may have clobbered some registers. */ 1708 if (ti_chipinit(sc)) { 1709 aprint_error_dev(self, "chip initialization failed\n"); 1710 goto fail2; 1711 } 1712 1713 /* 1714 * Get station address from the EEPROM. Note: the manual states 1715 * that the MAC address is at offset 0x8c, however the data is 1716 * stored as two longwords (since that's how it's loaded into 1717 * the NIC). This means the MAC address is actually preceded 1718 * by two zero bytes. We need to skip over those. 1719 */ 1720 if (ti_read_eeprom(sc, (void *)&eaddr, 1721 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1722 aprint_error_dev(self, "failed to read station address\n"); 1723 goto fail2; 1724 } 1725 1726 /* 1727 * A Tigon chip was detected. Inform the world. 1728 */ 1729 aprint_error_dev(self, "Ethernet address: %s\n", 1730 ether_sprintf(eaddr)); 1731 1732 sc->sc_dmat = pa->pa_dmat; 1733 1734 /* Allocate the general information block and ring buffers. */ 1735 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1736 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1737 BUS_DMA_NOWAIT)) != 0) { 1738 aprint_error_dev(&sc->sc_dev, "can't allocate ring buffer, error = %d\n", 1739 error); 1740 goto fail2; 1741 } 1742 1743 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1744 sizeof(struct ti_ring_data), (void **)&sc->ti_rdata, 1745 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1746 aprint_error_dev(&sc->sc_dev, "can't map ring buffer, error = %d\n", 1747 error); 1748 goto fail2; 1749 } 1750 1751 if ((error = bus_dmamap_create(sc->sc_dmat, 1752 sizeof(struct ti_ring_data), 1, 1753 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1754 &sc->info_dmamap)) != 0) { 1755 aprint_error_dev(&sc->sc_dev, "can't create ring buffer DMA map, error = %d\n", 1756 error); 1757 goto fail2; 1758 } 1759 1760 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1761 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1762 BUS_DMA_NOWAIT)) != 0) { 1763 aprint_error_dev(&sc->sc_dev, "can't load ring buffer DMA map, error = %d\n", 1764 error); 1765 goto fail2; 1766 } 1767 1768 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1769 1770 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1771 1772 /* Try to allocate memory for jumbo buffers. */ 1773 if (ti_alloc_jumbo_mem(sc)) { 1774 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 1775 goto fail2; 1776 } 1777 1778 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1779 1780 /* 1781 * We really need a better way to tell a 1000baseT card 1782 * from a 1000baseSX one, since in theory there could be 1783 * OEMed 1000baseT cards from lame vendors who aren't 1784 * clever enough to change the PCI ID. For the moment 1785 * though, the AceNIC is the only copper card available. 1786 */ 1787 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1788 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1789 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1790 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1791 sc->ti_copper = 1; 1792 else 1793 sc->ti_copper = 0; 1794 1795 /* Set default tuneable values. */ 1796 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1797 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1798 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1799 sc->ti_rx_max_coal_bds = 64; 1800 sc->ti_tx_max_coal_bds = 128; 1801 sc->ti_tx_buf_ratio = 21; 1802 1803 /* Set up ifnet structure */ 1804 ifp = &sc->ethercom.ec_if; 1805 ifp->if_softc = sc; 1806 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 1807 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1808 ifp->if_ioctl = ti_ioctl; 1809 ifp->if_start = ti_start; 1810 ifp->if_watchdog = ti_watchdog; 1811 IFQ_SET_READY(&ifp->if_snd); 1812 1813 #if 0 1814 /* 1815 * XXX This is not really correct -- we don't necessarily 1816 * XXX want to queue up as many as we can transmit at the 1817 * XXX upper layer like that. Someone with a board should 1818 * XXX check to see how this affects performance. 1819 */ 1820 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1821 #endif 1822 1823 /* 1824 * We can support 802.1Q VLAN-sized frames. 1825 */ 1826 sc->ethercom.ec_capabilities |= 1827 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1828 1829 /* 1830 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1831 */ 1832 ifp->if_capabilities |= 1833 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1834 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1835 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1836 1837 /* Set up ifmedia support. */ 1838 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1839 if (sc->ti_copper) { 1840 /* 1841 * Copper cards allow manual 10/100 mode selection, 1842 * but not manual 1000baseT mode selection. Why? 1843 * Because currently there's no way to specify the 1844 * master/slave setting through the firmware interface, 1845 * so Alteon decided to just bag it and handle it 1846 * via autonegotiation. 1847 */ 1848 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1849 ifmedia_add(&sc->ifmedia, 1850 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1851 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1852 ifmedia_add(&sc->ifmedia, 1853 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1854 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 1855 ifmedia_add(&sc->ifmedia, 1856 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 1857 } else { 1858 /* Fiber cards don't support 10/100 modes. */ 1859 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1860 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1861 } 1862 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1863 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1864 1865 /* 1866 * Call MI attach routines. 1867 */ 1868 if_attach(ifp); 1869 ether_ifattach(ifp, eaddr); 1870 1871 /* 1872 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1873 * doing do could allow DMA to corrupt kernel memory during the 1874 * reboot before the driver initializes. 1875 */ 1876 if (pmf_device_register1(self, NULL, NULL, ti_shutdown)) 1877 pmf_class_network_register(self, ifp); 1878 else 1879 aprint_error_dev(self, "couldn't establish power handler\n"); 1880 1881 return; 1882 fail2: 1883 pci_intr_disestablish(pc, sc->sc_ih); 1884 return; 1885 } 1886 1887 /* 1888 * Frame reception handling. This is called if there's a frame 1889 * on the receive return list. 1890 * 1891 * Note: we have to be able to handle three possibilities here: 1892 * 1) the frame is from the mini receive ring (can only happen) 1893 * on Tigon 2 boards) 1894 * 2) the frame is from the jumbo receive ring 1895 * 3) the frame is from the standard receive ring 1896 */ 1897 1898 static void 1899 ti_rxeof(struct ti_softc *sc) 1900 { 1901 struct ifnet *ifp; 1902 struct ti_cmd_desc cmd; 1903 1904 ifp = &sc->ethercom.ec_if; 1905 1906 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1907 struct ti_rx_desc *cur_rx; 1908 u_int32_t rxidx; 1909 struct mbuf *m = NULL; 1910 struct ether_header *eh; 1911 bus_dmamap_t dmamap; 1912 1913 cur_rx = 1914 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1915 rxidx = cur_rx->ti_idx; 1916 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1917 1918 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1919 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1920 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1921 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1922 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1923 ifp->if_ierrors++; 1924 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1925 continue; 1926 } 1927 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1928 == ENOBUFS) { 1929 ifp->if_ierrors++; 1930 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1931 continue; 1932 } 1933 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1934 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1935 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1936 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1937 dmamap = sc->mini_dmamap[rxidx]; 1938 sc->mini_dmamap[rxidx] = 0; 1939 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1940 ifp->if_ierrors++; 1941 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1942 continue; 1943 } 1944 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1945 == ENOBUFS) { 1946 ifp->if_ierrors++; 1947 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1948 continue; 1949 } 1950 } else { 1951 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1952 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1953 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1954 dmamap = sc->std_dmamap[rxidx]; 1955 sc->std_dmamap[rxidx] = 0; 1956 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1957 ifp->if_ierrors++; 1958 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1959 continue; 1960 } 1961 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 1962 == ENOBUFS) { 1963 ifp->if_ierrors++; 1964 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1965 continue; 1966 } 1967 } 1968 1969 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1970 ifp->if_ipackets++; 1971 m->m_pkthdr.rcvif = ifp; 1972 1973 /* 1974 * Handle BPF listeners. Let the BPF user see the packet, but 1975 * don't pass it up to the ether_input() layer unless it's 1976 * a broadcast packet, multicast packet, matches our ethernet 1977 * address or the interface is in promiscuous mode. 1978 */ 1979 bpf_mtap(ifp, m); 1980 1981 eh = mtod(m, struct ether_header *); 1982 switch (ntohs(eh->ether_type)) { 1983 #ifdef INET 1984 case ETHERTYPE_IP: 1985 { 1986 struct ip *ip = (struct ip *) (eh + 1); 1987 1988 /* 1989 * Note the Tigon firmware does not invert 1990 * the checksum for us, hence the XOR. 1991 */ 1992 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1993 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 1994 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1995 /* 1996 * ntohs() the constant so the compiler can 1997 * optimize... 1998 * 1999 * XXX Figure out a sane way to deal with 2000 * fragmented packets. 2001 */ 2002 if ((ip->ip_off & htons(IP_MF|IP_OFFMASK)) == 0) { 2003 switch (ip->ip_p) { 2004 case IPPROTO_TCP: 2005 m->m_pkthdr.csum_data = 2006 cur_rx->ti_tcp_udp_cksum; 2007 m->m_pkthdr.csum_flags |= 2008 M_CSUM_TCPv4|M_CSUM_DATA; 2009 break; 2010 case IPPROTO_UDP: 2011 m->m_pkthdr.csum_data = 2012 cur_rx->ti_tcp_udp_cksum; 2013 m->m_pkthdr.csum_flags |= 2014 M_CSUM_UDPv4|M_CSUM_DATA; 2015 break; 2016 default: 2017 /* Nothing */; 2018 } 2019 } 2020 break; 2021 } 2022 #endif 2023 default: 2024 /* Nothing. */ 2025 break; 2026 } 2027 2028 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2029 VLAN_INPUT_TAG(ifp, m, 2030 /* ti_vlan_tag also has the priority, trim it */ 2031 cur_rx->ti_vlan_tag & 4095, 2032 continue); 2033 } 2034 2035 (*ifp->if_input)(ifp, m); 2036 } 2037 2038 /* Only necessary on the Tigon 1. */ 2039 if (sc->ti_hwrev == TI_HWREV_TIGON) 2040 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2041 sc->ti_rx_saved_considx); 2042 2043 TI_UPDATE_STDPROD(sc, sc->ti_std); 2044 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2045 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2046 } 2047 2048 static void 2049 ti_txeof_tigon1(struct ti_softc *sc) 2050 { 2051 struct ti_tx_desc *cur_tx = NULL; 2052 struct ifnet *ifp; 2053 struct txdmamap_pool_entry *dma; 2054 2055 ifp = &sc->ethercom.ec_if; 2056 2057 /* 2058 * Go through our tx ring and free mbufs for those 2059 * frames that have been sent. 2060 */ 2061 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2062 u_int32_t idx = 0; 2063 2064 idx = sc->ti_tx_saved_considx; 2065 if (idx > 383) 2066 CSR_WRITE_4(sc, TI_WINBASE, 2067 TI_TX_RING_BASE + 6144); 2068 else if (idx > 255) 2069 CSR_WRITE_4(sc, TI_WINBASE, 2070 TI_TX_RING_BASE + 4096); 2071 else if (idx > 127) 2072 CSR_WRITE_4(sc, TI_WINBASE, 2073 TI_TX_RING_BASE + 2048); 2074 else 2075 CSR_WRITE_4(sc, TI_WINBASE, 2076 TI_TX_RING_BASE); 2077 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2078 if (cur_tx->ti_flags & TI_BDFLAG_END) 2079 ifp->if_opackets++; 2080 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2081 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2082 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2083 2084 dma = sc->txdma[idx]; 2085 KDASSERT(dma != NULL); 2086 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2087 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2088 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2089 2090 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2091 sc->txdma[idx] = NULL; 2092 } 2093 sc->ti_txcnt--; 2094 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2095 ifp->if_timer = 0; 2096 } 2097 2098 if (cur_tx != NULL) 2099 ifp->if_flags &= ~IFF_OACTIVE; 2100 } 2101 2102 static void 2103 ti_txeof_tigon2(struct ti_softc *sc) 2104 { 2105 struct ti_tx_desc *cur_tx = NULL; 2106 struct ifnet *ifp; 2107 struct txdmamap_pool_entry *dma; 2108 int firstidx, cnt; 2109 2110 ifp = &sc->ethercom.ec_if; 2111 2112 /* 2113 * Go through our tx ring and free mbufs for those 2114 * frames that have been sent. 2115 */ 2116 firstidx = sc->ti_tx_saved_considx; 2117 cnt = 0; 2118 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2119 u_int32_t idx = 0; 2120 2121 idx = sc->ti_tx_saved_considx; 2122 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2123 if (cur_tx->ti_flags & TI_BDFLAG_END) 2124 ifp->if_opackets++; 2125 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2126 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2127 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2128 2129 dma = sc->txdma[idx]; 2130 KDASSERT(dma != NULL); 2131 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2132 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2133 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2134 2135 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2136 sc->txdma[idx] = NULL; 2137 } 2138 cnt++; 2139 sc->ti_txcnt--; 2140 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2141 ifp->if_timer = 0; 2142 } 2143 2144 if (cnt != 0) 2145 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2146 2147 if (cur_tx != NULL) 2148 ifp->if_flags &= ~IFF_OACTIVE; 2149 } 2150 2151 static int 2152 ti_intr(void *xsc) 2153 { 2154 struct ti_softc *sc; 2155 struct ifnet *ifp; 2156 2157 sc = xsc; 2158 ifp = &sc->ethercom.ec_if; 2159 2160 #ifdef notdef 2161 /* Avoid this for now -- checking this register is expensive. */ 2162 /* Make sure this is really our interrupt. */ 2163 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2164 return (0); 2165 #endif 2166 2167 /* Ack interrupt and stop others from occuring. */ 2168 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2169 2170 if (ifp->if_flags & IFF_RUNNING) { 2171 /* Check RX return ring producer/consumer */ 2172 ti_rxeof(sc); 2173 2174 /* Check TX ring producer/consumer */ 2175 (*sc->sc_tx_eof)(sc); 2176 } 2177 2178 ti_handle_events(sc); 2179 2180 /* Re-enable interrupts. */ 2181 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2182 2183 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2184 IFQ_IS_EMPTY(&ifp->if_snd) == 0) 2185 ti_start(ifp); 2186 2187 return (1); 2188 } 2189 2190 static void 2191 ti_stats_update(struct ti_softc *sc) 2192 { 2193 struct ifnet *ifp; 2194 2195 ifp = &sc->ethercom.ec_if; 2196 2197 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2198 2199 ifp->if_collisions += 2200 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2201 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2202 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2203 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2204 ifp->if_collisions; 2205 2206 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2207 } 2208 2209 /* 2210 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2211 * pointers to descriptors. 2212 */ 2213 static int 2214 ti_encap_tigon1(struct ti_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 2215 { 2216 struct ti_tx_desc *f = NULL; 2217 u_int32_t frag, cur, cnt = 0; 2218 struct txdmamap_pool_entry *dma; 2219 bus_dmamap_t dmamap; 2220 int error, i; 2221 struct m_tag *mtag; 2222 u_int16_t csum_flags = 0; 2223 2224 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2225 if (dma == NULL) { 2226 return ENOMEM; 2227 } 2228 dmamap = dma->dmamap; 2229 2230 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2231 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2232 if (error) { 2233 struct mbuf *m; 2234 int j = 0; 2235 for (m = m_head; m; m = m->m_next) 2236 j++; 2237 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2238 "error %d\n", m_head->m_pkthdr.len, j, error); 2239 return (ENOMEM); 2240 } 2241 2242 cur = frag = *txidx; 2243 2244 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2245 /* IP header checksum field must be 0! */ 2246 csum_flags |= TI_BDFLAG_IP_CKSUM; 2247 } 2248 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2249 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2250 2251 /* XXX fragmented packet checksum capability? */ 2252 2253 /* 2254 * Start packing the mbufs in this chain into 2255 * the fragment pointers. Stop when we run out 2256 * of fragments or hit the end of the mbuf chain. 2257 */ 2258 for (i = 0; i < dmamap->dm_nsegs; i++) { 2259 if (frag > 383) 2260 CSR_WRITE_4(sc, TI_WINBASE, 2261 TI_TX_RING_BASE + 6144); 2262 else if (frag > 255) 2263 CSR_WRITE_4(sc, TI_WINBASE, 2264 TI_TX_RING_BASE + 4096); 2265 else if (frag > 127) 2266 CSR_WRITE_4(sc, TI_WINBASE, 2267 TI_TX_RING_BASE + 2048); 2268 else 2269 CSR_WRITE_4(sc, TI_WINBASE, 2270 TI_TX_RING_BASE); 2271 f = &sc->ti_tx_ring_nic[frag % 128]; 2272 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2273 break; 2274 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2275 f->ti_len = dmamap->dm_segs[i].ds_len; 2276 f->ti_flags = csum_flags; 2277 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head))) { 2278 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2279 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag); 2280 } else { 2281 f->ti_vlan_tag = 0; 2282 } 2283 /* 2284 * Sanity check: avoid coming within 16 descriptors 2285 * of the end of the ring. 2286 */ 2287 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2288 return (ENOBUFS); 2289 cur = frag; 2290 TI_INC(frag, TI_TX_RING_CNT); 2291 cnt++; 2292 } 2293 2294 if (i < dmamap->dm_nsegs) 2295 return (ENOBUFS); 2296 2297 if (frag == sc->ti_tx_saved_considx) 2298 return (ENOBUFS); 2299 2300 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2301 TI_BDFLAG_END; 2302 2303 /* Sync the packet's DMA map. */ 2304 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2305 BUS_DMASYNC_PREWRITE); 2306 2307 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2308 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2309 sc->txdma[cur] = dma; 2310 sc->ti_txcnt += cnt; 2311 2312 *txidx = frag; 2313 2314 return (0); 2315 } 2316 2317 static int 2318 ti_encap_tigon2(struct ti_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 2319 { 2320 struct ti_tx_desc *f = NULL; 2321 u_int32_t frag, firstfrag, cur, cnt = 0; 2322 struct txdmamap_pool_entry *dma; 2323 bus_dmamap_t dmamap; 2324 int error, i; 2325 struct m_tag *mtag; 2326 u_int16_t csum_flags = 0; 2327 2328 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2329 if (dma == NULL) { 2330 return ENOMEM; 2331 } 2332 dmamap = dma->dmamap; 2333 2334 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2335 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2336 if (error) { 2337 struct mbuf *m; 2338 int j = 0; 2339 for (m = m_head; m; m = m->m_next) 2340 j++; 2341 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2342 "error %d\n", m_head->m_pkthdr.len, j, error); 2343 return (ENOMEM); 2344 } 2345 2346 cur = firstfrag = frag = *txidx; 2347 2348 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2349 /* IP header checksum field must be 0! */ 2350 csum_flags |= TI_BDFLAG_IP_CKSUM; 2351 } 2352 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2353 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2354 2355 /* XXX fragmented packet checksum capability? */ 2356 2357 /* 2358 * Start packing the mbufs in this chain into 2359 * the fragment pointers. Stop when we run out 2360 * of fragments or hit the end of the mbuf chain. 2361 */ 2362 for (i = 0; i < dmamap->dm_nsegs; i++) { 2363 f = &sc->ti_rdata->ti_tx_ring[frag]; 2364 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2365 break; 2366 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2367 f->ti_len = dmamap->dm_segs[i].ds_len; 2368 f->ti_flags = csum_flags; 2369 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head))) { 2370 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2371 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag); 2372 } else { 2373 f->ti_vlan_tag = 0; 2374 } 2375 /* 2376 * Sanity check: avoid coming within 16 descriptors 2377 * of the end of the ring. 2378 */ 2379 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2380 return (ENOBUFS); 2381 cur = frag; 2382 TI_INC(frag, TI_TX_RING_CNT); 2383 cnt++; 2384 } 2385 2386 if (i < dmamap->dm_nsegs) 2387 return (ENOBUFS); 2388 2389 if (frag == sc->ti_tx_saved_considx) 2390 return (ENOBUFS); 2391 2392 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2393 2394 /* Sync the packet's DMA map. */ 2395 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2396 BUS_DMASYNC_PREWRITE); 2397 2398 /* Sync the descriptors we are using. */ 2399 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2400 2401 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2402 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2403 sc->txdma[cur] = dma; 2404 sc->ti_txcnt += cnt; 2405 2406 *txidx = frag; 2407 2408 return (0); 2409 } 2410 2411 /* 2412 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2413 * to the mbuf data regions directly in the transmit descriptors. 2414 */ 2415 static void 2416 ti_start(struct ifnet *ifp) 2417 { 2418 struct ti_softc *sc; 2419 struct mbuf *m_head = NULL; 2420 u_int32_t prodidx = 0; 2421 2422 sc = ifp->if_softc; 2423 2424 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2425 2426 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2427 IFQ_POLL(&ifp->if_snd, m_head); 2428 if (m_head == NULL) 2429 break; 2430 2431 /* 2432 * Pack the data into the transmit ring. If we 2433 * don't have room, set the OACTIVE flag and wait 2434 * for the NIC to drain the ring. 2435 */ 2436 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2437 ifp->if_flags |= IFF_OACTIVE; 2438 break; 2439 } 2440 2441 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2442 2443 /* 2444 * If there's a BPF listener, bounce a copy of this frame 2445 * to him. 2446 */ 2447 bpf_mtap(ifp, m_head); 2448 } 2449 2450 /* Transmit */ 2451 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2452 2453 /* 2454 * Set a timeout in case the chip goes out to lunch. 2455 */ 2456 ifp->if_timer = 5; 2457 } 2458 2459 static void 2460 ti_init(void *xsc) 2461 { 2462 struct ti_softc *sc = xsc; 2463 int s; 2464 2465 s = splnet(); 2466 2467 /* Cancel pending I/O and flush buffers. */ 2468 ti_stop(sc); 2469 2470 /* Init the gen info block, ring control blocks and firmware. */ 2471 if (ti_gibinit(sc)) { 2472 aprint_error_dev(&sc->sc_dev, "initialization failure\n"); 2473 splx(s); 2474 return; 2475 } 2476 2477 splx(s); 2478 } 2479 2480 static void 2481 ti_init2(struct ti_softc *sc) 2482 { 2483 struct ti_cmd_desc cmd; 2484 struct ifnet *ifp; 2485 const u_int8_t *m; 2486 struct ifmedia *ifm; 2487 int tmp; 2488 2489 ifp = &sc->ethercom.ec_if; 2490 2491 /* Specify MTU and interface index. */ 2492 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_unit(&sc->sc_dev)); /* ??? */ 2493 2494 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2495 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2496 tmp += ETHER_VLAN_ENCAP_LEN; 2497 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2498 2499 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2500 2501 /* Load our MAC address. */ 2502 m = (const u_int8_t *)CLLADDR(ifp->if_sadl); 2503 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2504 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2505 | (m[4] << 8) | m[5]); 2506 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2507 2508 /* Enable or disable promiscuous mode as needed. */ 2509 if (ifp->if_flags & IFF_PROMISC) { 2510 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2511 } else { 2512 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2513 } 2514 2515 /* Program multicast filter. */ 2516 ti_setmulti(sc); 2517 2518 /* 2519 * If this is a Tigon 1, we should tell the 2520 * firmware to use software packet filtering. 2521 */ 2522 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2523 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2524 } 2525 2526 /* Init RX ring. */ 2527 ti_init_rx_ring_std(sc); 2528 2529 /* Init jumbo RX ring. */ 2530 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2531 ti_init_rx_ring_jumbo(sc); 2532 2533 /* 2534 * If this is a Tigon 2, we can also configure the 2535 * mini ring. 2536 */ 2537 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2538 ti_init_rx_ring_mini(sc); 2539 2540 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2541 sc->ti_rx_saved_considx = 0; 2542 2543 /* Init TX ring. */ 2544 ti_init_tx_ring(sc); 2545 2546 /* Tell firmware we're alive. */ 2547 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2548 2549 /* Enable host interrupts. */ 2550 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2551 2552 ifp->if_flags |= IFF_RUNNING; 2553 ifp->if_flags &= ~IFF_OACTIVE; 2554 2555 /* 2556 * Make sure to set media properly. We have to do this 2557 * here since we have to issue commands in order to set 2558 * the link negotiation and we can't issue commands until 2559 * the firmware is running. 2560 */ 2561 ifm = &sc->ifmedia; 2562 tmp = ifm->ifm_media; 2563 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2564 ti_ifmedia_upd(ifp); 2565 ifm->ifm_media = tmp; 2566 } 2567 2568 /* 2569 * Set media options. 2570 */ 2571 static int 2572 ti_ifmedia_upd(struct ifnet *ifp) 2573 { 2574 struct ti_softc *sc; 2575 struct ifmedia *ifm; 2576 struct ti_cmd_desc cmd; 2577 2578 sc = ifp->if_softc; 2579 ifm = &sc->ifmedia; 2580 2581 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2582 return (EINVAL); 2583 2584 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2585 case IFM_AUTO: 2586 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2587 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2588 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2589 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2590 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2591 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2592 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2593 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2594 break; 2595 case IFM_1000_SX: 2596 case IFM_1000_T: 2597 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2598 CSR_WRITE_4(sc, TI_GCR_GLINK, 2599 TI_GLNK_PREF|TI_GLNK_1000MB|TI_GLNK_FULL_DUPLEX| 2600 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2601 } else { 2602 CSR_WRITE_4(sc, TI_GCR_GLINK, 2603 TI_GLNK_PREF|TI_GLNK_1000MB| 2604 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2605 } 2606 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2607 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2608 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2609 break; 2610 case IFM_100_FX: 2611 case IFM_10_FL: 2612 case IFM_100_TX: 2613 case IFM_10_T: 2614 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2615 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2616 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2617 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2618 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2619 } else { 2620 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2621 } 2622 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2623 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2624 } else { 2625 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2626 } 2627 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2628 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2629 break; 2630 } 2631 2632 sc->ethercom.ec_if.if_baudrate = 2633 ifmedia_baudrate(ifm->ifm_media); 2634 2635 return (0); 2636 } 2637 2638 /* 2639 * Report current media status. 2640 */ 2641 static void 2642 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2643 { 2644 struct ti_softc *sc; 2645 u_int32_t media = 0; 2646 2647 sc = ifp->if_softc; 2648 2649 ifmr->ifm_status = IFM_AVALID; 2650 ifmr->ifm_active = IFM_ETHER; 2651 2652 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2653 return; 2654 2655 ifmr->ifm_status |= IFM_ACTIVE; 2656 2657 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2658 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2659 if (sc->ti_copper) 2660 ifmr->ifm_active |= IFM_1000_T; 2661 else 2662 ifmr->ifm_active |= IFM_1000_SX; 2663 if (media & TI_GLNK_FULL_DUPLEX) 2664 ifmr->ifm_active |= IFM_FDX; 2665 else 2666 ifmr->ifm_active |= IFM_HDX; 2667 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2668 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2669 if (sc->ti_copper) { 2670 if (media & TI_LNK_100MB) 2671 ifmr->ifm_active |= IFM_100_TX; 2672 if (media & TI_LNK_10MB) 2673 ifmr->ifm_active |= IFM_10_T; 2674 } else { 2675 if (media & TI_LNK_100MB) 2676 ifmr->ifm_active |= IFM_100_FX; 2677 if (media & TI_LNK_10MB) 2678 ifmr->ifm_active |= IFM_10_FL; 2679 } 2680 if (media & TI_LNK_FULL_DUPLEX) 2681 ifmr->ifm_active |= IFM_FDX; 2682 if (media & TI_LNK_HALF_DUPLEX) 2683 ifmr->ifm_active |= IFM_HDX; 2684 } 2685 2686 sc->ethercom.ec_if.if_baudrate = 2687 ifmedia_baudrate(sc->ifmedia.ifm_media); 2688 } 2689 2690 static int 2691 ti_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2692 { 2693 struct ifaddr *ifa = (struct ifaddr *) data; 2694 struct ti_softc *sc = ifp->if_softc; 2695 2696 if ((ifp->if_flags & IFF_UP) == 0) { 2697 ifp->if_flags |= IFF_UP; 2698 ti_init(sc); 2699 } 2700 2701 switch (cmd) { 2702 case SIOCINITIFADDR: 2703 2704 switch (ifa->ifa_addr->sa_family) { 2705 #ifdef INET 2706 case AF_INET: 2707 arp_ifinit(ifp, ifa); 2708 break; 2709 #endif 2710 default: 2711 break; 2712 } 2713 break; 2714 2715 default: 2716 return (EINVAL); 2717 } 2718 2719 return (0); 2720 } 2721 2722 static int 2723 ti_ioctl(struct ifnet *ifp, u_long command, void *data) 2724 { 2725 struct ti_softc *sc = ifp->if_softc; 2726 struct ifreq *ifr = (struct ifreq *) data; 2727 int s, error = 0; 2728 struct ti_cmd_desc cmd; 2729 2730 s = splnet(); 2731 2732 switch (command) { 2733 case SIOCINITIFADDR: 2734 error = ti_ether_ioctl(ifp, command, data); 2735 break; 2736 case SIOCSIFMTU: 2737 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 2738 error = EINVAL; 2739 else if ((error = ifioctl_common(ifp, command, data)) == ENETRESET){ 2740 ti_init(sc); 2741 error = 0; 2742 } 2743 break; 2744 case SIOCSIFFLAGS: 2745 if ((error = ifioctl_common(ifp, command, data)) != 0) 2746 break; 2747 if (ifp->if_flags & IFF_UP) { 2748 /* 2749 * If only the state of the PROMISC flag changed, 2750 * then just use the 'set promisc mode' command 2751 * instead of reinitializing the entire NIC. Doing 2752 * a full re-init means reloading the firmware and 2753 * waiting for it to start up, which may take a 2754 * second or two. 2755 */ 2756 if (ifp->if_flags & IFF_RUNNING && 2757 ifp->if_flags & IFF_PROMISC && 2758 !(sc->ti_if_flags & IFF_PROMISC)) { 2759 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2760 TI_CMD_CODE_PROMISC_ENB, 0); 2761 } else if (ifp->if_flags & IFF_RUNNING && 2762 !(ifp->if_flags & IFF_PROMISC) && 2763 sc->ti_if_flags & IFF_PROMISC) { 2764 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2765 TI_CMD_CODE_PROMISC_DIS, 0); 2766 } else 2767 ti_init(sc); 2768 } else { 2769 if (ifp->if_flags & IFF_RUNNING) { 2770 ti_stop(sc); 2771 } 2772 } 2773 sc->ti_if_flags = ifp->if_flags; 2774 error = 0; 2775 break; 2776 case SIOCSIFMEDIA: 2777 case SIOCGIFMEDIA: 2778 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2779 break; 2780 default: 2781 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 2782 break; 2783 2784 error = 0; 2785 2786 if (command == SIOCSIFCAP) 2787 ti_init(sc); 2788 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 2789 ; 2790 else if (ifp->if_flags & IFF_RUNNING) 2791 ti_setmulti(sc); 2792 break; 2793 } 2794 2795 (void)splx(s); 2796 2797 return (error); 2798 } 2799 2800 static void 2801 ti_watchdog(struct ifnet *ifp) 2802 { 2803 struct ti_softc *sc; 2804 2805 sc = ifp->if_softc; 2806 2807 aprint_error_dev(&sc->sc_dev, "watchdog timeout -- resetting\n"); 2808 ti_stop(sc); 2809 ti_init(sc); 2810 2811 ifp->if_oerrors++; 2812 } 2813 2814 /* 2815 * Stop the adapter and free any mbufs allocated to the 2816 * RX and TX lists. 2817 */ 2818 static void 2819 ti_stop(struct ti_softc *sc) 2820 { 2821 struct ifnet *ifp; 2822 struct ti_cmd_desc cmd; 2823 2824 ifp = &sc->ethercom.ec_if; 2825 2826 /* Disable host interrupts. */ 2827 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2828 /* 2829 * Tell firmware we're shutting down. 2830 */ 2831 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2832 2833 /* Halt and reinitialize. */ 2834 ti_chipinit(sc); 2835 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2836 ti_chipinit(sc); 2837 2838 /* Free the RX lists. */ 2839 ti_free_rx_ring_std(sc); 2840 2841 /* Free jumbo RX list. */ 2842 ti_free_rx_ring_jumbo(sc); 2843 2844 /* Free mini RX list. */ 2845 ti_free_rx_ring_mini(sc); 2846 2847 /* Free TX buffers. */ 2848 ti_free_tx_ring(sc); 2849 2850 sc->ti_ev_prodidx.ti_idx = 0; 2851 sc->ti_return_prodidx.ti_idx = 0; 2852 sc->ti_tx_considx.ti_idx = 0; 2853 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2854 2855 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2856 } 2857 2858 /* 2859 * Stop all chip I/O so that the kernel's probe routines don't 2860 * get confused by errant DMAs when rebooting. 2861 */ 2862 static bool 2863 ti_shutdown(device_t self, int howto) 2864 { 2865 struct ti_softc *sc; 2866 2867 sc = device_private(self); 2868 ti_chipinit(sc); 2869 2870 return true; 2871 } 2872