1 /* $NetBSD: if_ti.c,v 1.47 2002/05/02 16:22:45 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.47 2002/05/02 16:22:45 thorpej Exp $"); 85 86 #include "bpfilter.h" 87 #include "opt_inet.h" 88 #include "opt_ns.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/queue.h> 98 #include <sys/device.h> 99 #include <sys/reboot.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_ether.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #ifdef INET 114 #include <netinet/in.h> 115 #include <netinet/if_inarp.h> 116 #include <netinet/in_systm.h> 117 #include <netinet/ip.h> 118 #endif 119 120 #ifdef NS 121 #include <netns/ns.h> 122 #include <netns/ns_if.h> 123 #endif 124 125 #include <machine/bus.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/pcidevs.h> 130 131 #include <dev/pci/if_tireg.h> 132 133 #include <dev/microcode/tigon/ti_fw.h> 134 #include <dev/microcode/tigon/ti_fw2.h> 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 140 static const struct ti_type ti_devs[] = { 141 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 142 "Alteon AceNIC 1000BASE-SX Ethernet" }, 143 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 144 "Alteon AceNIC 1000BASE-T Ethernet" }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 146 "3Com 3c985-SX Gigabit Ethernet" }, 147 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 148 "Netgear GA620 1000BASE-SX Ethernet" }, 149 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 150 "Netgear GA620 1000BASE-T Ethernet" }, 151 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 152 "Silicon Graphics Gigabit Ethernet" }, 153 { 0, 0, NULL } 154 }; 155 156 static const struct ti_type *ti_type_match __P((struct pci_attach_args *)); 157 static int ti_probe __P((struct device *, struct cfdata *, void *)); 158 static void ti_attach __P((struct device *, struct device *, void *)); 159 static void ti_shutdown __P((void *)); 160 static void ti_txeof_tigon1 __P((struct ti_softc *)); 161 static void ti_txeof_tigon2 __P((struct ti_softc *)); 162 static void ti_rxeof __P((struct ti_softc *)); 163 164 static void ti_stats_update __P((struct ti_softc *)); 165 static int ti_encap_tigon1 __P((struct ti_softc *, struct mbuf *, 166 u_int32_t *)); 167 static int ti_encap_tigon2 __P((struct ti_softc *, struct mbuf *, 168 u_int32_t *)); 169 170 static int ti_intr __P((void *)); 171 static void ti_start __P((struct ifnet *)); 172 static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 173 static void ti_init __P((void *)); 174 static void ti_init2 __P((struct ti_softc *)); 175 static void ti_stop __P((struct ti_softc *)); 176 static void ti_watchdog __P((struct ifnet *)); 177 static int ti_ifmedia_upd __P((struct ifnet *)); 178 static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 179 180 static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 181 static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 182 int, u_int8_t *)); 183 static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 184 185 static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 186 static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 187 static void ti_setmulti __P((struct ti_softc *)); 188 189 static void ti_mem __P((struct ti_softc *, u_int32_t, 190 u_int32_t, caddr_t)); 191 static void ti_loadfw __P((struct ti_softc *)); 192 static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 193 static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 194 caddr_t, int)); 195 static void ti_handle_events __P((struct ti_softc *)); 196 static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 197 static void *ti_jalloc __P((struct ti_softc *)); 198 static void ti_jfree __P((struct mbuf *, caddr_t, u_int, void *)); 199 static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 200 static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 201 static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 202 static int ti_init_rx_ring_std __P((struct ti_softc *)); 203 static void ti_free_rx_ring_std __P((struct ti_softc *)); 204 static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 205 static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 206 static int ti_init_rx_ring_mini __P((struct ti_softc *)); 207 static void ti_free_rx_ring_mini __P((struct ti_softc *)); 208 static void ti_free_tx_ring __P((struct ti_softc *)); 209 static int ti_init_tx_ring __P((struct ti_softc *)); 210 211 static int ti_64bitslot_war __P((struct ti_softc *)); 212 static int ti_chipinit __P((struct ti_softc *)); 213 static int ti_gibinit __P((struct ti_softc *)); 214 215 static int ti_ether_ioctl __P((struct ifnet *, u_long, caddr_t)); 216 217 struct cfattach ti_ca = { 218 sizeof(struct ti_softc), ti_probe, ti_attach 219 }; 220 221 /* 222 * Send an instruction or address to the EEPROM, check for ACK. 223 */ 224 static u_int32_t ti_eeprom_putbyte(sc, byte) 225 struct ti_softc *sc; 226 int byte; 227 { 228 int i, ack = 0; 229 230 /* 231 * Make sure we're in TX mode. 232 */ 233 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 234 235 /* 236 * Feed in each bit and stobe the clock. 237 */ 238 for (i = 0x80; i; i >>= 1) { 239 if (byte & i) { 240 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 241 } else { 242 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 243 } 244 DELAY(1); 245 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 246 DELAY(1); 247 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 248 } 249 250 /* 251 * Turn off TX mode. 252 */ 253 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 254 255 /* 256 * Check for ack. 257 */ 258 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 259 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 260 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 261 262 return(ack); 263 } 264 265 /* 266 * Read a byte of data stored in the EEPROM at address 'addr.' 267 * We have to send two address bytes since the EEPROM can hold 268 * more than 256 bytes of data. 269 */ 270 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 271 struct ti_softc *sc; 272 int addr; 273 u_int8_t *dest; 274 { 275 int i; 276 u_int8_t byte = 0; 277 278 EEPROM_START; 279 280 /* 281 * Send write control code to EEPROM. 282 */ 283 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 284 printf("%s: failed to send write command, status: %x\n", 285 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 286 return(1); 287 } 288 289 /* 290 * Send first byte of address of byte we want to read. 291 */ 292 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 293 printf("%s: failed to send address, status: %x\n", 294 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 295 return(1); 296 } 297 /* 298 * Send second byte address of byte we want to read. 299 */ 300 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 301 printf("%s: failed to send address, status: %x\n", 302 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 303 return(1); 304 } 305 306 EEPROM_STOP; 307 EEPROM_START; 308 /* 309 * Send read control code to EEPROM. 310 */ 311 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 312 printf("%s: failed to send read command, status: %x\n", 313 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 314 return(1); 315 } 316 317 /* 318 * Start reading bits from EEPROM. 319 */ 320 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 321 for (i = 0x80; i; i >>= 1) { 322 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 323 DELAY(1); 324 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 325 byte |= i; 326 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 327 DELAY(1); 328 } 329 330 EEPROM_STOP; 331 332 /* 333 * No ACK generated for read, so just return byte. 334 */ 335 336 *dest = byte; 337 338 return(0); 339 } 340 341 /* 342 * Read a sequence of bytes from the EEPROM. 343 */ 344 static int ti_read_eeprom(sc, dest, off, cnt) 345 struct ti_softc *sc; 346 caddr_t dest; 347 int off; 348 int cnt; 349 { 350 int err = 0, i; 351 u_int8_t byte = 0; 352 353 for (i = 0; i < cnt; i++) { 354 err = ti_eeprom_getbyte(sc, off + i, &byte); 355 if (err) 356 break; 357 *(dest + i) = byte; 358 } 359 360 return(err ? 1 : 0); 361 } 362 363 /* 364 * NIC memory access function. Can be used to either clear a section 365 * of NIC local memory or (if buf is non-NULL) copy data into it. 366 */ 367 static void ti_mem(sc, addr, len, buf) 368 struct ti_softc *sc; 369 u_int32_t addr, len; 370 caddr_t buf; 371 { 372 int segptr, segsize, cnt; 373 caddr_t ptr; 374 375 segptr = addr; 376 cnt = len; 377 ptr = buf; 378 379 while(cnt) { 380 if (cnt < TI_WINLEN) 381 segsize = cnt; 382 else 383 segsize = TI_WINLEN - (segptr % TI_WINLEN); 384 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 385 if (buf == NULL) { 386 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 387 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 388 segsize / 4); 389 } else { 390 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 391 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 392 (u_int32_t *)ptr, segsize / 4); 393 ptr += segsize; 394 } 395 segptr += segsize; 396 cnt -= segsize; 397 } 398 399 return; 400 } 401 402 /* 403 * Load firmware image into the NIC. Check that the firmware revision 404 * is acceptable and see if we want the firmware for the Tigon 1 or 405 * Tigon 2. 406 */ 407 static void ti_loadfw(sc) 408 struct ti_softc *sc; 409 { 410 switch(sc->ti_hwrev) { 411 case TI_HWREV_TIGON: 412 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 413 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 414 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 415 printf("%s: firmware revision mismatch; want " 416 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 417 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 418 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 419 tigonFwReleaseMinor, tigonFwReleaseFix); 420 return; 421 } 422 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 423 (caddr_t)tigonFwText); 424 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 425 (caddr_t)tigonFwData); 426 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 427 (caddr_t)tigonFwRodata); 428 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 429 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 430 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 431 break; 432 case TI_HWREV_TIGON_II: 433 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 434 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 435 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 436 printf("%s: firmware revision mismatch; want " 437 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 438 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 439 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 440 tigon2FwReleaseMinor, tigon2FwReleaseFix); 441 return; 442 } 443 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 444 (caddr_t)tigon2FwText); 445 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 446 (caddr_t)tigon2FwData); 447 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 448 (caddr_t)tigon2FwRodata); 449 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 450 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 451 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 452 break; 453 default: 454 printf("%s: can't load firmware: unknown hardware rev\n", 455 sc->sc_dev.dv_xname); 456 break; 457 } 458 459 return; 460 } 461 462 /* 463 * Send the NIC a command via the command ring. 464 */ 465 static void ti_cmd(sc, cmd) 466 struct ti_softc *sc; 467 struct ti_cmd_desc *cmd; 468 { 469 u_int32_t index; 470 471 index = sc->ti_cmd_saved_prodidx; 472 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 473 TI_INC(index, TI_CMD_RING_CNT); 474 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 475 sc->ti_cmd_saved_prodidx = index; 476 477 return; 478 } 479 480 /* 481 * Send the NIC an extended command. The 'len' parameter specifies the 482 * number of command slots to include after the initial command. 483 */ 484 static void ti_cmd_ext(sc, cmd, arg, len) 485 struct ti_softc *sc; 486 struct ti_cmd_desc *cmd; 487 caddr_t arg; 488 int len; 489 { 490 u_int32_t index; 491 int i; 492 493 index = sc->ti_cmd_saved_prodidx; 494 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 495 TI_INC(index, TI_CMD_RING_CNT); 496 for (i = 0; i < len; i++) { 497 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 498 *(u_int32_t *)(&arg[i * 4])); 499 TI_INC(index, TI_CMD_RING_CNT); 500 } 501 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 502 sc->ti_cmd_saved_prodidx = index; 503 504 return; 505 } 506 507 /* 508 * Handle events that have triggered interrupts. 509 */ 510 static void ti_handle_events(sc) 511 struct ti_softc *sc; 512 { 513 struct ti_event_desc *e; 514 515 if (sc->ti_rdata->ti_event_ring == NULL) 516 return; 517 518 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 519 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 520 switch(e->ti_event) { 521 case TI_EV_LINKSTAT_CHANGED: 522 sc->ti_linkstat = e->ti_code; 523 if (e->ti_code == TI_EV_CODE_LINK_UP) 524 printf("%s: 10/100 link up\n", 525 sc->sc_dev.dv_xname); 526 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 527 printf("%s: gigabit link up\n", 528 sc->sc_dev.dv_xname); 529 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 530 printf("%s: link down\n", 531 sc->sc_dev.dv_xname); 532 break; 533 case TI_EV_ERROR: 534 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 535 printf("%s: invalid command\n", 536 sc->sc_dev.dv_xname); 537 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 538 printf("%s: unknown command\n", 539 sc->sc_dev.dv_xname); 540 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 541 printf("%s: bad config data\n", 542 sc->sc_dev.dv_xname); 543 break; 544 case TI_EV_FIRMWARE_UP: 545 ti_init2(sc); 546 break; 547 case TI_EV_STATS_UPDATED: 548 ti_stats_update(sc); 549 break; 550 case TI_EV_RESET_JUMBO_RING: 551 case TI_EV_MCAST_UPDATED: 552 /* Who cares. */ 553 break; 554 default: 555 printf("%s: unknown event: %d\n", 556 sc->sc_dev.dv_xname, e->ti_event); 557 break; 558 } 559 /* Advance the consumer index. */ 560 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 561 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 562 } 563 564 return; 565 } 566 567 /* 568 * Memory management for the jumbo receive ring is a pain in the 569 * butt. We need to allocate at least 9018 bytes of space per frame, 570 * _and_ it has to be contiguous (unless you use the extended 571 * jumbo descriptor format). Using malloc() all the time won't 572 * work: malloc() allocates memory in powers of two, which means we 573 * would end up wasting a considerable amount of space by allocating 574 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 575 * to do our own memory management. 576 * 577 * The driver needs to allocate a contiguous chunk of memory at boot 578 * time. We then chop this up ourselves into 9K pieces and use them 579 * as external mbuf storage. 580 * 581 * One issue here is how much memory to allocate. The jumbo ring has 582 * 256 slots in it, but at 9K per slot than can consume over 2MB of 583 * RAM. This is a bit much, especially considering we also need 584 * RAM for the standard ring and mini ring (on the Tigon 2). To 585 * save space, we only actually allocate enough memory for 64 slots 586 * by default, which works out to between 500 and 600K. This can 587 * be tuned by changing a #define in if_tireg.h. 588 */ 589 590 static int ti_alloc_jumbo_mem(sc) 591 struct ti_softc *sc; 592 { 593 caddr_t ptr; 594 int i; 595 struct ti_jpool_entry *entry; 596 bus_dma_segment_t dmaseg; 597 int error, dmanseg; 598 599 /* Grab a big chunk o' storage. */ 600 if ((error = bus_dmamem_alloc(sc->sc_dmat, 601 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 602 BUS_DMA_NOWAIT)) != 0) { 603 printf("%s: can't allocate jumbo buffer, error = %d\n", 604 sc->sc_dev.dv_xname, error); 605 return (error); 606 } 607 608 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 609 TI_JMEM, (caddr_t *)&sc->ti_cdata.ti_jumbo_buf, 610 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 611 printf("%s: can't map jumbo buffer, error = %d\n", 612 sc->sc_dev.dv_xname, error); 613 return (error); 614 } 615 616 if ((error = bus_dmamap_create(sc->sc_dmat, 617 TI_JMEM, 1, 618 TI_JMEM, 0, BUS_DMA_NOWAIT, 619 &sc->jumbo_dmamap)) != 0) { 620 printf("%s: can't create jumbo buffer DMA map, error = %d\n", 621 sc->sc_dev.dv_xname, error); 622 return (error); 623 } 624 625 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 626 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 627 BUS_DMA_NOWAIT)) != 0) { 628 printf("%s: can't load jumbo buffer DMA map, error = %d\n", 629 sc->sc_dev.dv_xname, error); 630 return (error); 631 } 632 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 633 634 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 635 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 636 637 /* 638 * Now divide it up into 9K pieces and save the addresses 639 * in an array. 640 */ 641 ptr = sc->ti_cdata.ti_jumbo_buf; 642 for (i = 0; i < TI_JSLOTS; i++) { 643 sc->ti_cdata.ti_jslots[i] = ptr; 644 ptr += TI_JLEN; 645 entry = malloc(sizeof(struct ti_jpool_entry), 646 M_DEVBUF, M_NOWAIT); 647 if (entry == NULL) { 648 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 649 sc->ti_cdata.ti_jumbo_buf = NULL; 650 printf("%s: no memory for jumbo " 651 "buffer queue!\n", sc->sc_dev.dv_xname); 652 return(ENOBUFS); 653 } 654 entry->slot = i; 655 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 656 jpool_entries); 657 } 658 659 return(0); 660 } 661 662 /* 663 * Allocate a jumbo buffer. 664 */ 665 static void *ti_jalloc(sc) 666 struct ti_softc *sc; 667 { 668 struct ti_jpool_entry *entry; 669 670 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 671 672 if (entry == NULL) { 673 printf("%s: no free jumbo buffers\n", sc->sc_dev.dv_xname); 674 return(NULL); 675 } 676 677 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 678 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 679 return(sc->ti_cdata.ti_jslots[entry->slot]); 680 } 681 682 /* 683 * Release a jumbo buffer. 684 */ 685 static void ti_jfree(m, buf, size, arg) 686 struct mbuf *m; 687 caddr_t buf; 688 u_int size; 689 void *arg; 690 { 691 struct ti_softc *sc; 692 int i, s; 693 struct ti_jpool_entry *entry; 694 695 /* Extract the softc struct pointer. */ 696 sc = (struct ti_softc *)arg; 697 698 if (sc == NULL) 699 panic("ti_jfree: didn't get softc pointer!"); 700 701 /* calculate the slot this buffer belongs to */ 702 703 i = ((caddr_t)buf 704 - (caddr_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 705 706 if ((i < 0) || (i >= TI_JSLOTS)) 707 panic("ti_jfree: asked to free buffer that we don't manage!"); 708 709 s = splvm(); 710 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 711 if (entry == NULL) 712 panic("ti_jfree: buffer not in use!"); 713 entry->slot = i; 714 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, 715 entry, jpool_entries); 716 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, 717 entry, jpool_entries); 718 719 if (__predict_true(m != NULL)) 720 pool_cache_put(&mbpool_cache, m); 721 splx(s); 722 } 723 724 725 /* 726 * Intialize a standard receive ring descriptor. 727 */ 728 static int ti_newbuf_std(sc, i, m, dmamap) 729 struct ti_softc *sc; 730 int i; 731 struct mbuf *m; 732 bus_dmamap_t dmamap; /* required if (m != NULL) */ 733 { 734 struct mbuf *m_new = NULL; 735 struct ti_rx_desc *r; 736 int error; 737 738 if (dmamap == NULL) { 739 /* if (m) panic() */ 740 741 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 742 MCLBYTES, 0, BUS_DMA_NOWAIT, 743 &dmamap)) != 0) { 744 printf("%s: can't create recv map, error = %d\n", 745 sc->sc_dev.dv_xname, error); 746 return(ENOMEM); 747 } 748 } 749 sc->std_dmamap[i] = dmamap; 750 751 if (m == NULL) { 752 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 753 if (m_new == NULL) { 754 printf("%s: mbuf allocation failed " 755 "-- packet dropped!\n", sc->sc_dev.dv_xname); 756 return(ENOBUFS); 757 } 758 759 MCLGET(m_new, M_DONTWAIT); 760 if (!(m_new->m_flags & M_EXT)) { 761 printf("%s: cluster allocation failed " 762 "-- packet dropped!\n", sc->sc_dev.dv_xname); 763 m_freem(m_new); 764 return(ENOBUFS); 765 } 766 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 767 m_adj(m_new, ETHER_ALIGN); 768 769 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 770 mtod(m_new, caddr_t), m_new->m_len, NULL, 771 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 772 printf("%s: can't load recv map, error = %d\n", 773 sc->sc_dev.dv_xname, error); 774 return (ENOMEM); 775 } 776 } else { 777 m_new = m; 778 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 779 m_new->m_data = m_new->m_ext.ext_buf; 780 m_adj(m_new, ETHER_ALIGN); 781 782 /* reuse the dmamap */ 783 } 784 785 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 786 r = &sc->ti_rdata->ti_rx_std_ring[i]; 787 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 788 r->ti_type = TI_BDTYPE_RECV_BD; 789 r->ti_flags = 0; 790 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 791 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 792 if (sc->ethercom.ec_if.if_capenable & 793 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 794 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 795 r->ti_len = m_new->m_len; /* == ds_len */ 796 r->ti_idx = i; 797 798 return(0); 799 } 800 801 /* 802 * Intialize a mini receive ring descriptor. This only applies to 803 * the Tigon 2. 804 */ 805 static int ti_newbuf_mini(sc, i, m, dmamap) 806 struct ti_softc *sc; 807 int i; 808 struct mbuf *m; 809 bus_dmamap_t dmamap; /* required if (m != NULL) */ 810 { 811 struct mbuf *m_new = NULL; 812 struct ti_rx_desc *r; 813 int error; 814 815 if (dmamap == NULL) { 816 /* if (m) panic() */ 817 818 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 819 MHLEN, 0, BUS_DMA_NOWAIT, 820 &dmamap)) != 0) { 821 printf("%s: can't create recv map, error = %d\n", 822 sc->sc_dev.dv_xname, error); 823 return(ENOMEM); 824 } 825 } 826 sc->mini_dmamap[i] = dmamap; 827 828 if (m == NULL) { 829 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 830 if (m_new == NULL) { 831 printf("%s: mbuf allocation failed " 832 "-- packet dropped!\n", sc->sc_dev.dv_xname); 833 return(ENOBUFS); 834 } 835 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 836 m_adj(m_new, ETHER_ALIGN); 837 838 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 839 mtod(m_new, caddr_t), m_new->m_len, NULL, 840 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 841 printf("%s: can't load recv map, error = %d\n", 842 sc->sc_dev.dv_xname, error); 843 return (ENOMEM); 844 } 845 } else { 846 m_new = m; 847 m_new->m_data = m_new->m_pktdat; 848 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 849 m_adj(m_new, ETHER_ALIGN); 850 851 /* reuse the dmamap */ 852 } 853 854 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 855 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 856 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 857 r->ti_type = TI_BDTYPE_RECV_BD; 858 r->ti_flags = TI_BDFLAG_MINI_RING; 859 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 860 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 861 if (sc->ethercom.ec_if.if_capenable & 862 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 863 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 864 r->ti_len = m_new->m_len; /* == ds_len */ 865 r->ti_idx = i; 866 867 return(0); 868 } 869 870 /* 871 * Initialize a jumbo receive ring descriptor. This allocates 872 * a jumbo buffer from the pool managed internally by the driver. 873 */ 874 static int ti_newbuf_jumbo(sc, i, m) 875 struct ti_softc *sc; 876 int i; 877 struct mbuf *m; 878 { 879 struct mbuf *m_new = NULL; 880 struct ti_rx_desc *r; 881 882 if (m == NULL) { 883 caddr_t *buf = NULL; 884 885 /* Allocate the mbuf. */ 886 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 887 if (m_new == NULL) { 888 printf("%s: mbuf allocation failed " 889 "-- packet dropped!\n", sc->sc_dev.dv_xname); 890 return(ENOBUFS); 891 } 892 893 /* Allocate the jumbo buffer */ 894 buf = ti_jalloc(sc); 895 if (buf == NULL) { 896 m_freem(m_new); 897 printf("%s: jumbo allocation failed " 898 "-- packet dropped!\n", sc->sc_dev.dv_xname); 899 return(ENOBUFS); 900 } 901 902 /* Attach the buffer to the mbuf. */ 903 MEXTADD(m_new, (void *)buf, ETHER_MAX_LEN_JUMBO, 904 M_DEVBUF, ti_jfree, sc); 905 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 906 } else { 907 m_new = m; 908 m_new->m_data = m_new->m_ext.ext_buf; 909 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 910 } 911 912 m_adj(m_new, ETHER_ALIGN); 913 /* Set up the descriptor. */ 914 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 915 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 916 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 917 ((caddr_t)mtod(m_new, caddr_t) 918 - (caddr_t)sc->ti_cdata.ti_jumbo_buf); 919 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 920 r->ti_flags = TI_BDFLAG_JUMBO_RING; 921 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 922 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 923 if (sc->ethercom.ec_if.if_capenable & 924 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 925 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 926 r->ti_len = m_new->m_len; 927 r->ti_idx = i; 928 929 return(0); 930 } 931 932 /* 933 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 934 * that's 1MB or memory, which is a lot. For now, we fill only the first 935 * 256 ring entries and hope that our CPU is fast enough to keep up with 936 * the NIC. 937 */ 938 static int ti_init_rx_ring_std(sc) 939 struct ti_softc *sc; 940 { 941 int i; 942 struct ti_cmd_desc cmd; 943 944 for (i = 0; i < TI_SSLOTS; i++) { 945 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 946 return(ENOBUFS); 947 }; 948 949 TI_UPDATE_STDPROD(sc, i - 1); 950 sc->ti_std = i - 1; 951 952 return(0); 953 } 954 955 static void ti_free_rx_ring_std(sc) 956 struct ti_softc *sc; 957 { 958 int i; 959 960 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 961 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 962 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 963 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 964 965 /* if (sc->std_dmamap[i] == 0) panic() */ 966 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 967 sc->std_dmamap[i] = 0; 968 } 969 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 970 sizeof(struct ti_rx_desc)); 971 } 972 973 return; 974 } 975 976 static int ti_init_rx_ring_jumbo(sc) 977 struct ti_softc *sc; 978 { 979 int i; 980 struct ti_cmd_desc cmd; 981 982 for (i = 0; i < (TI_JSLOTS - 20); i++) { 983 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 984 return(ENOBUFS); 985 }; 986 987 TI_UPDATE_JUMBOPROD(sc, i - 1); 988 sc->ti_jumbo = i - 1; 989 990 return(0); 991 } 992 993 static void ti_free_rx_ring_jumbo(sc) 994 struct ti_softc *sc; 995 { 996 int i; 997 998 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 999 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1000 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1001 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1002 } 1003 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 1004 sizeof(struct ti_rx_desc)); 1005 } 1006 1007 return; 1008 } 1009 1010 static int ti_init_rx_ring_mini(sc) 1011 struct ti_softc *sc; 1012 { 1013 int i; 1014 1015 for (i = 0; i < TI_MSLOTS; i++) { 1016 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 1017 return(ENOBUFS); 1018 }; 1019 1020 TI_UPDATE_MINIPROD(sc, i - 1); 1021 sc->ti_mini = i - 1; 1022 1023 return(0); 1024 } 1025 1026 static void ti_free_rx_ring_mini(sc) 1027 struct ti_softc *sc; 1028 { 1029 int i; 1030 1031 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1032 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1033 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1034 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1035 1036 /* if (sc->mini_dmamap[i] == 0) panic() */ 1037 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 1038 sc->mini_dmamap[i] = 0; 1039 } 1040 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 1041 sizeof(struct ti_rx_desc)); 1042 } 1043 1044 return; 1045 } 1046 1047 static void ti_free_tx_ring(sc) 1048 struct ti_softc *sc; 1049 { 1050 int i; 1051 struct txdmamap_pool_entry *dma; 1052 1053 if (sc->ti_rdata->ti_tx_ring == NULL) 1054 return; 1055 1056 for (i = 0; i < TI_TX_RING_CNT; i++) { 1057 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1058 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1059 sc->ti_cdata.ti_tx_chain[i] = NULL; 1060 1061 /* if (sc->txdma[i] == 0) panic() */ 1062 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1063 link); 1064 sc->txdma[i] = 0; 1065 } 1066 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1067 sizeof(struct ti_tx_desc)); 1068 } 1069 1070 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1071 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, dma, link); 1072 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1073 free(dma, M_DEVBUF); 1074 } 1075 1076 return; 1077 } 1078 1079 static int ti_init_tx_ring(sc) 1080 struct ti_softc *sc; 1081 { 1082 int i, error; 1083 bus_dmamap_t dmamap; 1084 struct txdmamap_pool_entry *dma; 1085 1086 sc->ti_txcnt = 0; 1087 sc->ti_tx_saved_considx = 0; 1088 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1089 1090 SIMPLEQ_INIT(&sc->txdma_list); 1091 for (i = 0; i < TI_RSLOTS; i++) { 1092 /* I've seen mbufs with 30 fragments. */ 1093 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO, 1094 40, ETHER_MAX_LEN_JUMBO, 0, 1095 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1096 printf("%s: can't create tx map, error = %d\n", 1097 sc->sc_dev.dv_xname, error); 1098 return(ENOMEM); 1099 } 1100 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1101 if (!dma) { 1102 printf("%s: can't alloc txdmamap_pool_entry\n", 1103 sc->sc_dev.dv_xname); 1104 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1105 return (ENOMEM); 1106 } 1107 dma->dmamap = dmamap; 1108 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1109 } 1110 1111 return(0); 1112 } 1113 1114 /* 1115 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1116 * but we have to support the old way too so that Tigon 1 cards will 1117 * work. 1118 */ 1119 void ti_add_mcast(sc, addr) 1120 struct ti_softc *sc; 1121 struct ether_addr *addr; 1122 { 1123 struct ti_cmd_desc cmd; 1124 u_int16_t *m; 1125 u_int32_t ext[2] = {0, 0}; 1126 1127 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1128 1129 switch(sc->ti_hwrev) { 1130 case TI_HWREV_TIGON: 1131 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1132 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1133 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1134 break; 1135 case TI_HWREV_TIGON_II: 1136 ext[0] = htons(m[0]); 1137 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1138 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1139 break; 1140 default: 1141 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1142 break; 1143 } 1144 1145 return; 1146 } 1147 1148 void ti_del_mcast(sc, addr) 1149 struct ti_softc *sc; 1150 struct ether_addr *addr; 1151 { 1152 struct ti_cmd_desc cmd; 1153 u_int16_t *m; 1154 u_int32_t ext[2] = {0, 0}; 1155 1156 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1157 1158 switch(sc->ti_hwrev) { 1159 case TI_HWREV_TIGON: 1160 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1161 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1162 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1163 break; 1164 case TI_HWREV_TIGON_II: 1165 ext[0] = htons(m[0]); 1166 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1167 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1168 break; 1169 default: 1170 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1171 break; 1172 } 1173 1174 return; 1175 } 1176 1177 /* 1178 * Configure the Tigon's multicast address filter. 1179 * 1180 * The actual multicast table management is a bit of a pain, thanks to 1181 * slight brain damage on the part of both Alteon and us. With our 1182 * multicast code, we are only alerted when the multicast address table 1183 * changes and at that point we only have the current list of addresses: 1184 * we only know the current state, not the previous state, so we don't 1185 * actually know what addresses were removed or added. The firmware has 1186 * state, but we can't get our grubby mits on it, and there is no 'delete 1187 * all multicast addresses' command. Hence, we have to maintain our own 1188 * state so we know what addresses have been programmed into the NIC at 1189 * any given time. 1190 */ 1191 static void ti_setmulti(sc) 1192 struct ti_softc *sc; 1193 { 1194 struct ifnet *ifp; 1195 struct ti_cmd_desc cmd; 1196 struct ti_mc_entry *mc; 1197 u_int32_t intrs; 1198 struct ether_multi *enm; 1199 struct ether_multistep step; 1200 1201 ifp = &sc->ethercom.ec_if; 1202 1203 /* Disable interrupts. */ 1204 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1205 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1206 1207 /* First, zot all the existing filters. */ 1208 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1209 ti_del_mcast(sc, &mc->mc_addr); 1210 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1211 free(mc, M_DEVBUF); 1212 } 1213 1214 /* 1215 * Remember all multicast addresses so that we can delete them 1216 * later. Punt if there is a range of addresses or memory shortage. 1217 */ 1218 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 1219 while (enm != NULL) { 1220 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1221 ETHER_ADDR_LEN) != 0) 1222 goto allmulti; 1223 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1224 M_NOWAIT)) == NULL) 1225 goto allmulti; 1226 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1227 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1228 ETHER_NEXT_MULTI(step, enm); 1229 } 1230 1231 /* Accept only programmed multicast addresses */ 1232 ifp->if_flags &= ~IFF_ALLMULTI; 1233 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1234 1235 /* Now program new ones. */ 1236 for (mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead); mc != NULL; 1237 mc = SIMPLEQ_NEXT(mc, mc_entries)) 1238 ti_add_mcast(sc, &mc->mc_addr); 1239 1240 /* Re-enable interrupts. */ 1241 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1242 1243 return; 1244 1245 allmulti: 1246 /* No need to keep individual multicast addresses */ 1247 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1248 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc, 1249 mc_entries); 1250 free(mc, M_DEVBUF); 1251 } 1252 1253 /* Accept all multicast addresses */ 1254 ifp->if_flags |= IFF_ALLMULTI; 1255 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1256 1257 /* Re-enable interrupts. */ 1258 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1259 } 1260 1261 /* 1262 * Check to see if the BIOS has configured us for a 64 bit slot when 1263 * we aren't actually in one. If we detect this condition, we can work 1264 * around it on the Tigon 2 by setting a bit in the PCI state register, 1265 * but for the Tigon 1 we must give up and abort the interface attach. 1266 */ 1267 static int ti_64bitslot_war(sc) 1268 struct ti_softc *sc; 1269 { 1270 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1271 CSR_WRITE_4(sc, 0x600, 0); 1272 CSR_WRITE_4(sc, 0x604, 0); 1273 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1274 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1275 if (sc->ti_hwrev == TI_HWREV_TIGON) 1276 return(EINVAL); 1277 else { 1278 TI_SETBIT(sc, TI_PCI_STATE, 1279 TI_PCISTATE_32BIT_BUS); 1280 return(0); 1281 } 1282 } 1283 } 1284 1285 return(0); 1286 } 1287 1288 /* 1289 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1290 * self-test results. 1291 */ 1292 static int ti_chipinit(sc) 1293 struct ti_softc *sc; 1294 { 1295 u_int32_t cacheline; 1296 u_int32_t pci_writemax = 0; 1297 1298 /* Initialize link to down state. */ 1299 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1300 1301 /* Set endianness before we access any non-PCI registers. */ 1302 #if BYTE_ORDER == BIG_ENDIAN 1303 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1304 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1305 #else 1306 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1307 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1308 #endif 1309 1310 /* Check the ROM failed bit to see if self-tests passed. */ 1311 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1312 printf("%s: board self-diagnostics failed!\n", 1313 sc->sc_dev.dv_xname); 1314 return(ENODEV); 1315 } 1316 1317 /* Halt the CPU. */ 1318 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1319 1320 /* Figure out the hardware revision. */ 1321 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1322 case TI_REV_TIGON_I: 1323 sc->ti_hwrev = TI_HWREV_TIGON; 1324 break; 1325 case TI_REV_TIGON_II: 1326 sc->ti_hwrev = TI_HWREV_TIGON_II; 1327 break; 1328 default: 1329 printf("%s: unsupported chip revision\n", sc->sc_dev.dv_xname); 1330 return(ENODEV); 1331 } 1332 1333 /* Do special setup for Tigon 2. */ 1334 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1335 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1336 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1337 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1338 } 1339 1340 /* Set up the PCI state register. */ 1341 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1342 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1343 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1344 } 1345 1346 /* Clear the read/write max DMA parameters. */ 1347 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1348 TI_PCISTATE_READ_MAXDMA)); 1349 1350 /* Get cache line size. */ 1351 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1352 1353 /* 1354 * If the system has set enabled the PCI memory write 1355 * and invalidate command in the command register, set 1356 * the write max parameter accordingly. This is necessary 1357 * to use MWI with the Tigon 2. 1358 */ 1359 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1360 & PCI_COMMAND_INVALIDATE_ENABLE) { 1361 switch(cacheline) { 1362 case 1: 1363 case 4: 1364 case 8: 1365 case 16: 1366 case 32: 1367 case 64: 1368 break; 1369 default: 1370 /* Disable PCI memory write and invalidate. */ 1371 if (bootverbose) 1372 printf("%s: cache line size %d not " 1373 "supported; disabling PCI MWI\n", 1374 sc->sc_dev.dv_xname, cacheline); 1375 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1376 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1377 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1378 break; 1379 } 1380 } 1381 1382 #ifdef __brokenalpha__ 1383 /* 1384 * From the Alteon sample driver: 1385 * Must insure that we do not cross an 8K (bytes) boundary 1386 * for DMA reads. Our highest limit is 1K bytes. This is a 1387 * restriction on some ALPHA platforms with early revision 1388 * 21174 PCI chipsets, such as the AlphaPC 164lx 1389 */ 1390 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1391 #else 1392 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1393 #endif 1394 1395 /* This sets the min dma param all the way up (0xff). */ 1396 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1397 1398 /* Configure DMA variables. */ 1399 #if BYTE_ORDER == BIG_ENDIAN 1400 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1401 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1402 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1403 TI_OPMODE_DONT_FRAG_JUMBO); 1404 #else 1405 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1406 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1407 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1408 #endif 1409 1410 /* 1411 * Only allow 1 DMA channel to be active at a time. 1412 * I don't think this is a good idea, but without it 1413 * the firmware racks up lots of nicDmaReadRingFull 1414 * errors. 1415 * Incompatible with hardware assisted checksums. 1416 */ 1417 if ((sc->ethercom.ec_if.if_capenable & 1418 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4|IFCAP_CSUM_IPv4)) == 0) 1419 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1420 1421 /* Recommended settings from Tigon manual. */ 1422 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1423 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1424 1425 if (ti_64bitslot_war(sc)) { 1426 printf("%s: bios thinks we're in a 64 bit slot, " 1427 "but we aren't", sc->sc_dev.dv_xname); 1428 return(EINVAL); 1429 } 1430 1431 return(0); 1432 } 1433 1434 /* 1435 * Initialize the general information block and firmware, and 1436 * start the CPU(s) running. 1437 */ 1438 static int ti_gibinit(sc) 1439 struct ti_softc *sc; 1440 { 1441 struct ti_rcb *rcb; 1442 int i; 1443 struct ifnet *ifp; 1444 1445 ifp = &sc->ethercom.ec_if; 1446 1447 /* Disable interrupts for now. */ 1448 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1449 1450 /* Tell the chip where to find the general information block. */ 1451 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1452 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1453 1454 /* Load the firmware into SRAM. */ 1455 ti_loadfw(sc); 1456 1457 /* Set up the contents of the general info and ring control blocks. */ 1458 1459 /* Set up the event ring and producer pointer. */ 1460 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1461 1462 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0); 1463 rcb->ti_flags = 0; 1464 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1465 TI_CDEVPRODADDR(sc); 1466 1467 sc->ti_ev_prodidx.ti_idx = 0; 1468 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1469 sc->ti_ev_saved_considx = 0; 1470 1471 /* Set up the command ring and producer mailbox. */ 1472 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1473 1474 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1475 rcb->ti_flags = 0; 1476 rcb->ti_max_len = 0; 1477 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1478 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1479 } 1480 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1481 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1482 sc->ti_cmd_saved_prodidx = 0; 1483 1484 /* 1485 * Assign the address of the stats refresh buffer. 1486 * We re-use the current stats buffer for this to 1487 * conserve memory. 1488 */ 1489 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1490 TI_CDSTATSADDR(sc); 1491 1492 /* Set up the standard receive ring. */ 1493 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1494 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0); 1495 rcb->ti_max_len = ETHER_MAX_LEN; 1496 rcb->ti_flags = 0; 1497 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1498 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1499 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1500 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1501 if (sc->ethercom.ec_nvlans != 0) 1502 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1503 1504 /* Set up the jumbo receive ring. */ 1505 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1506 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0); 1507 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1508 rcb->ti_flags = 0; 1509 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1510 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1511 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1512 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1513 if (sc->ethercom.ec_nvlans != 0) 1514 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1515 1516 /* 1517 * Set up the mini ring. Only activated on the 1518 * Tigon 2 but the slot in the config block is 1519 * still there on the Tigon 1. 1520 */ 1521 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1522 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0); 1523 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1524 if (sc->ti_hwrev == TI_HWREV_TIGON) 1525 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1526 else 1527 rcb->ti_flags = 0; 1528 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1529 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1530 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1531 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1532 if (sc->ethercom.ec_nvlans != 0) 1533 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1534 1535 /* 1536 * Set up the receive return ring. 1537 */ 1538 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1539 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0); 1540 rcb->ti_flags = 0; 1541 rcb->ti_max_len = TI_RETURN_RING_CNT; 1542 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1543 TI_CDRTNPRODADDR(sc); 1544 1545 /* 1546 * Set up the tx ring. Note: for the Tigon 2, we have the option 1547 * of putting the transmit ring in the host's address space and 1548 * letting the chip DMA it instead of leaving the ring in the NIC's 1549 * memory and accessing it through the shared memory region. We 1550 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1551 * so we have to revert to the shared memory scheme if we detect 1552 * a Tigon 1 chip. 1553 */ 1554 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1555 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1556 sc->ti_tx_ring_nic = 1557 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1558 } 1559 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1560 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1561 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1562 if (sc->ti_hwrev == TI_HWREV_TIGON) 1563 rcb->ti_flags = 0; 1564 else 1565 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1566 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1567 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1568 /* 1569 * When we get the packet, there is a pseudo-header seed already 1570 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1571 * compute the pseudo-header checksum again! 1572 */ 1573 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1574 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM| 1575 TI_RCB_FLAG_NO_PHDR_CKSUM; 1576 if (sc->ethercom.ec_nvlans != 0) 1577 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1578 rcb->ti_max_len = TI_TX_RING_CNT; 1579 if (sc->ti_hwrev == TI_HWREV_TIGON) 1580 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1581 else 1582 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0); 1583 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1584 TI_CDTXCONSADDR(sc); 1585 1586 /* 1587 * We're done frobbing the General Information Block. Sync 1588 * it. Note we take care of the first stats sync here, as 1589 * well. 1590 */ 1591 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1592 1593 /* Set up tuneables */ 1594 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1595 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1596 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1597 (sc->ti_rx_coal_ticks / 10)); 1598 else 1599 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1600 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1601 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1602 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1603 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1604 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1605 1606 /* Turn interrupts on. */ 1607 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1608 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1609 1610 /* Start CPU. */ 1611 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1612 1613 return(0); 1614 } 1615 1616 /* 1617 * look for id in the device list, returning the first match 1618 */ 1619 static const struct ti_type * 1620 ti_type_match(pa) 1621 struct pci_attach_args *pa; 1622 { 1623 const struct ti_type *t; 1624 1625 t = ti_devs; 1626 while(t->ti_name != NULL) { 1627 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1628 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1629 return (t); 1630 } 1631 t++; 1632 } 1633 1634 return(NULL); 1635 } 1636 1637 /* 1638 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1639 * against our list and return its name if we find a match. 1640 */ 1641 static int ti_probe(parent, match, aux) 1642 struct device *parent; 1643 struct cfdata *match; 1644 void *aux; 1645 { 1646 struct pci_attach_args *pa = aux; 1647 const struct ti_type *t; 1648 1649 t = ti_type_match(pa); 1650 1651 return((t == NULL) ? 0 : 1); 1652 } 1653 1654 static void ti_attach(parent, self, aux) 1655 struct device *parent, *self; 1656 void *aux; 1657 { 1658 u_int32_t command; 1659 struct ifnet *ifp; 1660 struct ti_softc *sc; 1661 u_char eaddr[ETHER_ADDR_LEN]; 1662 struct pci_attach_args *pa = aux; 1663 pci_chipset_tag_t pc = pa->pa_pc; 1664 pci_intr_handle_t ih; 1665 const char *intrstr = NULL; 1666 bus_dma_segment_t dmaseg; 1667 int error, dmanseg, nolinear; 1668 const struct ti_type *t; 1669 1670 t = ti_type_match(pa); 1671 if (t == NULL) { 1672 printf("ti_attach: were did the card go ?\n"); 1673 return; 1674 } 1675 1676 printf(": %s (rev. 0x%02x)\n", t->ti_name, PCI_REVISION(pa->pa_class)); 1677 1678 sc = (struct ti_softc *)self; 1679 1680 /* 1681 * Map control/status registers. 1682 */ 1683 nolinear = 0; 1684 if (pci_mapreg_map(pa, 0x10, 1685 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1686 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1687 NULL, NULL)) { 1688 nolinear = 1; 1689 if (pci_mapreg_map(pa, 0x10, 1690 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1691 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1692 printf(": can't map memory space\n"); 1693 return; 1694 } 1695 } 1696 if (nolinear == 0) 1697 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle); 1698 else 1699 sc->ti_vhandle = NULL; 1700 1701 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1702 command |= PCI_COMMAND_MASTER_ENABLE; 1703 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1704 1705 /* Allocate interrupt */ 1706 if (pci_intr_map(pa, &ih)) { 1707 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 1708 return;; 1709 } 1710 intrstr = pci_intr_string(pc, ih); 1711 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc); 1712 if (sc->sc_ih == NULL) { 1713 printf("%s: couldn't establish interrupt", 1714 sc->sc_dev.dv_xname); 1715 if (intrstr != NULL) 1716 printf(" at %s", intrstr); 1717 printf("\n"); 1718 return;; 1719 } 1720 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 1721 /* 1722 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1723 * doing do could allow DMA to corrupt kernel memory during the 1724 * reboot before the driver initializes. 1725 */ 1726 (void) shutdownhook_establish(ti_shutdown, sc); 1727 1728 if (ti_chipinit(sc)) { 1729 printf("%s: chip initialization failed\n", self->dv_xname); 1730 goto fail2; 1731 } 1732 1733 /* 1734 * Deal with some chip diffrences. 1735 */ 1736 switch (sc->ti_hwrev) { 1737 case TI_HWREV_TIGON: 1738 sc->sc_tx_encap = ti_encap_tigon1; 1739 sc->sc_tx_eof = ti_txeof_tigon1; 1740 if (nolinear == 1) 1741 printf("%s: memory space not mapped linear\n", 1742 self->dv_xname); 1743 break; 1744 1745 case TI_HWREV_TIGON_II: 1746 sc->sc_tx_encap = ti_encap_tigon2; 1747 sc->sc_tx_eof = ti_txeof_tigon2; 1748 break; 1749 1750 default: 1751 printf("%s: Unknown chip version: %d\n", self->dv_xname, 1752 sc->ti_hwrev); 1753 goto fail2; 1754 } 1755 1756 /* Zero out the NIC's on-board SRAM. */ 1757 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1758 1759 /* Init again -- zeroing memory may have clobbered some registers. */ 1760 if (ti_chipinit(sc)) { 1761 printf("%s: chip initialization failed\n", self->dv_xname); 1762 goto fail2; 1763 } 1764 1765 /* 1766 * Get station address from the EEPROM. Note: the manual states 1767 * that the MAC address is at offset 0x8c, however the data is 1768 * stored as two longwords (since that's how it's loaded into 1769 * the NIC). This means the MAC address is actually preceded 1770 * by two zero bytes. We need to skip over those. 1771 */ 1772 if (ti_read_eeprom(sc, (caddr_t)&eaddr, 1773 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1774 printf("%s: failed to read station address\n", self->dv_xname); 1775 goto fail2; 1776 } 1777 1778 /* 1779 * A Tigon chip was detected. Inform the world. 1780 */ 1781 printf("%s: Ethernet address: %s\n", self->dv_xname, 1782 ether_sprintf(eaddr)); 1783 1784 sc->sc_dmat = pa->pa_dmat; 1785 1786 /* Allocate the general information block and ring buffers. */ 1787 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1788 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1789 BUS_DMA_NOWAIT)) != 0) { 1790 printf("%s: can't allocate ring buffer, error = %d\n", 1791 sc->sc_dev.dv_xname, error); 1792 goto fail2; 1793 } 1794 1795 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1796 sizeof(struct ti_ring_data), (caddr_t *)&sc->ti_rdata, 1797 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1798 printf("%s: can't map ring buffer, error = %d\n", 1799 sc->sc_dev.dv_xname, error); 1800 goto fail2; 1801 } 1802 1803 if ((error = bus_dmamap_create(sc->sc_dmat, 1804 sizeof(struct ti_ring_data), 1, 1805 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1806 &sc->info_dmamap)) != 0) { 1807 printf("%s: can't create ring buffer DMA map, error = %d\n", 1808 sc->sc_dev.dv_xname, error); 1809 goto fail2; 1810 } 1811 1812 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1813 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1814 BUS_DMA_NOWAIT)) != 0) { 1815 printf("%s: can't load ring buffer DMA map, error = %d\n", 1816 sc->sc_dev.dv_xname, error); 1817 goto fail2; 1818 } 1819 1820 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1821 1822 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1823 1824 /* Try to allocate memory for jumbo buffers. */ 1825 if (ti_alloc_jumbo_mem(sc)) { 1826 printf("%s: jumbo buffer allocation failed\n", self->dv_xname); 1827 goto fail2; 1828 } 1829 1830 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1831 1832 /* 1833 * We really need a better way to tell a 1000baseT card 1834 * from a 1000baseSX one, since in theory there could be 1835 * OEMed 1000baseT cards from lame vendors who aren't 1836 * clever enough to change the PCI ID. For the moment 1837 * though, the AceNIC is the only copper card available. 1838 */ 1839 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1840 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1841 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1842 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1843 sc->ti_copper = 1; 1844 else 1845 sc->ti_copper = 0; 1846 1847 /* Set default tuneable values. */ 1848 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1849 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1850 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1851 sc->ti_rx_max_coal_bds = 64; 1852 sc->ti_tx_max_coal_bds = 128; 1853 sc->ti_tx_buf_ratio = 21; 1854 1855 /* Set up ifnet structure */ 1856 ifp = &sc->ethercom.ec_if; 1857 ifp->if_softc = sc; 1858 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1859 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1860 ifp->if_ioctl = ti_ioctl; 1861 ifp->if_start = ti_start; 1862 ifp->if_watchdog = ti_watchdog; 1863 IFQ_SET_READY(&ifp->if_snd); 1864 1865 #if 0 1866 /* 1867 * XXX This is not really correct -- we don't necessarily 1868 * XXX want to queue up as many as we can transmit at the 1869 * XXX upper layer like that. Someone with a board should 1870 * XXX check to see how this affects performance. 1871 */ 1872 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1873 #endif 1874 1875 /* 1876 * We can support 802.1Q VLAN-sized frames. 1877 */ 1878 sc->ethercom.ec_capabilities |= 1879 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1880 1881 /* 1882 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1883 */ 1884 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1885 IFCAP_CSUM_UDPv4; 1886 1887 /* Set up ifmedia support. */ 1888 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1889 if (sc->ti_copper) { 1890 /* 1891 * Copper cards allow manual 10/100 mode selection, 1892 * but not manual 1000baseT mode selection. Why? 1893 * Becuase currently there's no way to specify the 1894 * master/slave setting through the firmware interface, 1895 * so Alteon decided to just bag it and handle it 1896 * via autonegotiation. 1897 */ 1898 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1899 ifmedia_add(&sc->ifmedia, 1900 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1901 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1902 ifmedia_add(&sc->ifmedia, 1903 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1904 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 1905 ifmedia_add(&sc->ifmedia, 1906 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 1907 } else { 1908 /* Fiber cards don't support 10/100 modes. */ 1909 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1910 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1911 } 1912 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1913 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1914 1915 /* 1916 * Call MI attach routines. 1917 */ 1918 if_attach(ifp); 1919 ether_ifattach(ifp, eaddr); 1920 1921 return; 1922 fail2: 1923 pci_intr_disestablish(pc, sc->sc_ih); 1924 return; 1925 } 1926 1927 /* 1928 * Frame reception handling. This is called if there's a frame 1929 * on the receive return list. 1930 * 1931 * Note: we have to be able to handle three possibilities here: 1932 * 1) the frame is from the mini receive ring (can only happen) 1933 * on Tigon 2 boards) 1934 * 2) the frame is from the jumbo receive ring 1935 * 3) the frame is from the standard receive ring 1936 */ 1937 1938 static void ti_rxeof(sc) 1939 struct ti_softc *sc; 1940 { 1941 struct ifnet *ifp; 1942 struct ti_cmd_desc cmd; 1943 1944 ifp = &sc->ethercom.ec_if; 1945 1946 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1947 struct ti_rx_desc *cur_rx; 1948 u_int32_t rxidx; 1949 struct mbuf *m = NULL; 1950 u_int16_t vlan_tag = 0; 1951 int have_tag = 0; 1952 struct ether_header *eh; 1953 bus_dmamap_t dmamap; 1954 1955 cur_rx = 1956 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1957 rxidx = cur_rx->ti_idx; 1958 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1959 1960 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1961 have_tag = 1; 1962 vlan_tag = cur_rx->ti_vlan_tag; 1963 } 1964 1965 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1966 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1967 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1968 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1969 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1970 ifp->if_ierrors++; 1971 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1972 continue; 1973 } 1974 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1975 == ENOBUFS) { 1976 ifp->if_ierrors++; 1977 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1978 continue; 1979 } 1980 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1981 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1982 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1983 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1984 dmamap = sc->mini_dmamap[rxidx]; 1985 sc->mini_dmamap[rxidx] = 0; 1986 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1987 ifp->if_ierrors++; 1988 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1989 continue; 1990 } 1991 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1992 == ENOBUFS) { 1993 ifp->if_ierrors++; 1994 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1995 continue; 1996 } 1997 } else { 1998 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1999 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2000 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2001 dmamap = sc->std_dmamap[rxidx]; 2002 sc->std_dmamap[rxidx] = 0; 2003 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2004 ifp->if_ierrors++; 2005 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2006 continue; 2007 } 2008 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 2009 == ENOBUFS) { 2010 ifp->if_ierrors++; 2011 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2012 continue; 2013 } 2014 } 2015 2016 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 2017 ifp->if_ipackets++; 2018 m->m_pkthdr.rcvif = ifp; 2019 2020 #if NBPFILTER > 0 2021 /* 2022 * Handle BPF listeners. Let the BPF user see the packet, but 2023 * don't pass it up to the ether_input() layer unless it's 2024 * a broadcast packet, multicast packet, matches our ethernet 2025 * address or the interface is in promiscuous mode. 2026 */ 2027 if (ifp->if_bpf) 2028 bpf_mtap(ifp->if_bpf, m); 2029 #endif 2030 2031 eh = mtod(m, struct ether_header *); 2032 switch (ntohs(eh->ether_type)) { 2033 #ifdef INET 2034 case ETHERTYPE_IP: 2035 { 2036 struct ip *ip = (struct ip *) (eh + 1); 2037 2038 /* 2039 * Note the Tigon firmware does not invert 2040 * the checksum for us, hence the XOR. 2041 */ 2042 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2043 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 2044 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2045 /* 2046 * ntohs() the constant so the compiler can 2047 * optimize... 2048 * 2049 * XXX Figure out a sane way to deal with 2050 * fragmented packets. 2051 */ 2052 if ((ip->ip_off & htons(IP_MF|IP_OFFMASK)) == 0) { 2053 switch (ip->ip_p) { 2054 case IPPROTO_TCP: 2055 m->m_pkthdr.csum_data = 2056 cur_rx->ti_tcp_udp_cksum; 2057 m->m_pkthdr.csum_flags |= 2058 M_CSUM_TCPv4|M_CSUM_DATA; 2059 break; 2060 case IPPROTO_UDP: 2061 m->m_pkthdr.csum_data = 2062 cur_rx->ti_tcp_udp_cksum; 2063 m->m_pkthdr.csum_flags |= 2064 M_CSUM_UDPv4|M_CSUM_DATA; 2065 break; 2066 default: 2067 /* Nothing */; 2068 } 2069 } 2070 break; 2071 } 2072 #endif 2073 default: 2074 /* Nothing. */ 2075 break; 2076 } 2077 2078 if (have_tag) { 2079 struct mbuf *n; 2080 n = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 2081 if (n) { 2082 *mtod(n, int *) = vlan_tag; 2083 n->m_len = sizeof(int); 2084 } else { 2085 printf("%s: no mbuf for tag\n", ifp->if_xname); 2086 m_freem(m); 2087 continue; 2088 } 2089 have_tag = vlan_tag = 0; 2090 } 2091 (*ifp->if_input)(ifp, m); 2092 } 2093 2094 /* Only necessary on the Tigon 1. */ 2095 if (sc->ti_hwrev == TI_HWREV_TIGON) 2096 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2097 sc->ti_rx_saved_considx); 2098 2099 TI_UPDATE_STDPROD(sc, sc->ti_std); 2100 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2101 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2102 2103 return; 2104 } 2105 2106 static void ti_txeof_tigon1(sc) 2107 struct ti_softc *sc; 2108 { 2109 struct ti_tx_desc *cur_tx = NULL; 2110 struct ifnet *ifp; 2111 struct txdmamap_pool_entry *dma; 2112 2113 ifp = &sc->ethercom.ec_if; 2114 2115 /* 2116 * Go through our tx ring and free mbufs for those 2117 * frames that have been sent. 2118 */ 2119 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2120 u_int32_t idx = 0; 2121 2122 idx = sc->ti_tx_saved_considx; 2123 if (idx > 383) 2124 CSR_WRITE_4(sc, TI_WINBASE, 2125 TI_TX_RING_BASE + 6144); 2126 else if (idx > 255) 2127 CSR_WRITE_4(sc, TI_WINBASE, 2128 TI_TX_RING_BASE + 4096); 2129 else if (idx > 127) 2130 CSR_WRITE_4(sc, TI_WINBASE, 2131 TI_TX_RING_BASE + 2048); 2132 else 2133 CSR_WRITE_4(sc, TI_WINBASE, 2134 TI_TX_RING_BASE); 2135 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2136 if (cur_tx->ti_flags & TI_BDFLAG_END) 2137 ifp->if_opackets++; 2138 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2139 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2140 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2141 2142 dma = sc->txdma[idx]; 2143 KDASSERT(dma != NULL); 2144 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2145 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2146 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2147 2148 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2149 sc->txdma[idx] = NULL; 2150 } 2151 sc->ti_txcnt--; 2152 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2153 ifp->if_timer = 0; 2154 } 2155 2156 if (cur_tx != NULL) 2157 ifp->if_flags &= ~IFF_OACTIVE; 2158 2159 return; 2160 } 2161 2162 static void ti_txeof_tigon2(sc) 2163 struct ti_softc *sc; 2164 { 2165 struct ti_tx_desc *cur_tx = NULL; 2166 struct ifnet *ifp; 2167 struct txdmamap_pool_entry *dma; 2168 int firstidx, cnt; 2169 2170 ifp = &sc->ethercom.ec_if; 2171 2172 /* 2173 * Go through our tx ring and free mbufs for those 2174 * frames that have been sent. 2175 */ 2176 firstidx = sc->ti_tx_saved_considx; 2177 cnt = 0; 2178 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2179 u_int32_t idx = 0; 2180 2181 idx = sc->ti_tx_saved_considx; 2182 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2183 if (cur_tx->ti_flags & TI_BDFLAG_END) 2184 ifp->if_opackets++; 2185 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2186 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2187 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2188 2189 dma = sc->txdma[idx]; 2190 KDASSERT(dma != NULL); 2191 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2192 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2193 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2194 2195 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2196 sc->txdma[idx] = NULL; 2197 } 2198 cnt++; 2199 sc->ti_txcnt--; 2200 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2201 ifp->if_timer = 0; 2202 } 2203 2204 if (cnt != 0) 2205 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2206 2207 if (cur_tx != NULL) 2208 ifp->if_flags &= ~IFF_OACTIVE; 2209 2210 return; 2211 } 2212 2213 static int ti_intr(xsc) 2214 void *xsc; 2215 { 2216 struct ti_softc *sc; 2217 struct ifnet *ifp; 2218 2219 sc = xsc; 2220 ifp = &sc->ethercom.ec_if; 2221 2222 #ifdef notdef 2223 /* Avoid this for now -- checking this register is expensive. */ 2224 /* Make sure this is really our interrupt. */ 2225 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2226 return (0); 2227 #endif 2228 2229 /* Ack interrupt and stop others from occuring. */ 2230 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2231 2232 if (ifp->if_flags & IFF_RUNNING) { 2233 /* Check RX return ring producer/consumer */ 2234 ti_rxeof(sc); 2235 2236 /* Check TX ring producer/consumer */ 2237 (*sc->sc_tx_eof)(sc); 2238 } 2239 2240 ti_handle_events(sc); 2241 2242 /* Re-enable interrupts. */ 2243 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2244 2245 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2246 IFQ_IS_EMPTY(&ifp->if_snd) == 0) 2247 ti_start(ifp); 2248 2249 return (1); 2250 } 2251 2252 static void ti_stats_update(sc) 2253 struct ti_softc *sc; 2254 { 2255 struct ifnet *ifp; 2256 2257 ifp = &sc->ethercom.ec_if; 2258 2259 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2260 2261 ifp->if_collisions += 2262 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2263 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2264 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2265 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2266 ifp->if_collisions; 2267 2268 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2269 } 2270 2271 /* 2272 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2273 * pointers to descriptors. 2274 */ 2275 static int ti_encap_tigon1(sc, m_head, txidx) 2276 struct ti_softc *sc; 2277 struct mbuf *m_head; 2278 u_int32_t *txidx; 2279 { 2280 struct ti_tx_desc *f = NULL; 2281 u_int32_t frag, cur, cnt = 0; 2282 struct txdmamap_pool_entry *dma; 2283 bus_dmamap_t dmamap; 2284 int error, i; 2285 struct mbuf *n; 2286 u_int16_t csum_flags = 0; 2287 2288 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2289 if (dma == NULL) { 2290 return ENOMEM; 2291 } 2292 dmamap = dma->dmamap; 2293 2294 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2295 BUS_DMA_WRITE); 2296 if (error) { 2297 struct mbuf *m; 2298 int i = 0; 2299 for (m = m_head; m; m = m->m_next) 2300 i++; 2301 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2302 "error %d\n", m_head->m_pkthdr.len, i, error); 2303 return (ENOMEM); 2304 } 2305 2306 cur = frag = *txidx; 2307 2308 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2309 /* IP header checksum field must be 0! */ 2310 csum_flags |= TI_BDFLAG_IP_CKSUM; 2311 } 2312 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2313 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2314 2315 /* XXX fragmented packet checksum capability? */ 2316 2317 /* 2318 * Start packing the mbufs in this chain into 2319 * the fragment pointers. Stop when we run out 2320 * of fragments or hit the end of the mbuf chain. 2321 */ 2322 for (i = 0; i < dmamap->dm_nsegs; i++) { 2323 if (frag > 383) 2324 CSR_WRITE_4(sc, TI_WINBASE, 2325 TI_TX_RING_BASE + 6144); 2326 else if (frag > 255) 2327 CSR_WRITE_4(sc, TI_WINBASE, 2328 TI_TX_RING_BASE + 4096); 2329 else if (frag > 127) 2330 CSR_WRITE_4(sc, TI_WINBASE, 2331 TI_TX_RING_BASE + 2048); 2332 else 2333 CSR_WRITE_4(sc, TI_WINBASE, 2334 TI_TX_RING_BASE); 2335 f = &sc->ti_tx_ring_nic[frag % 128]; 2336 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2337 break; 2338 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2339 f->ti_len = dmamap->dm_segs[i].ds_len; 2340 f->ti_flags = csum_flags; 2341 n = m_aux_find(m_head, AF_LINK, ETHERTYPE_VLAN); 2342 if (n) { 2343 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2344 f->ti_vlan_tag = *mtod(n, int *); 2345 } else { 2346 f->ti_vlan_tag = 0; 2347 } 2348 /* 2349 * Sanity check: avoid coming within 16 descriptors 2350 * of the end of the ring. 2351 */ 2352 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2353 return(ENOBUFS); 2354 cur = frag; 2355 TI_INC(frag, TI_TX_RING_CNT); 2356 cnt++; 2357 } 2358 2359 if (i < dmamap->dm_nsegs) 2360 return(ENOBUFS); 2361 2362 if (frag == sc->ti_tx_saved_considx) 2363 return(ENOBUFS); 2364 2365 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2366 TI_BDFLAG_END; 2367 2368 /* Sync the packet's DMA map. */ 2369 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2370 BUS_DMASYNC_PREWRITE); 2371 2372 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2373 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, dma, link); 2374 sc->txdma[cur] = dma; 2375 sc->ti_txcnt += cnt; 2376 2377 *txidx = frag; 2378 2379 return(0); 2380 } 2381 2382 static int ti_encap_tigon2(sc, m_head, txidx) 2383 struct ti_softc *sc; 2384 struct mbuf *m_head; 2385 u_int32_t *txidx; 2386 { 2387 struct ti_tx_desc *f = NULL; 2388 u_int32_t frag, firstfrag, cur, cnt = 0; 2389 struct txdmamap_pool_entry *dma; 2390 bus_dmamap_t dmamap; 2391 int error, i; 2392 struct mbuf *n; 2393 u_int16_t csum_flags = 0; 2394 2395 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2396 if (dma == NULL) { 2397 return ENOMEM; 2398 } 2399 dmamap = dma->dmamap; 2400 2401 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2402 BUS_DMA_WRITE); 2403 if (error) { 2404 struct mbuf *m; 2405 int i = 0; 2406 for (m = m_head; m; m = m->m_next) 2407 i++; 2408 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2409 "error %d\n", m_head->m_pkthdr.len, i, error); 2410 return (ENOMEM); 2411 } 2412 2413 cur = firstfrag = frag = *txidx; 2414 2415 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2416 /* IP header checksum field must be 0! */ 2417 csum_flags |= TI_BDFLAG_IP_CKSUM; 2418 } 2419 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2420 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2421 2422 /* XXX fragmented packet checksum capability? */ 2423 2424 /* 2425 * Start packing the mbufs in this chain into 2426 * the fragment pointers. Stop when we run out 2427 * of fragments or hit the end of the mbuf chain. 2428 */ 2429 for (i = 0; i < dmamap->dm_nsegs; i++) { 2430 f = &sc->ti_rdata->ti_tx_ring[frag]; 2431 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2432 break; 2433 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2434 f->ti_len = dmamap->dm_segs[i].ds_len; 2435 f->ti_flags = csum_flags; 2436 n = m_aux_find(m_head, AF_LINK, ETHERTYPE_VLAN); 2437 if (n) { 2438 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2439 f->ti_vlan_tag = *mtod(n, int *); 2440 } else { 2441 f->ti_vlan_tag = 0; 2442 } 2443 /* 2444 * Sanity check: avoid coming within 16 descriptors 2445 * of the end of the ring. 2446 */ 2447 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2448 return(ENOBUFS); 2449 cur = frag; 2450 TI_INC(frag, TI_TX_RING_CNT); 2451 cnt++; 2452 } 2453 2454 if (i < dmamap->dm_nsegs) 2455 return(ENOBUFS); 2456 2457 if (frag == sc->ti_tx_saved_considx) 2458 return(ENOBUFS); 2459 2460 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2461 2462 /* Sync the packet's DMA map. */ 2463 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2464 BUS_DMASYNC_PREWRITE); 2465 2466 /* Sync the descriptors we are using. */ 2467 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2468 2469 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2470 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, dma, link); 2471 sc->txdma[cur] = dma; 2472 sc->ti_txcnt += cnt; 2473 2474 *txidx = frag; 2475 2476 return(0); 2477 } 2478 2479 /* 2480 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2481 * to the mbuf data regions directly in the transmit descriptors. 2482 */ 2483 static void ti_start(ifp) 2484 struct ifnet *ifp; 2485 { 2486 struct ti_softc *sc; 2487 struct mbuf *m_head = NULL; 2488 u_int32_t prodidx = 0; 2489 2490 sc = ifp->if_softc; 2491 2492 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2493 2494 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2495 IFQ_POLL(&ifp->if_snd, m_head); 2496 if (m_head == NULL) 2497 break; 2498 2499 /* 2500 * Pack the data into the transmit ring. If we 2501 * don't have room, set the OACTIVE flag and wait 2502 * for the NIC to drain the ring. 2503 */ 2504 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2505 ifp->if_flags |= IFF_OACTIVE; 2506 break; 2507 } 2508 2509 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2510 2511 /* 2512 * If there's a BPF listener, bounce a copy of this frame 2513 * to him. 2514 */ 2515 #if NBPFILTER > 0 2516 if (ifp->if_bpf) 2517 bpf_mtap(ifp->if_bpf, m_head); 2518 #endif 2519 } 2520 2521 /* Transmit */ 2522 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2523 2524 /* 2525 * Set a timeout in case the chip goes out to lunch. 2526 */ 2527 ifp->if_timer = 5; 2528 2529 return; 2530 } 2531 2532 static void ti_init(xsc) 2533 void *xsc; 2534 { 2535 struct ti_softc *sc = xsc; 2536 int s; 2537 2538 s = splnet(); 2539 2540 /* Cancel pending I/O and flush buffers. */ 2541 ti_stop(sc); 2542 2543 /* Init the gen info block, ring control blocks and firmware. */ 2544 if (ti_gibinit(sc)) { 2545 printf("%s: initialization failure\n", sc->sc_dev.dv_xname); 2546 splx(s); 2547 return; 2548 } 2549 2550 splx(s); 2551 2552 return; 2553 } 2554 2555 static void ti_init2(sc) 2556 struct ti_softc *sc; 2557 { 2558 struct ti_cmd_desc cmd; 2559 struct ifnet *ifp; 2560 u_int8_t *m; 2561 struct ifmedia *ifm; 2562 int tmp; 2563 2564 ifp = &sc->ethercom.ec_if; 2565 2566 /* Specify MTU and interface index. */ 2567 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->sc_dev.dv_unit); /* ??? */ 2568 2569 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2570 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2571 tmp += ETHER_VLAN_ENCAP_LEN; 2572 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2573 2574 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2575 2576 /* Load our MAC address. */ 2577 m = (u_int8_t *)LLADDR(ifp->if_sadl); 2578 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2579 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2580 | (m[4] << 8) | m[5]); 2581 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2582 2583 /* Enable or disable promiscuous mode as needed. */ 2584 if (ifp->if_flags & IFF_PROMISC) { 2585 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2586 } else { 2587 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2588 } 2589 2590 /* Program multicast filter. */ 2591 ti_setmulti(sc); 2592 2593 /* 2594 * If this is a Tigon 1, we should tell the 2595 * firmware to use software packet filtering. 2596 */ 2597 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2598 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2599 } 2600 2601 /* Init RX ring. */ 2602 ti_init_rx_ring_std(sc); 2603 2604 /* Init jumbo RX ring. */ 2605 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2606 ti_init_rx_ring_jumbo(sc); 2607 2608 /* 2609 * If this is a Tigon 2, we can also configure the 2610 * mini ring. 2611 */ 2612 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2613 ti_init_rx_ring_mini(sc); 2614 2615 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2616 sc->ti_rx_saved_considx = 0; 2617 2618 /* Init TX ring. */ 2619 ti_init_tx_ring(sc); 2620 2621 /* Tell firmware we're alive. */ 2622 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2623 2624 /* Enable host interrupts. */ 2625 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2626 2627 ifp->if_flags |= IFF_RUNNING; 2628 ifp->if_flags &= ~IFF_OACTIVE; 2629 2630 /* 2631 * Make sure to set media properly. We have to do this 2632 * here since we have to issue commands in order to set 2633 * the link negotiation and we can't issue commands until 2634 * the firmware is running. 2635 */ 2636 ifm = &sc->ifmedia; 2637 tmp = ifm->ifm_media; 2638 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2639 ti_ifmedia_upd(ifp); 2640 ifm->ifm_media = tmp; 2641 2642 return; 2643 } 2644 2645 /* 2646 * Set media options. 2647 */ 2648 static int ti_ifmedia_upd(ifp) 2649 struct ifnet *ifp; 2650 { 2651 struct ti_softc *sc; 2652 struct ifmedia *ifm; 2653 struct ti_cmd_desc cmd; 2654 2655 sc = ifp->if_softc; 2656 ifm = &sc->ifmedia; 2657 2658 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2659 return(EINVAL); 2660 2661 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2662 case IFM_AUTO: 2663 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2664 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2665 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2666 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2667 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2668 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2669 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2670 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2671 break; 2672 case IFM_1000_SX: 2673 case IFM_1000_T: 2674 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2675 CSR_WRITE_4(sc, TI_GCR_GLINK, 2676 TI_GLNK_PREF|TI_GLNK_1000MB|TI_GLNK_FULL_DUPLEX| 2677 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2678 } else { 2679 CSR_WRITE_4(sc, TI_GCR_GLINK, 2680 TI_GLNK_PREF|TI_GLNK_1000MB| 2681 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2682 } 2683 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2684 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2685 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2686 break; 2687 case IFM_100_FX: 2688 case IFM_10_FL: 2689 case IFM_100_TX: 2690 case IFM_10_T: 2691 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2692 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2693 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2694 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2695 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2696 } else { 2697 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2698 } 2699 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2700 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2701 } else { 2702 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2703 } 2704 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2705 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2706 break; 2707 } 2708 2709 sc->ethercom.ec_if.if_baudrate = 2710 ifmedia_baudrate(ifm->ifm_media); 2711 2712 return(0); 2713 } 2714 2715 /* 2716 * Report current media status. 2717 */ 2718 static void ti_ifmedia_sts(ifp, ifmr) 2719 struct ifnet *ifp; 2720 struct ifmediareq *ifmr; 2721 { 2722 struct ti_softc *sc; 2723 u_int32_t media = 0; 2724 2725 sc = ifp->if_softc; 2726 2727 ifmr->ifm_status = IFM_AVALID; 2728 ifmr->ifm_active = IFM_ETHER; 2729 2730 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2731 return; 2732 2733 ifmr->ifm_status |= IFM_ACTIVE; 2734 2735 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2736 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2737 if (sc->ti_copper) 2738 ifmr->ifm_active |= IFM_1000_T; 2739 else 2740 ifmr->ifm_active |= IFM_1000_SX; 2741 if (media & TI_GLNK_FULL_DUPLEX) 2742 ifmr->ifm_active |= IFM_FDX; 2743 else 2744 ifmr->ifm_active |= IFM_HDX; 2745 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2746 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2747 if (sc->ti_copper) { 2748 if (media & TI_LNK_100MB) 2749 ifmr->ifm_active |= IFM_100_TX; 2750 if (media & TI_LNK_10MB) 2751 ifmr->ifm_active |= IFM_10_T; 2752 } else { 2753 if (media & TI_LNK_100MB) 2754 ifmr->ifm_active |= IFM_100_FX; 2755 if (media & TI_LNK_10MB) 2756 ifmr->ifm_active |= IFM_10_FL; 2757 } 2758 if (media & TI_LNK_FULL_DUPLEX) 2759 ifmr->ifm_active |= IFM_FDX; 2760 if (media & TI_LNK_HALF_DUPLEX) 2761 ifmr->ifm_active |= IFM_HDX; 2762 } 2763 2764 sc->ethercom.ec_if.if_baudrate = 2765 ifmedia_baudrate(sc->ifmedia.ifm_media); 2766 2767 return; 2768 } 2769 2770 static int 2771 ti_ether_ioctl(ifp, cmd, data) 2772 struct ifnet *ifp; 2773 u_long cmd; 2774 caddr_t data; 2775 { 2776 struct ifaddr *ifa = (struct ifaddr *) data; 2777 struct ti_softc *sc = ifp->if_softc; 2778 2779 if ((ifp->if_flags & IFF_UP) == 0) { 2780 ifp->if_flags |= IFF_UP; 2781 ti_init(sc); 2782 } 2783 2784 switch (cmd) { 2785 case SIOCSIFADDR: 2786 2787 switch (ifa->ifa_addr->sa_family) { 2788 #ifdef INET 2789 case AF_INET: 2790 arp_ifinit(ifp, ifa); 2791 break; 2792 #endif 2793 #ifdef NS 2794 case AF_NS: 2795 { 2796 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 2797 2798 if (ns_nullhost(*ina)) 2799 ina->x_host = *(union ns_host *) 2800 LLADDR(ifp->if_sadl); 2801 else 2802 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 2803 ifp->if_addrlen); 2804 break; 2805 } 2806 #endif 2807 default: 2808 break; 2809 } 2810 break; 2811 2812 default: 2813 return (EINVAL); 2814 } 2815 2816 return (0); 2817 } 2818 2819 static int ti_ioctl(ifp, command, data) 2820 struct ifnet *ifp; 2821 u_long command; 2822 caddr_t data; 2823 { 2824 struct ti_softc *sc = ifp->if_softc; 2825 struct ifreq *ifr = (struct ifreq *) data; 2826 int s, error = 0; 2827 struct ti_cmd_desc cmd; 2828 2829 s = splnet(); 2830 2831 switch(command) { 2832 case SIOCSIFADDR: 2833 case SIOCGIFADDR: 2834 error = ti_ether_ioctl(ifp, command, data); 2835 break; 2836 case SIOCSIFMTU: 2837 if (ifr->ifr_mtu > ETHERMTU_JUMBO) 2838 error = EINVAL; 2839 else { 2840 ifp->if_mtu = ifr->ifr_mtu; 2841 ti_init(sc); 2842 } 2843 break; 2844 case SIOCSIFFLAGS: 2845 if (ifp->if_flags & IFF_UP) { 2846 /* 2847 * If only the state of the PROMISC flag changed, 2848 * then just use the 'set promisc mode' command 2849 * instead of reinitializing the entire NIC. Doing 2850 * a full re-init means reloading the firmware and 2851 * waiting for it to start up, which may take a 2852 * second or two. 2853 */ 2854 if (ifp->if_flags & IFF_RUNNING && 2855 ifp->if_flags & IFF_PROMISC && 2856 !(sc->ti_if_flags & IFF_PROMISC)) { 2857 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2858 TI_CMD_CODE_PROMISC_ENB, 0); 2859 } else if (ifp->if_flags & IFF_RUNNING && 2860 !(ifp->if_flags & IFF_PROMISC) && 2861 sc->ti_if_flags & IFF_PROMISC) { 2862 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2863 TI_CMD_CODE_PROMISC_DIS, 0); 2864 } else 2865 ti_init(sc); 2866 } else { 2867 if (ifp->if_flags & IFF_RUNNING) { 2868 ti_stop(sc); 2869 } 2870 } 2871 sc->ti_if_flags = ifp->if_flags; 2872 error = 0; 2873 break; 2874 case SIOCADDMULTI: 2875 case SIOCDELMULTI: 2876 error = (command == SIOCADDMULTI) ? 2877 ether_addmulti(ifr, &sc->ethercom) : 2878 ether_delmulti(ifr, &sc->ethercom); 2879 if (error == ENETRESET) { 2880 if (ifp->if_flags & IFF_RUNNING) 2881 ti_setmulti(sc); 2882 error = 0; 2883 } 2884 break; 2885 case SIOCSIFMEDIA: 2886 case SIOCGIFMEDIA: 2887 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2888 break; 2889 default: 2890 error = EINVAL; 2891 break; 2892 } 2893 2894 (void)splx(s); 2895 2896 return(error); 2897 } 2898 2899 static void ti_watchdog(ifp) 2900 struct ifnet *ifp; 2901 { 2902 struct ti_softc *sc; 2903 2904 sc = ifp->if_softc; 2905 2906 printf("%s: watchdog timeout -- resetting\n", sc->sc_dev.dv_xname); 2907 ti_stop(sc); 2908 ti_init(sc); 2909 2910 ifp->if_oerrors++; 2911 2912 return; 2913 } 2914 2915 /* 2916 * Stop the adapter and free any mbufs allocated to the 2917 * RX and TX lists. 2918 */ 2919 static void ti_stop(sc) 2920 struct ti_softc *sc; 2921 { 2922 struct ifnet *ifp; 2923 struct ti_cmd_desc cmd; 2924 2925 ifp = &sc->ethercom.ec_if; 2926 2927 /* Disable host interrupts. */ 2928 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2929 /* 2930 * Tell firmware we're shutting down. 2931 */ 2932 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2933 2934 /* Halt and reinitialize. */ 2935 ti_chipinit(sc); 2936 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2937 ti_chipinit(sc); 2938 2939 /* Free the RX lists. */ 2940 ti_free_rx_ring_std(sc); 2941 2942 /* Free jumbo RX list. */ 2943 ti_free_rx_ring_jumbo(sc); 2944 2945 /* Free mini RX list. */ 2946 ti_free_rx_ring_mini(sc); 2947 2948 /* Free TX buffers. */ 2949 ti_free_tx_ring(sc); 2950 2951 sc->ti_ev_prodidx.ti_idx = 0; 2952 sc->ti_return_prodidx.ti_idx = 0; 2953 sc->ti_tx_considx.ti_idx = 0; 2954 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2955 2956 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2957 2958 return; 2959 } 2960 2961 /* 2962 * Stop all chip I/O so that the kernel's probe routines don't 2963 * get confused by errant DMAs when rebooting. 2964 */ 2965 static void ti_shutdown(v) 2966 void *v; 2967 { 2968 struct ti_softc *sc = v; 2969 2970 ti_chipinit(sc); 2971 2972 return; 2973 } 2974