1 /* $NetBSD: if_vr.c,v 1.53 2001/11/13 07:48:45 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1997, 1998 42 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Bill Paul. 55 * 4. Neither the name of the author nor the names of any co-contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 69 * THE POSSIBILITY OF SUCH DAMAGE. 70 * 71 * $FreeBSD: if_vr.c,v 1.7 1999/01/10 18:51:49 wpaul Exp $ 72 */ 73 74 /* 75 * VIA Rhine fast ethernet PCI NIC driver 76 * 77 * Supports various network adapters based on the VIA Rhine 78 * and Rhine II PCI controllers, including the D-Link DFE530TX. 79 * Datasheets are available at http://www.via.com.tw. 80 * 81 * Written by Bill Paul <wpaul@ctr.columbia.edu> 82 * Electrical Engineering Department 83 * Columbia University, New York City 84 */ 85 86 /* 87 * The VIA Rhine controllers are similar in some respects to the 88 * the DEC tulip chips, except less complicated. The controller 89 * uses an MII bus and an external physical layer interface. The 90 * receiver has a one entry perfect filter and a 64-bit hash table 91 * multicast filter. Transmit and receive descriptors are similar 92 * to the tulip. 93 * 94 * The Rhine has a serious flaw in its transmit DMA mechanism: 95 * transmit buffers must be longword aligned. Unfortunately, 96 * the kernel doesn't guarantee that mbufs will be filled in starting 97 * at longword boundaries, so we have to do a buffer copy before 98 * transmission. 99 * 100 * Apparently, the receive DMA mechanism also has the same flaw. This 101 * means that on systems with struct alignment requirements, incoming 102 * frames must be copied to a new buffer which shifts the data forward 103 * 2 bytes so that the payload is aligned on a 4-byte boundary. 104 */ 105 106 #include <sys/cdefs.h> 107 __KERNEL_RCSID(0, "$NetBSD: if_vr.c,v 1.53 2001/11/13 07:48:45 lukem Exp $"); 108 109 #include <sys/param.h> 110 #include <sys/systm.h> 111 #include <sys/callout.h> 112 #include <sys/sockio.h> 113 #include <sys/mbuf.h> 114 #include <sys/malloc.h> 115 #include <sys/kernel.h> 116 #include <sys/socket.h> 117 #include <sys/device.h> 118 119 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 120 121 #include <net/if.h> 122 #include <net/if_arp.h> 123 #include <net/if_dl.h> 124 #include <net/if_media.h> 125 #include <net/if_ether.h> 126 127 #include "bpfilter.h" 128 #if NBPFILTER > 0 129 #include <net/bpf.h> 130 #endif 131 132 #include <machine/bus.h> 133 #include <machine/intr.h> 134 #include <machine/endian.h> 135 136 #include <dev/mii/mii.h> 137 #include <dev/mii/miivar.h> 138 #include <dev/mii/mii_bitbang.h> 139 140 #include <dev/pci/pcireg.h> 141 #include <dev/pci/pcivar.h> 142 #include <dev/pci/pcidevs.h> 143 144 #include <dev/pci/if_vrreg.h> 145 146 #define VR_USEIOSPACE 147 148 /* 149 * Various supported device vendors/types and their names. 150 */ 151 static struct vr_type { 152 pci_vendor_id_t vr_vid; 153 pci_product_id_t vr_did; 154 const char *vr_name; 155 } vr_devs[] = { 156 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT3043, 157 "VIA VT3043 (Rhine) 10/100" }, 158 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6102, 159 "VIA VT6102 (Rhine II) 10/100" }, 160 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT86C100A, 161 "VIA VT86C100A (Rhine-II) 10/100" }, 162 { 0, 0, NULL } 163 }; 164 165 /* 166 * Transmit descriptor list size. 167 */ 168 #define VR_NTXDESC 64 169 #define VR_NTXDESC_MASK (VR_NTXDESC - 1) 170 #define VR_NEXTTX(x) (((x) + 1) & VR_NTXDESC_MASK) 171 172 /* 173 * Receive descriptor list size. 174 */ 175 #define VR_NRXDESC 64 176 #define VR_NRXDESC_MASK (VR_NRXDESC - 1) 177 #define VR_NEXTRX(x) (((x) + 1) & VR_NRXDESC_MASK) 178 179 /* 180 * Control data structres that are DMA'd to the Rhine chip. We allocate 181 * them in a single clump that maps to a single DMA segment to make several 182 * things easier. 183 * 184 * Note that since we always copy outgoing packets to aligned transmit 185 * buffers, we can reduce the transmit descriptors to one per packet. 186 */ 187 struct vr_control_data { 188 struct vr_desc vr_txdescs[VR_NTXDESC]; 189 struct vr_desc vr_rxdescs[VR_NRXDESC]; 190 }; 191 192 #define VR_CDOFF(x) offsetof(struct vr_control_data, x) 193 #define VR_CDTXOFF(x) VR_CDOFF(vr_txdescs[(x)]) 194 #define VR_CDRXOFF(x) VR_CDOFF(vr_rxdescs[(x)]) 195 196 /* 197 * Software state of transmit and receive descriptors. 198 */ 199 struct vr_descsoft { 200 struct mbuf *ds_mbuf; /* head of mbuf chain */ 201 bus_dmamap_t ds_dmamap; /* our DMA map */ 202 }; 203 204 struct vr_softc { 205 struct device vr_dev; /* generic device glue */ 206 void *vr_ih; /* interrupt cookie */ 207 void *vr_ats; /* shutdown hook */ 208 bus_space_tag_t vr_bst; /* bus space tag */ 209 bus_space_handle_t vr_bsh; /* bus space handle */ 210 bus_dma_tag_t vr_dmat; /* bus DMA tag */ 211 pci_chipset_tag_t vr_pc; /* PCI chipset info */ 212 struct ethercom vr_ec; /* Ethernet common info */ 213 u_int8_t vr_enaddr[ETHER_ADDR_LEN]; 214 struct mii_data vr_mii; /* MII/media info */ 215 216 struct callout vr_tick_ch; /* tick callout */ 217 218 bus_dmamap_t vr_cddmamap; /* control data DMA map */ 219 #define vr_cddma vr_cddmamap->dm_segs[0].ds_addr 220 221 /* 222 * Software state for transmit and receive descriptors. 223 */ 224 struct vr_descsoft vr_txsoft[VR_NTXDESC]; 225 struct vr_descsoft vr_rxsoft[VR_NRXDESC]; 226 227 /* 228 * Control data structures. 229 */ 230 struct vr_control_data *vr_control_data; 231 232 int vr_txpending; /* number of TX requests pending */ 233 int vr_txdirty; /* first dirty TX descriptor */ 234 int vr_txlast; /* last used TX descriptor */ 235 236 int vr_rxptr; /* next ready RX descriptor */ 237 }; 238 239 #define VR_CDTXADDR(sc, x) ((sc)->vr_cddma + VR_CDTXOFF((x))) 240 #define VR_CDRXADDR(sc, x) ((sc)->vr_cddma + VR_CDRXOFF((x))) 241 242 #define VR_CDTX(sc, x) (&(sc)->vr_control_data->vr_txdescs[(x)]) 243 #define VR_CDRX(sc, x) (&(sc)->vr_control_data->vr_rxdescs[(x)]) 244 245 #define VR_DSTX(sc, x) (&(sc)->vr_txsoft[(x)]) 246 #define VR_DSRX(sc, x) (&(sc)->vr_rxsoft[(x)]) 247 248 #define VR_CDTXSYNC(sc, x, ops) \ 249 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 250 VR_CDTXOFF((x)), sizeof(struct vr_desc), (ops)) 251 252 #define VR_CDRXSYNC(sc, x, ops) \ 253 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 254 VR_CDRXOFF((x)), sizeof(struct vr_desc), (ops)) 255 256 /* 257 * Note we rely on MCLBYTES being a power of two below. 258 */ 259 #define VR_INIT_RXDESC(sc, i) \ 260 do { \ 261 struct vr_desc *__d = VR_CDRX((sc), (i)); \ 262 struct vr_descsoft *__ds = VR_DSRX((sc), (i)); \ 263 \ 264 __d->vr_next = htole32(VR_CDRXADDR((sc), VR_NEXTRX((i)))); \ 265 __d->vr_status = htole32(VR_RXSTAT_FIRSTFRAG | \ 266 VR_RXSTAT_LASTFRAG | VR_RXSTAT_OWN); \ 267 __d->vr_data = htole32(__ds->ds_dmamap->dm_segs[0].ds_addr); \ 268 __d->vr_ctl = htole32(VR_RXCTL_CHAIN | VR_RXCTL_RX_INTR | \ 269 ((MCLBYTES - 1) & VR_RXCTL_BUFLEN)); \ 270 VR_CDRXSYNC((sc), (i), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 271 } while (0) 272 273 /* 274 * register space access macros 275 */ 276 #define CSR_WRITE_4(sc, reg, val) \ 277 bus_space_write_4(sc->vr_bst, sc->vr_bsh, reg, val) 278 #define CSR_WRITE_2(sc, reg, val) \ 279 bus_space_write_2(sc->vr_bst, sc->vr_bsh, reg, val) 280 #define CSR_WRITE_1(sc, reg, val) \ 281 bus_space_write_1(sc->vr_bst, sc->vr_bsh, reg, val) 282 283 #define CSR_READ_4(sc, reg) \ 284 bus_space_read_4(sc->vr_bst, sc->vr_bsh, reg) 285 #define CSR_READ_2(sc, reg) \ 286 bus_space_read_2(sc->vr_bst, sc->vr_bsh, reg) 287 #define CSR_READ_1(sc, reg) \ 288 bus_space_read_1(sc->vr_bst, sc->vr_bsh, reg) 289 290 #define VR_TIMEOUT 1000 291 292 static int vr_add_rxbuf __P((struct vr_softc *, int)); 293 294 static void vr_rxeof __P((struct vr_softc *)); 295 static void vr_rxeoc __P((struct vr_softc *)); 296 static void vr_txeof __P((struct vr_softc *)); 297 static int vr_intr __P((void *)); 298 static void vr_start __P((struct ifnet *)); 299 static int vr_ioctl __P((struct ifnet *, u_long, caddr_t)); 300 static int vr_init __P((struct ifnet *)); 301 static void vr_stop __P((struct ifnet *, int)); 302 static void vr_rxdrain __P((struct vr_softc *)); 303 static void vr_watchdog __P((struct ifnet *)); 304 static void vr_tick __P((void *)); 305 306 static int vr_ifmedia_upd __P((struct ifnet *)); 307 static void vr_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 308 309 static int vr_mii_readreg __P((struct device *, int, int)); 310 static void vr_mii_writereg __P((struct device *, int, int, int)); 311 static void vr_mii_statchg __P((struct device *)); 312 313 static void vr_setmulti __P((struct vr_softc *)); 314 static void vr_reset __P((struct vr_softc *)); 315 316 int vr_copy_small = 0; 317 318 #define VR_SETBIT(sc, reg, x) \ 319 CSR_WRITE_1(sc, reg, \ 320 CSR_READ_1(sc, reg) | x) 321 322 #define VR_CLRBIT(sc, reg, x) \ 323 CSR_WRITE_1(sc, reg, \ 324 CSR_READ_1(sc, reg) & ~x) 325 326 #define VR_SETBIT16(sc, reg, x) \ 327 CSR_WRITE_2(sc, reg, \ 328 CSR_READ_2(sc, reg) | x) 329 330 #define VR_CLRBIT16(sc, reg, x) \ 331 CSR_WRITE_2(sc, reg, \ 332 CSR_READ_2(sc, reg) & ~x) 333 334 #define VR_SETBIT32(sc, reg, x) \ 335 CSR_WRITE_4(sc, reg, \ 336 CSR_READ_4(sc, reg) | x) 337 338 #define VR_CLRBIT32(sc, reg, x) \ 339 CSR_WRITE_4(sc, reg, \ 340 CSR_READ_4(sc, reg) & ~x) 341 342 /* 343 * MII bit-bang glue. 344 */ 345 u_int32_t vr_mii_bitbang_read __P((struct device *)); 346 void vr_mii_bitbang_write __P((struct device *, u_int32_t)); 347 348 const struct mii_bitbang_ops vr_mii_bitbang_ops = { 349 vr_mii_bitbang_read, 350 vr_mii_bitbang_write, 351 { 352 VR_MIICMD_DATAOUT, /* MII_BIT_MDO */ 353 VR_MIICMD_DATAIN, /* MII_BIT_MDI */ 354 VR_MIICMD_CLK, /* MII_BIT_MDC */ 355 VR_MIICMD_DIR, /* MII_BIT_DIR_HOST_PHY */ 356 0, /* MII_BIT_DIR_PHY_HOST */ 357 } 358 }; 359 360 u_int32_t 361 vr_mii_bitbang_read(self) 362 struct device *self; 363 { 364 struct vr_softc *sc = (void *) self; 365 366 return (CSR_READ_1(sc, VR_MIICMD)); 367 } 368 369 void 370 vr_mii_bitbang_write(self, val) 371 struct device *self; 372 u_int32_t val; 373 { 374 struct vr_softc *sc = (void *) self; 375 376 CSR_WRITE_1(sc, VR_MIICMD, (val & 0xff) | VR_MIICMD_DIRECTPGM); 377 } 378 379 /* 380 * Read an PHY register through the MII. 381 */ 382 static int 383 vr_mii_readreg(self, phy, reg) 384 struct device *self; 385 int phy, reg; 386 { 387 struct vr_softc *sc = (void *) self; 388 389 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 390 return (mii_bitbang_readreg(self, &vr_mii_bitbang_ops, phy, reg)); 391 } 392 393 /* 394 * Write to a PHY register through the MII. 395 */ 396 static void 397 vr_mii_writereg(self, phy, reg, val) 398 struct device *self; 399 int phy, reg, val; 400 { 401 struct vr_softc *sc = (void *) self; 402 403 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 404 mii_bitbang_writereg(self, &vr_mii_bitbang_ops, phy, reg, val); 405 } 406 407 static void 408 vr_mii_statchg(self) 409 struct device *self; 410 { 411 struct vr_softc *sc = (struct vr_softc *)self; 412 413 /* 414 * In order to fiddle with the 'full-duplex' bit in the netconfig 415 * register, we first have to put the transmit and/or receive logic 416 * in the idle state. 417 */ 418 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 419 420 if (sc->vr_mii.mii_media_active & IFM_FDX) 421 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 422 else 423 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 424 425 if (sc->vr_ec.ec_if.if_flags & IFF_RUNNING) 426 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 427 } 428 429 #define vr_calchash(addr) \ 430 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 431 432 /* 433 * Program the 64-bit multicast hash filter. 434 */ 435 static void 436 vr_setmulti(sc) 437 struct vr_softc *sc; 438 { 439 struct ifnet *ifp; 440 int h = 0; 441 u_int32_t hashes[2] = { 0, 0 }; 442 struct ether_multistep step; 443 struct ether_multi *enm; 444 int mcnt = 0; 445 u_int8_t rxfilt; 446 447 ifp = &sc->vr_ec.ec_if; 448 449 rxfilt = CSR_READ_1(sc, VR_RXCFG); 450 451 if (ifp->if_flags & IFF_PROMISC) { 452 allmulti: 453 ifp->if_flags |= IFF_ALLMULTI; 454 rxfilt |= VR_RXCFG_RX_MULTI; 455 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 456 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 457 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 458 return; 459 } 460 461 /* first, zot all the existing hash bits */ 462 CSR_WRITE_4(sc, VR_MAR0, 0); 463 CSR_WRITE_4(sc, VR_MAR1, 0); 464 465 /* now program new ones */ 466 ETHER_FIRST_MULTI(step, &sc->vr_ec, enm); 467 while (enm != NULL) { 468 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 469 ETHER_ADDR_LEN) != 0) 470 goto allmulti; 471 472 h = vr_calchash(enm->enm_addrlo); 473 474 if (h < 32) 475 hashes[0] |= (1 << h); 476 else 477 hashes[1] |= (1 << (h - 32)); 478 ETHER_NEXT_MULTI(step, enm); 479 mcnt++; 480 } 481 482 ifp->if_flags &= ~IFF_ALLMULTI; 483 484 if (mcnt) 485 rxfilt |= VR_RXCFG_RX_MULTI; 486 else 487 rxfilt &= ~VR_RXCFG_RX_MULTI; 488 489 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 490 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 491 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 492 } 493 494 static void 495 vr_reset(sc) 496 struct vr_softc *sc; 497 { 498 int i; 499 500 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 501 502 for (i = 0; i < VR_TIMEOUT; i++) { 503 DELAY(10); 504 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 505 break; 506 } 507 if (i == VR_TIMEOUT) 508 printf("%s: reset never completed!\n", 509 sc->vr_dev.dv_xname); 510 511 /* Wait a little while for the chip to get its brains in order. */ 512 DELAY(1000); 513 } 514 515 /* 516 * Initialize an RX descriptor and attach an MBUF cluster. 517 * Note: the length fields are only 11 bits wide, which means the 518 * largest size we can specify is 2047. This is important because 519 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 520 * overflow the field and make a mess. 521 */ 522 static int 523 vr_add_rxbuf(sc, i) 524 struct vr_softc *sc; 525 int i; 526 { 527 struct vr_descsoft *ds = VR_DSRX(sc, i); 528 struct mbuf *m_new; 529 int error; 530 531 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 532 if (m_new == NULL) 533 return (ENOBUFS); 534 535 MCLGET(m_new, M_DONTWAIT); 536 if ((m_new->m_flags & M_EXT) == 0) { 537 m_freem(m_new); 538 return (ENOBUFS); 539 } 540 541 if (ds->ds_mbuf != NULL) 542 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 543 544 ds->ds_mbuf = m_new; 545 546 error = bus_dmamap_load(sc->vr_dmat, ds->ds_dmamap, 547 m_new->m_ext.ext_buf, m_new->m_ext.ext_size, NULL, 548 BUS_DMA_READ|BUS_DMA_NOWAIT); 549 if (error) { 550 printf("%s: unable to load rx DMA map %d, error = %d\n", 551 sc->vr_dev.dv_xname, i, error); 552 panic("vr_add_rxbuf"); /* XXX */ 553 } 554 555 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 556 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 557 558 VR_INIT_RXDESC(sc, i); 559 560 return (0); 561 } 562 563 /* 564 * A frame has been uploaded: pass the resulting mbuf chain up to 565 * the higher level protocols. 566 */ 567 static void 568 vr_rxeof(sc) 569 struct vr_softc *sc; 570 { 571 struct mbuf *m; 572 struct ifnet *ifp; 573 struct vr_desc *d; 574 struct vr_descsoft *ds; 575 int i, total_len; 576 u_int32_t rxstat; 577 578 ifp = &sc->vr_ec.ec_if; 579 580 for (i = sc->vr_rxptr;; i = VR_NEXTRX(i)) { 581 d = VR_CDRX(sc, i); 582 ds = VR_DSRX(sc, i); 583 584 VR_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 585 586 rxstat = le32toh(d->vr_status); 587 588 if (rxstat & VR_RXSTAT_OWN) { 589 /* 590 * We have processed all of the receive buffers. 591 */ 592 break; 593 } 594 595 /* 596 * If an error occurs, update stats, clear the 597 * status word and leave the mbuf cluster in place: 598 * it should simply get re-used next time this descriptor 599 * comes up in the ring. 600 */ 601 if (rxstat & VR_RXSTAT_RXERR) { 602 const char *errstr; 603 604 ifp->if_ierrors++; 605 switch (rxstat & 0x000000FF) { 606 case VR_RXSTAT_CRCERR: 607 errstr = "crc error"; 608 break; 609 case VR_RXSTAT_FRAMEALIGNERR: 610 errstr = "frame alignment error"; 611 break; 612 case VR_RXSTAT_FIFOOFLOW: 613 errstr = "FIFO overflow"; 614 break; 615 case VR_RXSTAT_GIANT: 616 errstr = "received giant packet"; 617 break; 618 case VR_RXSTAT_RUNT: 619 errstr = "received runt packet"; 620 break; 621 case VR_RXSTAT_BUSERR: 622 errstr = "system bus error"; 623 break; 624 case VR_RXSTAT_BUFFERR: 625 errstr = "rx buffer error"; 626 break; 627 default: 628 errstr = "unknown rx error"; 629 break; 630 } 631 printf("%s: receive error: %s\n", sc->vr_dev.dv_xname, 632 errstr); 633 634 VR_INIT_RXDESC(sc, i); 635 636 continue; 637 } 638 639 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 640 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 641 642 /* No errors; receive the packet. */ 643 total_len = VR_RXBYTES(le32toh(d->vr_status)); 644 645 #ifdef __NO_STRICT_ALIGNMENT 646 /* 647 * If the packet is small enough to fit in a 648 * single header mbuf, allocate one and copy 649 * the data into it. This greatly reduces 650 * memory consumption when we receive lots 651 * of small packets. 652 * 653 * Otherwise, we add a new buffer to the receive 654 * chain. If this fails, we drop the packet and 655 * recycle the old buffer. 656 */ 657 if (vr_copy_small != 0 && total_len <= MHLEN) { 658 MGETHDR(m, M_DONTWAIT, MT_DATA); 659 if (m == NULL) 660 goto dropit; 661 memcpy(mtod(m, caddr_t), 662 mtod(ds->ds_mbuf, caddr_t), total_len); 663 VR_INIT_RXDESC(sc, i); 664 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 665 ds->ds_dmamap->dm_mapsize, 666 BUS_DMASYNC_PREREAD); 667 } else { 668 m = ds->ds_mbuf; 669 if (vr_add_rxbuf(sc, i) == ENOBUFS) { 670 dropit: 671 ifp->if_ierrors++; 672 VR_INIT_RXDESC(sc, i); 673 bus_dmamap_sync(sc->vr_dmat, 674 ds->ds_dmamap, 0, 675 ds->ds_dmamap->dm_mapsize, 676 BUS_DMASYNC_PREREAD); 677 continue; 678 } 679 } 680 #else 681 /* 682 * The Rhine's packet buffers must be 4-byte aligned. 683 * But this means that the data after the Ethernet header 684 * is misaligned. We must allocate a new buffer and 685 * copy the data, shifted forward 2 bytes. 686 */ 687 MGETHDR(m, M_DONTWAIT, MT_DATA); 688 if (m == NULL) { 689 dropit: 690 ifp->if_ierrors++; 691 VR_INIT_RXDESC(sc, i); 692 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 693 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 694 continue; 695 } 696 if (total_len > (MHLEN - 2)) { 697 MCLGET(m, M_DONTWAIT); 698 if ((m->m_flags & M_EXT) == 0) { 699 m_freem(m); 700 goto dropit; 701 } 702 } 703 m->m_data += 2; 704 705 /* 706 * Note that we use clusters for incoming frames, so the 707 * buffer is virtually contiguous. 708 */ 709 memcpy(mtod(m, caddr_t), mtod(ds->ds_mbuf, caddr_t), 710 total_len); 711 712 /* Allow the receive descriptor to continue using its mbuf. */ 713 VR_INIT_RXDESC(sc, i); 714 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 715 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 716 #endif /* __NO_STRICT_ALIGNMENT */ 717 718 /* 719 * The Rhine chip includes the FCS with every 720 * received packet. 721 */ 722 m->m_flags |= M_HASFCS; 723 724 ifp->if_ipackets++; 725 m->m_pkthdr.rcvif = ifp; 726 m->m_pkthdr.len = m->m_len = total_len; 727 #if NBPFILTER > 0 728 /* 729 * Handle BPF listeners. Let the BPF user see the packet, but 730 * don't pass it up to the ether_input() layer unless it's 731 * a broadcast packet, multicast packet, matches our ethernet 732 * address or the interface is in promiscuous mode. 733 */ 734 if (ifp->if_bpf) 735 bpf_mtap(ifp->if_bpf, m); 736 #endif 737 /* Pass it on. */ 738 (*ifp->if_input)(ifp, m); 739 } 740 741 /* Update the receive pointer. */ 742 sc->vr_rxptr = i; 743 } 744 745 void 746 vr_rxeoc(sc) 747 struct vr_softc *sc; 748 { 749 750 vr_rxeof(sc); 751 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 752 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 753 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 754 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 755 } 756 757 /* 758 * A frame was downloaded to the chip. It's safe for us to clean up 759 * the list buffers. 760 */ 761 static void 762 vr_txeof(sc) 763 struct vr_softc *sc; 764 { 765 struct ifnet *ifp = &sc->vr_ec.ec_if; 766 struct vr_desc *d; 767 struct vr_descsoft *ds; 768 u_int32_t txstat; 769 int i; 770 771 ifp->if_flags &= ~IFF_OACTIVE; 772 773 /* 774 * Go through our tx list and free mbufs for those 775 * frames that have been transmitted. 776 */ 777 for (i = sc->vr_txdirty; sc->vr_txpending != 0; 778 i = VR_NEXTTX(i), sc->vr_txpending--) { 779 d = VR_CDTX(sc, i); 780 ds = VR_DSTX(sc, i); 781 782 VR_CDTXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 783 784 txstat = le32toh(d->vr_status); 785 if (txstat & VR_TXSTAT_OWN) 786 break; 787 788 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 789 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 790 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 791 m_freem(ds->ds_mbuf); 792 ds->ds_mbuf = NULL; 793 794 if (txstat & VR_TXSTAT_ERRSUM) { 795 ifp->if_oerrors++; 796 if (txstat & VR_TXSTAT_DEFER) 797 ifp->if_collisions++; 798 if (txstat & VR_TXSTAT_LATECOLL) 799 ifp->if_collisions++; 800 } 801 802 ifp->if_collisions += (txstat & VR_TXSTAT_COLLCNT) >> 3; 803 ifp->if_opackets++; 804 } 805 806 /* Update the dirty transmit buffer pointer. */ 807 sc->vr_txdirty = i; 808 809 /* 810 * Cancel the watchdog timer if there are no pending 811 * transmissions. 812 */ 813 if (sc->vr_txpending == 0) 814 ifp->if_timer = 0; 815 } 816 817 static int 818 vr_intr(arg) 819 void *arg; 820 { 821 struct vr_softc *sc; 822 struct ifnet *ifp; 823 u_int16_t status; 824 int handled = 0, dotx = 0; 825 826 sc = arg; 827 ifp = &sc->vr_ec.ec_if; 828 829 /* Suppress unwanted interrupts. */ 830 if ((ifp->if_flags & IFF_UP) == 0) { 831 vr_stop(ifp, 1); 832 return (0); 833 } 834 835 /* Disable interrupts. */ 836 CSR_WRITE_2(sc, VR_IMR, 0x0000); 837 838 for (;;) { 839 status = CSR_READ_2(sc, VR_ISR); 840 if (status) 841 CSR_WRITE_2(sc, VR_ISR, status); 842 843 if ((status & VR_INTRS) == 0) 844 break; 845 846 handled = 1; 847 848 if (status & VR_ISR_RX_OK) 849 vr_rxeof(sc); 850 851 if (status & 852 (VR_ISR_RX_ERR | VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW | 853 VR_ISR_RX_DROPPED)) 854 vr_rxeoc(sc); 855 856 if (status & VR_ISR_TX_OK) { 857 dotx = 1; 858 vr_txeof(sc); 859 } 860 861 if (status & (VR_ISR_TX_UNDERRUN | VR_ISR_TX_ABRT)) { 862 if (status & VR_ISR_TX_UNDERRUN) 863 printf("%s: transmit underrun\n", 864 sc->vr_dev.dv_xname); 865 if (status & VR_ISR_TX_ABRT) 866 printf("%s: transmit aborted\n", 867 sc->vr_dev.dv_xname); 868 ifp->if_oerrors++; 869 dotx = 1; 870 vr_txeof(sc); 871 if (sc->vr_txpending) { 872 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 873 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 874 } 875 } 876 877 if (status & VR_ISR_BUSERR) { 878 printf("%s: PCI bus error\n", sc->vr_dev.dv_xname); 879 /* vr_init() calls vr_start() */ 880 dotx = 0; 881 (void) vr_init(ifp); 882 } 883 } 884 885 /* Re-enable interrupts. */ 886 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 887 888 if (dotx) 889 vr_start(ifp); 890 891 return (handled); 892 } 893 894 /* 895 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 896 * to the mbuf data regions directly in the transmit lists. We also save a 897 * copy of the pointers since the transmit list fragment pointers are 898 * physical addresses. 899 */ 900 static void 901 vr_start(ifp) 902 struct ifnet *ifp; 903 { 904 struct vr_softc *sc = ifp->if_softc; 905 struct mbuf *m0, *m; 906 struct vr_desc *d; 907 struct vr_descsoft *ds; 908 int error, firsttx, nexttx, opending; 909 910 /* 911 * Remember the previous txpending and the first transmit 912 * descriptor we use. 913 */ 914 opending = sc->vr_txpending; 915 firsttx = VR_NEXTTX(sc->vr_txlast); 916 917 /* 918 * Loop through the send queue, setting up transmit descriptors 919 * until we drain the queue, or use up all available transmit 920 * descriptors. 921 */ 922 while (sc->vr_txpending < VR_NTXDESC) { 923 /* 924 * Grab a packet off the queue. 925 */ 926 IFQ_POLL(&ifp->if_snd, m0); 927 if (m0 == NULL) 928 break; 929 m = NULL; 930 931 /* 932 * Get the next available transmit descriptor. 933 */ 934 nexttx = VR_NEXTTX(sc->vr_txlast); 935 d = VR_CDTX(sc, nexttx); 936 ds = VR_DSTX(sc, nexttx); 937 938 /* 939 * Load the DMA map. If this fails, the packet didn't 940 * fit in one DMA segment, and we need to copy. Note, 941 * the packet must also be aligned. 942 */ 943 if ((mtod(m0, uintptr_t) & 3) != 0 || 944 bus_dmamap_load_mbuf(sc->vr_dmat, ds->ds_dmamap, m0, 945 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 946 MGETHDR(m, M_DONTWAIT, MT_DATA); 947 if (m == NULL) { 948 printf("%s: unable to allocate Tx mbuf\n", 949 sc->vr_dev.dv_xname); 950 break; 951 } 952 if (m0->m_pkthdr.len > MHLEN) { 953 MCLGET(m, M_DONTWAIT); 954 if ((m->m_flags & M_EXT) == 0) { 955 printf("%s: unable to allocate Tx " 956 "cluster\n", sc->vr_dev.dv_xname); 957 m_freem(m); 958 break; 959 } 960 } 961 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 962 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 963 error = bus_dmamap_load_mbuf(sc->vr_dmat, 964 ds->ds_dmamap, m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 965 if (error) { 966 printf("%s: unable to load Tx buffer, " 967 "error = %d\n", sc->vr_dev.dv_xname, error); 968 break; 969 } 970 } 971 972 IFQ_DEQUEUE(&ifp->if_snd, m0); 973 if (m != NULL) { 974 m_freem(m0); 975 m0 = m; 976 } 977 978 /* Sync the DMA map. */ 979 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 980 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 981 982 /* 983 * Store a pointer to the packet so we can free it later. 984 */ 985 ds->ds_mbuf = m0; 986 987 #if NBPFILTER > 0 988 /* 989 * If there's a BPF listener, bounce a copy of this frame 990 * to him. 991 */ 992 if (ifp->if_bpf) 993 bpf_mtap(ifp->if_bpf, m0); 994 #endif 995 996 /* 997 * Fill in the transmit descriptor. The Rhine 998 * doesn't auto-pad, so we have to do this ourselves. 999 */ 1000 d->vr_data = htole32(ds->ds_dmamap->dm_segs[0].ds_addr); 1001 d->vr_ctl = htole32(m0->m_pkthdr.len < VR_MIN_FRAMELEN ? 1002 VR_MIN_FRAMELEN : m0->m_pkthdr.len); 1003 d->vr_ctl |= 1004 htole32(VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG| 1005 VR_TXCTL_LASTFRAG); 1006 1007 /* 1008 * If this is the first descriptor we're enqueuing, 1009 * don't give it to the Rhine yet. That could cause 1010 * a race condition. We'll do it below. 1011 */ 1012 if (nexttx == firsttx) 1013 d->vr_status = 0; 1014 else 1015 d->vr_status = htole32(VR_TXSTAT_OWN); 1016 1017 VR_CDTXSYNC(sc, nexttx, 1018 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1019 1020 /* Advance the tx pointer. */ 1021 sc->vr_txpending++; 1022 sc->vr_txlast = nexttx; 1023 } 1024 1025 if (sc->vr_txpending == VR_NTXDESC) { 1026 /* No more slots left; notify upper layer. */ 1027 ifp->if_flags |= IFF_OACTIVE; 1028 } 1029 1030 if (sc->vr_txpending != opending) { 1031 /* 1032 * We enqueued packets. If the transmitter was idle, 1033 * reset the txdirty pointer. 1034 */ 1035 if (opending == 0) 1036 sc->vr_txdirty = firsttx; 1037 1038 /* 1039 * Cause a transmit interrupt to happen on the 1040 * last packet we enqueued. 1041 */ 1042 VR_CDTX(sc, sc->vr_txlast)->vr_ctl |= htole32(VR_TXCTL_FINT); 1043 VR_CDTXSYNC(sc, sc->vr_txlast, 1044 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1045 1046 /* 1047 * The entire packet chain is set up. Give the 1048 * first descriptor to the Rhine now. 1049 */ 1050 VR_CDTX(sc, firsttx)->vr_status = htole32(VR_TXSTAT_OWN); 1051 VR_CDTXSYNC(sc, firsttx, 1052 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1053 1054 /* Start the transmitter. */ 1055 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_TX_GO); 1056 1057 /* Set the watchdog timer in case the chip flakes out. */ 1058 ifp->if_timer = 5; 1059 } 1060 } 1061 1062 /* 1063 * Initialize the interface. Must be called at splnet. 1064 */ 1065 static int 1066 vr_init(ifp) 1067 struct ifnet *ifp; 1068 { 1069 struct vr_softc *sc = ifp->if_softc; 1070 struct vr_desc *d; 1071 struct vr_descsoft *ds; 1072 int i, error = 0; 1073 1074 /* Cancel pending I/O. */ 1075 vr_stop(ifp, 0); 1076 1077 /* Reset the Rhine to a known state. */ 1078 vr_reset(sc); 1079 1080 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1081 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_STORENFWD); 1082 1083 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1084 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1085 1086 /* 1087 * Initialize the transmit desciptor ring. txlast is initialized 1088 * to the end of the list so that it will wrap around to the first 1089 * descriptor when the first packet is transmitted. 1090 */ 1091 for (i = 0; i < VR_NTXDESC; i++) { 1092 d = VR_CDTX(sc, i); 1093 memset(d, 0, sizeof(struct vr_desc)); 1094 d->vr_next = htole32(VR_CDTXADDR(sc, VR_NEXTTX(i))); 1095 VR_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1096 } 1097 sc->vr_txpending = 0; 1098 sc->vr_txdirty = 0; 1099 sc->vr_txlast = VR_NTXDESC - 1; 1100 1101 /* 1102 * Initialize the receive descriptor ring. 1103 */ 1104 for (i = 0; i < VR_NRXDESC; i++) { 1105 ds = VR_DSRX(sc, i); 1106 if (ds->ds_mbuf == NULL) { 1107 if ((error = vr_add_rxbuf(sc, i)) != 0) { 1108 printf("%s: unable to allocate or map rx " 1109 "buffer %d, error = %d\n", 1110 sc->vr_dev.dv_xname, i, error); 1111 /* 1112 * XXX Should attempt to run with fewer receive 1113 * XXX buffers instead of just failing. 1114 */ 1115 vr_rxdrain(sc); 1116 goto out; 1117 } 1118 } else 1119 VR_INIT_RXDESC(sc, i); 1120 } 1121 sc->vr_rxptr = 0; 1122 1123 /* If we want promiscuous mode, set the allframes bit. */ 1124 if (ifp->if_flags & IFF_PROMISC) 1125 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1126 else 1127 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1128 1129 /* Set capture broadcast bit to capture broadcast frames. */ 1130 if (ifp->if_flags & IFF_BROADCAST) 1131 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1132 else 1133 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1134 1135 /* Program the multicast filter, if necessary. */ 1136 vr_setmulti(sc); 1137 1138 /* Give the transmit and receive rings to the Rhine. */ 1139 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 1140 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, VR_NEXTTX(sc->vr_txlast))); 1141 1142 /* Set current media. */ 1143 mii_mediachg(&sc->vr_mii); 1144 1145 /* Enable receiver and transmitter. */ 1146 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1147 VR_CMD_TX_ON|VR_CMD_RX_ON| 1148 VR_CMD_RX_GO); 1149 1150 /* Enable interrupts. */ 1151 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1152 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1153 1154 ifp->if_flags |= IFF_RUNNING; 1155 ifp->if_flags &= ~IFF_OACTIVE; 1156 1157 /* Start one second timer. */ 1158 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1159 1160 /* Attempt to start output on the interface. */ 1161 vr_start(ifp); 1162 1163 out: 1164 if (error) 1165 printf("%s: interface not running\n", sc->vr_dev.dv_xname); 1166 return (error); 1167 } 1168 1169 /* 1170 * Set media options. 1171 */ 1172 static int 1173 vr_ifmedia_upd(ifp) 1174 struct ifnet *ifp; 1175 { 1176 struct vr_softc *sc = ifp->if_softc; 1177 1178 if (ifp->if_flags & IFF_UP) 1179 mii_mediachg(&sc->vr_mii); 1180 return (0); 1181 } 1182 1183 /* 1184 * Report current media status. 1185 */ 1186 static void 1187 vr_ifmedia_sts(ifp, ifmr) 1188 struct ifnet *ifp; 1189 struct ifmediareq *ifmr; 1190 { 1191 struct vr_softc *sc = ifp->if_softc; 1192 1193 mii_pollstat(&sc->vr_mii); 1194 ifmr->ifm_status = sc->vr_mii.mii_media_status; 1195 ifmr->ifm_active = sc->vr_mii.mii_media_active; 1196 } 1197 1198 static int 1199 vr_ioctl(ifp, command, data) 1200 struct ifnet *ifp; 1201 u_long command; 1202 caddr_t data; 1203 { 1204 struct vr_softc *sc = ifp->if_softc; 1205 struct ifreq *ifr = (struct ifreq *)data; 1206 int s, error = 0; 1207 1208 s = splnet(); 1209 1210 switch (command) { 1211 case SIOCGIFMEDIA: 1212 case SIOCSIFMEDIA: 1213 error = ifmedia_ioctl(ifp, ifr, &sc->vr_mii.mii_media, command); 1214 break; 1215 1216 default: 1217 error = ether_ioctl(ifp, command, data); 1218 if (error == ENETRESET) { 1219 /* 1220 * Multicast list has changed; set the hardware filter 1221 * accordingly. 1222 */ 1223 vr_setmulti(sc); 1224 error = 0; 1225 } 1226 break; 1227 } 1228 1229 splx(s); 1230 return (error); 1231 } 1232 1233 static void 1234 vr_watchdog(ifp) 1235 struct ifnet *ifp; 1236 { 1237 struct vr_softc *sc = ifp->if_softc; 1238 1239 printf("%s: device timeout\n", sc->vr_dev.dv_xname); 1240 ifp->if_oerrors++; 1241 1242 (void) vr_init(ifp); 1243 } 1244 1245 /* 1246 * One second timer, used to tick MII. 1247 */ 1248 static void 1249 vr_tick(arg) 1250 void *arg; 1251 { 1252 struct vr_softc *sc = arg; 1253 int s; 1254 1255 s = splnet(); 1256 mii_tick(&sc->vr_mii); 1257 splx(s); 1258 1259 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1260 } 1261 1262 /* 1263 * Drain the receive queue. 1264 */ 1265 static void 1266 vr_rxdrain(sc) 1267 struct vr_softc *sc; 1268 { 1269 struct vr_descsoft *ds; 1270 int i; 1271 1272 for (i = 0; i < VR_NRXDESC; i++) { 1273 ds = VR_DSRX(sc, i); 1274 if (ds->ds_mbuf != NULL) { 1275 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1276 m_freem(ds->ds_mbuf); 1277 ds->ds_mbuf = NULL; 1278 } 1279 } 1280 } 1281 1282 /* 1283 * Stop the adapter and free any mbufs allocated to the 1284 * transmit lists. 1285 */ 1286 static void 1287 vr_stop(ifp, disable) 1288 struct ifnet *ifp; 1289 int disable; 1290 { 1291 struct vr_softc *sc = ifp->if_softc; 1292 struct vr_descsoft *ds; 1293 int i; 1294 1295 /* Cancel one second timer. */ 1296 callout_stop(&sc->vr_tick_ch); 1297 1298 /* Down the MII. */ 1299 mii_down(&sc->vr_mii); 1300 1301 ifp = &sc->vr_ec.ec_if; 1302 ifp->if_timer = 0; 1303 1304 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1305 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1306 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1307 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1308 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1309 1310 /* 1311 * Release any queued transmit buffers. 1312 */ 1313 for (i = 0; i < VR_NTXDESC; i++) { 1314 ds = VR_DSTX(sc, i); 1315 if (ds->ds_mbuf != NULL) { 1316 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1317 m_freem(ds->ds_mbuf); 1318 ds->ds_mbuf = NULL; 1319 } 1320 } 1321 1322 if (disable) 1323 vr_rxdrain(sc); 1324 1325 /* 1326 * Mark the interface down and cancel the watchdog timer. 1327 */ 1328 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1329 ifp->if_timer = 0; 1330 } 1331 1332 static struct vr_type *vr_lookup __P((struct pci_attach_args *)); 1333 static int vr_probe __P((struct device *, struct cfdata *, void *)); 1334 static void vr_attach __P((struct device *, struct device *, void *)); 1335 static void vr_shutdown __P((void *)); 1336 1337 struct cfattach vr_ca = { 1338 sizeof (struct vr_softc), vr_probe, vr_attach 1339 }; 1340 1341 static struct vr_type * 1342 vr_lookup(pa) 1343 struct pci_attach_args *pa; 1344 { 1345 struct vr_type *vrt; 1346 1347 for (vrt = vr_devs; vrt->vr_name != NULL; vrt++) { 1348 if (PCI_VENDOR(pa->pa_id) == vrt->vr_vid && 1349 PCI_PRODUCT(pa->pa_id) == vrt->vr_did) 1350 return (vrt); 1351 } 1352 return (NULL); 1353 } 1354 1355 static int 1356 vr_probe(parent, match, aux) 1357 struct device *parent; 1358 struct cfdata *match; 1359 void *aux; 1360 { 1361 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1362 1363 if (vr_lookup(pa) != NULL) 1364 return (1); 1365 1366 return (0); 1367 } 1368 1369 /* 1370 * Stop all chip I/O so that the kernel's probe routines don't 1371 * get confused by errant DMAs when rebooting. 1372 */ 1373 static void 1374 vr_shutdown(arg) 1375 void *arg; 1376 { 1377 struct vr_softc *sc = (struct vr_softc *)arg; 1378 1379 vr_stop(&sc->vr_ec.ec_if, 1); 1380 } 1381 1382 /* 1383 * Attach the interface. Allocate softc structures, do ifmedia 1384 * setup and ethernet/BPF attach. 1385 */ 1386 static void 1387 vr_attach(parent, self, aux) 1388 struct device *parent; 1389 struct device *self; 1390 void *aux; 1391 { 1392 struct vr_softc *sc = (struct vr_softc *) self; 1393 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 1394 bus_dma_segment_t seg; 1395 struct vr_type *vrt; 1396 u_int32_t command; 1397 struct ifnet *ifp; 1398 u_char eaddr[ETHER_ADDR_LEN]; 1399 int i, rseg, error; 1400 1401 #define PCI_CONF_WRITE(r, v) pci_conf_write(pa->pa_pc, pa->pa_tag, (r), (v)) 1402 #define PCI_CONF_READ(r) pci_conf_read(pa->pa_pc, pa->pa_tag, (r)) 1403 1404 callout_init(&sc->vr_tick_ch); 1405 1406 vrt = vr_lookup(pa); 1407 if (vrt == NULL) { 1408 printf("\n"); 1409 panic("vr_attach: impossible"); 1410 } 1411 1412 printf(": %s Ethernet\n", vrt->vr_name); 1413 1414 /* 1415 * Handle power management nonsense. 1416 */ 1417 1418 command = PCI_CONF_READ(VR_PCI_CAPID) & 0x000000FF; 1419 if (command == 0x01) { 1420 command = PCI_CONF_READ(VR_PCI_PWRMGMTCTRL); 1421 if (command & VR_PSTATE_MASK) { 1422 u_int32_t iobase, membase, irq; 1423 1424 /* Save important PCI config data. */ 1425 iobase = PCI_CONF_READ(VR_PCI_LOIO); 1426 membase = PCI_CONF_READ(VR_PCI_LOMEM); 1427 irq = PCI_CONF_READ(VR_PCI_INTLINE); 1428 1429 /* Reset the power state. */ 1430 printf("%s: chip is in D%d power mode " 1431 "-- setting to D0\n", 1432 sc->vr_dev.dv_xname, command & VR_PSTATE_MASK); 1433 command &= 0xFFFFFFFC; 1434 PCI_CONF_WRITE(VR_PCI_PWRMGMTCTRL, command); 1435 1436 /* Restore PCI config data. */ 1437 PCI_CONF_WRITE(VR_PCI_LOIO, iobase); 1438 PCI_CONF_WRITE(VR_PCI_LOMEM, membase); 1439 PCI_CONF_WRITE(VR_PCI_INTLINE, irq); 1440 } 1441 } 1442 1443 /* Make sure bus mastering is enabled. */ 1444 command = PCI_CONF_READ(PCI_COMMAND_STATUS_REG); 1445 command |= PCI_COMMAND_MASTER_ENABLE; 1446 PCI_CONF_WRITE(PCI_COMMAND_STATUS_REG, command); 1447 1448 /* 1449 * Map control/status registers. 1450 */ 1451 { 1452 bus_space_tag_t iot, memt; 1453 bus_space_handle_t ioh, memh; 1454 int ioh_valid, memh_valid; 1455 pci_intr_handle_t intrhandle; 1456 const char *intrstr; 1457 1458 ioh_valid = (pci_mapreg_map(pa, VR_PCI_LOIO, 1459 PCI_MAPREG_TYPE_IO, 0, 1460 &iot, &ioh, NULL, NULL) == 0); 1461 memh_valid = (pci_mapreg_map(pa, VR_PCI_LOMEM, 1462 PCI_MAPREG_TYPE_MEM | 1463 PCI_MAPREG_MEM_TYPE_32BIT, 1464 0, &memt, &memh, NULL, NULL) == 0); 1465 #if defined(VR_USEIOSPACE) 1466 if (ioh_valid) { 1467 sc->vr_bst = iot; 1468 sc->vr_bsh = ioh; 1469 } else if (memh_valid) { 1470 sc->vr_bst = memt; 1471 sc->vr_bsh = memh; 1472 } 1473 #else 1474 if (memh_valid) { 1475 sc->vr_bst = memt; 1476 sc->vr_bsh = memh; 1477 } else if (ioh_valid) { 1478 sc->vr_bst = iot; 1479 sc->vr_bsh = ioh; 1480 } 1481 #endif 1482 else { 1483 printf(": unable to map device registers\n"); 1484 return; 1485 } 1486 1487 /* Allocate interrupt */ 1488 if (pci_intr_map(pa, &intrhandle)) { 1489 printf("%s: couldn't map interrupt\n", 1490 sc->vr_dev.dv_xname); 1491 return; 1492 } 1493 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1494 sc->vr_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 1495 vr_intr, sc); 1496 if (sc->vr_ih == NULL) { 1497 printf("%s: couldn't establish interrupt", 1498 sc->vr_dev.dv_xname); 1499 if (intrstr != NULL) 1500 printf(" at %s", intrstr); 1501 printf("\n"); 1502 } 1503 printf("%s: interrupting at %s\n", 1504 sc->vr_dev.dv_xname, intrstr); 1505 } 1506 1507 /* Reset the adapter. */ 1508 vr_reset(sc); 1509 1510 /* 1511 * Get station address. The way the Rhine chips work, 1512 * you're not allowed to directly access the EEPROM once 1513 * they've been programmed a special way. Consequently, 1514 * we need to read the node address from the PAR0 and PAR1 1515 * registers. 1516 */ 1517 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 1518 DELAY(200); 1519 for (i = 0; i < ETHER_ADDR_LEN; i++) 1520 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 1521 1522 /* 1523 * A Rhine chip was detected. Inform the world. 1524 */ 1525 printf("%s: Ethernet address: %s\n", 1526 sc->vr_dev.dv_xname, ether_sprintf(eaddr)); 1527 1528 memcpy(sc->vr_enaddr, eaddr, ETHER_ADDR_LEN); 1529 1530 sc->vr_dmat = pa->pa_dmat; 1531 1532 /* 1533 * Allocate the control data structures, and create and load 1534 * the DMA map for it. 1535 */ 1536 if ((error = bus_dmamem_alloc(sc->vr_dmat, 1537 sizeof(struct vr_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 1538 0)) != 0) { 1539 printf("%s: unable to allocate control data, error = %d\n", 1540 sc->vr_dev.dv_xname, error); 1541 goto fail_0; 1542 } 1543 1544 if ((error = bus_dmamem_map(sc->vr_dmat, &seg, rseg, 1545 sizeof(struct vr_control_data), (caddr_t *)&sc->vr_control_data, 1546 BUS_DMA_COHERENT)) != 0) { 1547 printf("%s: unable to map control data, error = %d\n", 1548 sc->vr_dev.dv_xname, error); 1549 goto fail_1; 1550 } 1551 1552 if ((error = bus_dmamap_create(sc->vr_dmat, 1553 sizeof(struct vr_control_data), 1, 1554 sizeof(struct vr_control_data), 0, 0, 1555 &sc->vr_cddmamap)) != 0) { 1556 printf("%s: unable to create control data DMA map, " 1557 "error = %d\n", sc->vr_dev.dv_xname, error); 1558 goto fail_2; 1559 } 1560 1561 if ((error = bus_dmamap_load(sc->vr_dmat, sc->vr_cddmamap, 1562 sc->vr_control_data, sizeof(struct vr_control_data), NULL, 1563 0)) != 0) { 1564 printf("%s: unable to load control data DMA map, error = %d\n", 1565 sc->vr_dev.dv_xname, error); 1566 goto fail_3; 1567 } 1568 1569 /* 1570 * Create the transmit buffer DMA maps. 1571 */ 1572 for (i = 0; i < VR_NTXDESC; i++) { 1573 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1574 1, MCLBYTES, 0, 0, 1575 &VR_DSTX(sc, i)->ds_dmamap)) != 0) { 1576 printf("%s: unable to create tx DMA map %d, " 1577 "error = %d\n", sc->vr_dev.dv_xname, i, error); 1578 goto fail_4; 1579 } 1580 } 1581 1582 /* 1583 * Create the receive buffer DMA maps. 1584 */ 1585 for (i = 0; i < VR_NRXDESC; i++) { 1586 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1, 1587 MCLBYTES, 0, 0, 1588 &VR_DSRX(sc, i)->ds_dmamap)) != 0) { 1589 printf("%s: unable to create rx DMA map %d, " 1590 "error = %d\n", sc->vr_dev.dv_xname, i, error); 1591 goto fail_5; 1592 } 1593 VR_DSRX(sc, i)->ds_mbuf = NULL; 1594 } 1595 1596 ifp = &sc->vr_ec.ec_if; 1597 ifp->if_softc = sc; 1598 ifp->if_mtu = ETHERMTU; 1599 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1600 ifp->if_ioctl = vr_ioctl; 1601 ifp->if_start = vr_start; 1602 ifp->if_watchdog = vr_watchdog; 1603 ifp->if_init = vr_init; 1604 ifp->if_stop = vr_stop; 1605 IFQ_SET_READY(&ifp->if_snd); 1606 1607 strcpy(ifp->if_xname, sc->vr_dev.dv_xname); 1608 1609 /* 1610 * Initialize MII/media info. 1611 */ 1612 sc->vr_mii.mii_ifp = ifp; 1613 sc->vr_mii.mii_readreg = vr_mii_readreg; 1614 sc->vr_mii.mii_writereg = vr_mii_writereg; 1615 sc->vr_mii.mii_statchg = vr_mii_statchg; 1616 ifmedia_init(&sc->vr_mii.mii_media, 0, vr_ifmedia_upd, vr_ifmedia_sts); 1617 mii_attach(&sc->vr_dev, &sc->vr_mii, 0xffffffff, MII_PHY_ANY, 1618 MII_OFFSET_ANY, 0); 1619 if (LIST_FIRST(&sc->vr_mii.mii_phys) == NULL) { 1620 ifmedia_add(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1621 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE); 1622 } else 1623 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_AUTO); 1624 1625 /* 1626 * Call MI attach routines. 1627 */ 1628 if_attach(ifp); 1629 ether_ifattach(ifp, sc->vr_enaddr); 1630 1631 sc->vr_ats = shutdownhook_establish(vr_shutdown, sc); 1632 if (sc->vr_ats == NULL) 1633 printf("%s: warning: couldn't establish shutdown hook\n", 1634 sc->vr_dev.dv_xname); 1635 return; 1636 1637 fail_5: 1638 for (i = 0; i < VR_NRXDESC; i++) { 1639 if (sc->vr_rxsoft[i].ds_dmamap != NULL) 1640 bus_dmamap_destroy(sc->vr_dmat, 1641 sc->vr_rxsoft[i].ds_dmamap); 1642 } 1643 fail_4: 1644 for (i = 0; i < VR_NTXDESC; i++) { 1645 if (sc->vr_txsoft[i].ds_dmamap != NULL) 1646 bus_dmamap_destroy(sc->vr_dmat, 1647 sc->vr_txsoft[i].ds_dmamap); 1648 } 1649 bus_dmamap_unload(sc->vr_dmat, sc->vr_cddmamap); 1650 fail_3: 1651 bus_dmamap_destroy(sc->vr_dmat, sc->vr_cddmamap); 1652 fail_2: 1653 bus_dmamem_unmap(sc->vr_dmat, (caddr_t)sc->vr_control_data, 1654 sizeof(struct vr_control_data)); 1655 fail_1: 1656 bus_dmamem_free(sc->vr_dmat, &seg, rseg); 1657 fail_0: 1658 return; 1659 } 1660