1 /* $NetBSD: if_xgereg.h,v 1.2 2005/12/11 12:22:50 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2004, SUNET, Swedish University Computer Network. 5 * All rights reserved. 6 * 7 * Written by Anders Magnusson for SUNET, Swedish University Computer Network. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * SUNET, Swedish University Computer Network. 21 * 4. The name of SUNET may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SUNET 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 38 /* 39 * Defines for the S2io Xframe adapter. 40 */ 41 42 /* PCI address space */ 43 #define XGE_PIF_BAR 0x10 44 #define XGE_TXP_BAR 0x18 45 46 /* PIF register address calculation */ 47 #define DCSRB(x) (0x0000+(x)) /* 10GbE Device Control and Status Registers */ 48 #define PCIXB(x) (0x0800+(x)) /* PCI-X Interface Functional Registers */ 49 #define TDMAB(x) (0x1000+(x)) /* Transmit DMA Functional Registers */ 50 #define RDMAB(x) (0x1800+(x)) /* Receive DMA Functional Registers */ 51 #define MACRB(x) (0x2000+(x)) /* MAC functional registers */ 52 #define RLDRB(x) (0x2800+(x)) /* RLDRAM memory controller */ 53 #define XGXSB(x) (0x3000+(x)) /* XGXS functional Registers */ 54 55 /* 56 * Control and Status Registers 57 */ 58 #define GENERAL_INT_STATUS DCSRB(0x0000) 59 #define GENERAL_INT_MASK DCSRB(0x0008) 60 #define SW_RESET DCSRB(0x0100) 61 #define XGXS_RESET(x) ((uint64_t)(x) << 32) 62 #define ADAPTER_STATUS DCSRB(0x0108) 63 #define TDMA_READY (1ULL<<63) 64 #define RDMA_READY (1ULL<<62) 65 #define PFC_READY (1ULL<<61) 66 #define TMAC_BUF_EMPTY (1ULL<<60) 67 #define PIC_QUIESCENT (1ULL<<58) 68 #define RMAC_REMOTE_FAULT (1ULL<<57) 69 #define RMAC_LOCAL_FAULT (1ULL<<56) 70 #define MC_DRAM_READY (1ULL<<39) 71 #define MC_QUEUES_READY (1ULL<<38) 72 #define M_PLL_LOCK (1ULL<<33) 73 #define P_PLL_LOCK (1ULL<<32) 74 #define ADAPTER_CONTROL DCSRB(0x0110) 75 #define ADAPTER_EN (1ULL<<56) 76 #define EOI_TX_ON (1ULL<<48) 77 #define LED_ON (1ULL<<40) 78 #define WAIT_INT_EN (1ULL<<15) 79 #define ECC_ENABLE_N (1ULL<<8) 80 81 /* for debug of ADAPTER_STATUS */ 82 #define QUIESCENT (TDMA_READY|RDMA_READY|PFC_READY|TMAC_BUF_EMPTY|\ 83 PIC_QUIESCENT|MC_DRAM_READY|MC_QUEUES_READY|M_PLL_LOCK|P_PLL_LOCK) 84 #define QUIESCENT_BMSK \ 85 "\177\20b\x3fTDMA_READY\0b\x3eRDMA_READY\0b\x3dPFC_READY\0" \ 86 "b\x3cTMAC_BUF_EMPTY\0b\x3aPIC_QUIESCENT\0\x39RMAC_REMOTE_FAULT\0" \ 87 "b\x38RMAC_LOCAL_FAULT\0b\x27MC_DRAM_READY\0b\x26MC_QUEUES_READY\0" \ 88 "b\x21M_PLL_LOCK\0b\x20P_PLL_LOCK" 89 90 /* 91 * PCI-X registers 92 */ 93 /* Interrupt control registers */ 94 #define PIC_INT_STATUS PCIXB(0) 95 #define PIC_INT_MASK PCIXB(0x008) 96 #define TXPIC_INT_MASK PCIXB(0x018) 97 #define RXPIC_INT_MASK PCIXB(0x030) 98 #define FLASH_INT_MASK PCIXB(0x048) 99 #define MDIO_INT_MASK PCIXB(0x060) 100 #define IIC_INT_MASK PCIXB(0x078) 101 #define GPIO_INT_MASK PCIXB(0x098) 102 #define TX_TRAFFIC_INT PCIXB(0x0e0) 103 #define TX_TRAFFIC_MASK PCIXB(0x0e8) 104 #define RX_TRAFFIC_INT PCIXB(0x0f0) 105 #define RX_TRAFFIC_MASK PCIXB(0x0f8) 106 #define PIC_CONTROL PCIXB(0x100) 107 108 /* Byte swapping for little-endian */ 109 #define SWAPPER_CTRL PCIXB(0x108) 110 #define PIF_R_FE (1ULL<<63) 111 #define PIF_R_SE (1ULL<<62) 112 #define PIF_W_FE (1ULL<<55) 113 #define PIF_W_SE (1ULL<<54) 114 #define TxP_FE (1ULL<<47) 115 #define TxP_SE (1ULL<<46) 116 #define TxD_R_FE (1ULL<<45) 117 #define TxD_R_SE (1ULL<<44) 118 #define TxD_W_FE (1ULL<<43) 119 #define TxD_W_SE (1ULL<<42) 120 #define TxF_R_FE (1ULL<<41) 121 #define TxF_R_SE (1ULL<<40) 122 #define RxD_R_FE (1ULL<<31) 123 #define RxD_R_SE (1ULL<<30) 124 #define RxD_W_FE (1ULL<<29) 125 #define RxD_W_SE (1ULL<<28) 126 #define RxF_W_FE (1ULL<<27) 127 #define RxF_W_SE (1ULL<<26) 128 #define XMSI_FE (1ULL<<23) 129 #define XMSI_SE (1ULL<<22) 130 #define STATS_FE (1ULL<<15) 131 #define STATS_SE (1ULL<<14) 132 133 /* Diagnostic register to check byte-swapping conf */ 134 #define PIF_RD_SWAPPER_Fb PCIXB(0x110) 135 #define SWAPPER_MAGIC 0x0123456789abcdefULL 136 137 /* Stats registers */ 138 #define STAT_CFG PCIXB(0x1d0) 139 #define STAT_ADDR PCIXB(0x1d8) 140 141 /* DTE-XGXS Interface */ 142 #define MDIO_CONTROL PCIXB(0x1e0) 143 #define DTX_CONTROL PCIXB(0x1e8) 144 #define I2C_CONTROL PCIXB(0x1f0) 145 #define GPIO_CONTROL PCIXB(0x1f8) 146 147 /* 148 * Transmit DMA registers. 149 */ 150 #define TXDMA_INT_MASK TDMAB(0x008) 151 #define PFC_ERR_MASK TDMAB(0x018) 152 #define TDA_ERR_MASK TDMAB(0x030) 153 #define PCC_ERR_MASK TDMAB(0x048) 154 #define TTI_ERR_MASK TDMAB(0x060) 155 #define LSO_ERR_MASK TDMAB(0x078) 156 #define TPA_ERR_MASK TDMAB(0x090) 157 #define SM_ERR_MASK TDMAB(0x0a8) 158 159 /* Transmit FIFO config */ 160 #define TX_FIFO_P0 TDMAB(0x0108) 161 #define TX_FIFO_P1 TDMAB(0x0110) 162 #define TX_FIFO_P2 TDMAB(0x0118) 163 #define TX_FIFO_P3 TDMAB(0x0120) 164 #define TX_FIFO_ENABLE (1ULL<<63) 165 #define TX_FIFO_NUM0(x) ((uint64_t)(x) << 56) 166 #define TX_FIFO_LEN0(x) ((uint64_t)((x)-1) << 32) 167 #define TX_FIFO_NUM1(x) ((uint64_t)(x) << 24) 168 #define TX_FIFO_LEN1(x) ((uint64_t)((x)-1) << 0) 169 170 /* Transmit interrupts */ 171 #define TTI_COMMAND_MEM TDMAB(0x150) 172 #define TTI_CMD_MEM_WE (1ULL<<56) 173 #define TTI_CMD_MEM_STROBE (1ULL<<48) 174 #define TTI_DATA1_MEM TDMAB(0x158) 175 #define TX_TIMER_VAL(x) ((uint64_t)(x) << 32) 176 #define TX_TIMER_AC (1ULL<<25) 177 #define TX_TIMER_CI (1ULL<<24) 178 #define TX_URNG_A(x) ((uint64_t)(x) << 16) 179 #define TX_URNG_B(x) ((uint64_t)(x) << 8) 180 #define TX_URNG_C(x) ((uint64_t)(x) << 0) 181 #define TTI_DATA2_MEM TDMAB(0x160) 182 #define TX_UFC_A(x) ((uint64_t)(x) << 48) 183 #define TX_UFC_B(x) ((uint64_t)(x) << 32) 184 #define TX_UFC_C(x) ((uint64_t)(x) << 16) 185 #define TX_UFC_D(x) ((uint64_t)(x) << 0) 186 187 188 /* Transmit protocol assist */ 189 #define TX_PA_CFG TDMAB(0x0168) 190 #define TX_PA_CFG_IFR (1ULL<<62) /* Ignore frame error */ 191 #define TX_PA_CFG_ISO (1ULL<<61) /* Ignore snap OUI */ 192 #define TX_PA_CFG_ILC (1ULL<<60) /* Ignore LLC ctrl */ 193 #define TX_PA_CFG_ILE (1ULL<<57) /* Ignore L2 error */ 194 195 /* 196 * Transmit descriptor list (TxDL) pointer and control. 197 * There may be up to 8192 TxDL's per FIFO, but with a NIC total 198 * of 8192. The TxDL's are located in the NIC memory. 199 * Each TxDL can have up to 256 Transmit descriptors (TxD) 200 * that are located in host memory. 201 * 202 * The txdl struct fields must be written in order. 203 */ 204 #ifdef notdef /* Use bus_space stuff instead */ 205 struct txdl { 206 uint64_t txdl_pointer; /* address of TxD's */ 207 uint64_t txdl_control; 208 }; 209 #endif 210 #define TXDLOFF1(x) (16*(x)) /* byte offset in txdl for list */ 211 #define TXDLOFF2(x) (16*(x)+8) /* byte offset in txdl for list */ 212 #define TXDL_NUMTXD(x) ((uint64_t)(x) << 56) /* # of TxD's in the list */ 213 #define TXDL_LGC_FIRST (1ULL << 49) /* First special list */ 214 #define TXDL_LGC_LAST (1ULL << 48) /* Last special list */ 215 #define TXDL_SFF (1ULL << 40) /* List is a special function list */ 216 #define TXDL_PAR 0 /* Pointer address register */ 217 #define TXDL_LCR 8 /* List control register */ 218 219 struct txd { 220 uint64_t txd_control1; 221 uint64_t txd_control2; 222 uint64_t txd_bufaddr; 223 uint64_t txd_hostctrl; 224 }; 225 #define TXD_CTL1_OWN (1ULL << 56) /* Owner, 0 == host, 1 == NIC */ 226 #define TXD_CTL1_GCF (1ULL << 41) /* First frame or LSO */ 227 #define TXD_CTL1_GCL (1ULL << 40) /* Last frame or LSO */ 228 #define TXD_CTL1_LSO (1ULL << 33) /* LSO should be performed */ 229 #define TXD_CTL1_COF (1ULL << 32) /* UDP Checksum over fragments */ 230 #define TXD_CTL1_MSS(x) ((uint64_t)(x) << 16) 231 232 #define TXD_CTL2_INTLST (1ULL << 16) /* Per-list interrupt */ 233 #define TXD_CTL2_UTIL (1ULL << 17) /* Utilization interrupt */ 234 #define TXD_CTL2_CIPv4 (1ULL << 58) /* Calculate IPv4 header checksum */ 235 #define TXD_CTL2_CTCP (1ULL << 57) /* Calculate TCP checksum */ 236 #define TXD_CTL2_CUDP (1ULL << 56) /* Calculate UDP checksum */ 237 /* 238 * Receive DMA registers 239 */ 240 /* Receive interrupt registers */ 241 #define RXDMA_INT_MASK RDMAB(0x008) 242 #define RDA_ERR_MASK RDMAB(0x018) 243 #define RC_ERR_MASK RDMAB(0x030) 244 #define PRC_PCIX_ERR_MASK RDMAB(0x048) 245 #define RPA_ERR_MASK RDMAB(0x060) 246 #define RTI_ERR_MASK RDMAB(0x078) 247 248 #define RX_QUEUE_PRIORITY RDMAB(0x100) 249 #define RX_W_ROUND_ROBIN_0 RDMAB(0x108) 250 #define RX_W_ROUND_ROBIN_1 RDMAB(0x110) 251 #define RX_W_ROUND_ROBIN_2 RDMAB(0x118) 252 #define RX_W_ROUND_ROBIN_3 RDMAB(0x120) 253 #define RX_W_ROUND_ROBIN_4 RDMAB(0x128) 254 #define PRC_RXD0_0 RDMAB(0x130) 255 #define PRC_CTRL_0 RDMAB(0x170) 256 #define RC_IN_SVC (1ULL << 56) 257 #define RING_MODE_1 (0ULL << 48) 258 #define RING_MODE_3 (1ULL << 48) 259 #define RING_MODE_5 (2ULL << 48) 260 #define RC_NO_SNOOP_D (1ULL << 41) 261 #define RC_NO_SNOOP_B (1ULL << 40) 262 #define PRC_ALARM_ACTION RDMAB(0x1b0) 263 #define RTI_COMMAND_MEM RDMAB(0x1b8) 264 #define RTI_CMD_MEM_WE (1ULL << 56) 265 #define RTI_CMD_MEM_STROBE (1ULL << 48) 266 #define RTI_DATA1_MEM RDMAB(0x1c0) 267 #define RX_TIMER_VAL(x) ((uint64_t)(x) << 32) 268 #define RX_TIMER_AC (1ULL << 25) 269 #define RX_URNG_A(x) ((uint64_t)(x) << 16) 270 #define RX_URNG_B(x) ((uint64_t)(x) << 8) 271 #define RX_URNG_C(x) ((uint64_t)(x) << 0) 272 #define RTI_DATA2_MEM RDMAB(0x1c8) 273 #define RX_UFC_A(x) ((uint64_t)(x) << 48) 274 #define RX_UFC_B(x) ((uint64_t)(x) << 32) 275 #define RX_UFC_C(x) ((uint64_t)(x) << 16) 276 #define RX_UFC_D(x) ((uint64_t)(x) << 0) 277 #define RX_PA_CFG RDMAB(0x1d0) 278 /* 279 * Receive descriptor (RxD) format. 280 * There are three formats of receive descriptors, 1, 3 and 5 buffer format. 281 */ 282 #define RX_MODE_1 1 283 #define RX_MODE_3 3 284 #define RX_MODE_5 5 285 286 struct rxd1 { 287 uint64_t rxd_hcontrol; 288 uint64_t rxd_control1; 289 uint64_t rxd_control2; 290 uint64_t rxd_buf0; 291 }; 292 293 /* 4k struct for 5 buffer mode */ 294 #define NDESC_1BUFMODE 127 /* # desc/page for 5-buffer mode */ 295 struct rxd1_4k { 296 struct rxd1 r4_rxd[NDESC_1BUFMODE]; 297 uint64_t pad[3]; 298 uint64_t r4_next; /* phys address of next 4k buffer */ 299 }; 300 301 struct rxd3 { 302 uint64_t rxd_hcontrol; 303 uint64_t rxd_control1; 304 uint64_t rxd_control2; 305 uint64_t rxd_buf0; 306 uint64_t rxd_buf1; 307 uint64_t rxd_buf2; 308 }; 309 310 struct rxd5 { 311 uint64_t rxd_control3; 312 uint64_t rxd_control1; 313 uint64_t rxd_control2; 314 uint64_t rxd_buf0; 315 uint64_t rxd_buf1; 316 uint64_t rxd_buf2; 317 uint64_t rxd_buf3; 318 uint64_t rxd_buf4; 319 }; 320 321 /* 4k struct for 5 buffer mode */ 322 #define NDESC_5BUFMODE 63 /* # desc/page for 5-buffer mode */ 323 #define XGE_PAGE 4096 /* page size used for receive */ 324 struct rxd5_4k { 325 struct rxd5 r4_rxd[NDESC_5BUFMODE]; 326 uint64_t pad[7]; 327 uint64_t r4_next; /* phys address of next 4k buffer */ 328 }; 329 330 #define RXD_MKCTL3(h,bs3,bs4) \ 331 (((uint64_t)(h) << 32) | ((uint64_t)(bs3) << 16) | (uint64_t)(bs4)) 332 #define RXD_MKCTL2(bs0,bs1,bs2) \ 333 (((uint64_t)(bs0) << 48) | ((uint64_t)(bs1) << 32) | \ 334 ((uint64_t)(bs2) << 16)) 335 336 #define RXD_CTL2_BUF0SIZ(x) (((x) >> 48) & 0xffff) 337 #define RXD_CTL2_BUF1SIZ(x) (((x) >> 32) & 0xffff) 338 #define RXD_CTL2_BUF2SIZ(x) (((x) >> 16) & 0xffff) 339 #define RXD_CTL3_BUF3SIZ(x) (((x) >> 16) & 0xffff) 340 #define RXD_CTL3_BUF4SIZ(x) ((x) & 0xffff) 341 #define RXD_CTL1_OWN (1ULL << 56) 342 #define RXD_CTL1_XCODE(x) (((x) >> 48) & 0xf) /* Status bits */ 343 #define RXD_CTL1_X_OK 0 344 #define RXD_CTL1_X_PERR 1 /* Parity error */ 345 #define RXD_CTL1_X_ABORT 2 /* Abort during xfer */ 346 #define RXD_CTL1_X_PA 3 /* Parity error and abort */ 347 #define RXD_CTL1_X_RDA 4 /* RDA failure */ 348 #define RXD_CTL1_X_UP 5 /* Unknown protocol */ 349 #define RXD_CTL1_X_FI 6 /* Frame integrity (FCS) error */ 350 #define RXD_CTL1_X_BSZ 7 /* Buffer size error */ 351 #define RXD_CTL1_X_ECC 8 /* Internal ECC */ 352 #define RXD_CTL1_X_UNK 15 /* Unknown error */ 353 #define RXD_CTL1_PROTOS(x) (((x) >> 32) & 0xff) 354 #define RXD_CTL1_P_VLAN 0x80 /* VLAN tagged */ 355 #define RXD_CTL1_P_MSK 0x60 /* Mask for frame type */ 356 #define RXD_CTL1_P_DIX 0x00 357 #define RXD_CTL1_P_LLC 0x20 358 #define RXD_CTL1_P_SNAP 0x40 359 #define RXD_CTL1_P_IPX 0x60 360 #define RXD_CTL1_P_IPv4 0x10 361 #define RXD_CTL1_P_IPv6 0x08 362 #define RXD_CTL1_P_IPFRAG 0x04 363 #define RXD_CTL1_P_TCP 0x02 364 #define RXD_CTL1_P_UDP 0x01 365 #define RXD_CTL1_L3CSUM(x) (((x) >> 16) & 0xffff) 366 #define RXD_CTL1_L4CSUM(x) ((x) & 0xffff) 367 #define RXD_CTL2_VLANTAG(x) ((x) & 0xffff) 368 369 /* 370 * MAC Configuration/Status 371 */ 372 #define MAC_INT_STATUS MACRB(0x000) 373 #define MAC_TMAC_INT (1ULL<<63) 374 #define MAC_RMAC_INT (1ULL<<62) 375 #define MAC_INT_MASK MACRB(0x008) 376 #define MAC_TMAC_ERR_MASK MACRB(0x018) 377 #define MAC_RMAC_ERR_REG MACRB(0x028) 378 #define RMAC_LINK_STATE_CHANGE_INT (1ULL<<32) 379 #define MAC_RMAC_ERR_MASK MACRB(0x030) 380 381 #define MAC_CFG MACRB(0x0100) 382 #define TMAC_EN (1ULL<<63) 383 #define RMAC_EN (1ULL<<62) 384 #define UTILZATION_CALC_SEL (1ULL<<61) 385 #define TMAC_LOOPBACK (1ULL<<60) 386 #define TMAC_APPEND_PAD (1ULL<<59) 387 #define RMAC_STRIP_FCS (1ULL<<58) 388 #define RMAC_STRIP_PAD (1ULL<<57) 389 #define RMAC_PROM_EN (1ULL<<56) 390 #define RMAC_DISCARD_PFRM (1ULL<<55) 391 #define RMAC_BCAST_EN (1ULL<<54) 392 #define RMAC_ALL_ADDR_EN (1ULL<<53) 393 #define RMAC_MAX_PYLD_LEN MACRB(0x0110) 394 #define RMAC_PYLD_LEN(x) ((uint64_t)(x) << 48) 395 #define RMAC_CFG_KEY MACRB(0x0120) 396 #define RMAC_KEY_VALUE (0x4c0dULL<<48) 397 #define RMAC_ADDR_CMD_MEM MACRB(0x0128) 398 #define RMAC_ADDR_CMD_MEM_WE (1ULL<<56) 399 #define RMAC_ADDR_CMD_MEM_STR (1ULL<<48) 400 #define RMAC_ADDR_CMD_MEM_OFF(x) ((uint64_t)(x) << 32) 401 #define MAX_MCAST_ADDR 64 /* slots in mcast table */ 402 #define RMAC_ADDR_DATA0_MEM MACRB(0x0130) 403 #define RMAC_ADDR_DATA1_MEM MACRB(0x0138) 404 #define RMAC_PAUSE_CFG MACRB(0x150) 405 #define RMAC_PAUSE_GEN_EN (1ULL<<63) 406 #define RMAC_PAUSE_RCV_EN (1ULL<<62) 407 408 /* 409 * RLDRAM registers. 410 */ 411 #define MC_INT_MASK RLDRB(0x008) 412 #define MC_ERR_MASK RLDRB(0x018) 413 414 #define RX_QUEUE_CFG RLDRB(0x100) 415 #define MC_QUEUE(q,s) ((uint64_t)(s)<<(56-(q*8))) 416 #define MC_RLDRAM_MRS RLDRB(0x108) 417 #define MC_QUEUE_SIZE_ENABLE (1ULL<<24) 418 #define MC_RLDRAM_MRS_ENABLE (1ULL<<16) 419 420 /* 421 * XGXS registers. 422 */ 423 /* XGXS control/statue */ 424 #define XGXS_INT_MASK XGXSB(0x008) 425 #define XGXS_TXGXS_ERR_MASK XGXSB(0x018) 426 #define XGXS_RXGXS_ERR_MASK XGXSB(0x030) 427 #define XGXS_CFG XGXSB(0x0100) 428