1 /* $NetBSD: isp_pci.c,v 1.87 2002/11/25 02:16:50 thorpej Exp $ */ 2 /* 3 * This driver, which is contained in NetBSD in the files: 4 * 5 * sys/dev/ic/isp.c 6 * sys/dev/ic/isp_inline.h 7 * sys/dev/ic/isp_netbsd.c 8 * sys/dev/ic/isp_netbsd.h 9 * sys/dev/ic/isp_target.c 10 * sys/dev/ic/isp_target.h 11 * sys/dev/ic/isp_tpublic.h 12 * sys/dev/ic/ispmbox.h 13 * sys/dev/ic/ispreg.h 14 * sys/dev/ic/ispvar.h 15 * sys/microcode/isp/asm_sbus.h 16 * sys/microcode/isp/asm_1040.h 17 * sys/microcode/isp/asm_1080.h 18 * sys/microcode/isp/asm_12160.h 19 * sys/microcode/isp/asm_2100.h 20 * sys/microcode/isp/asm_2200.h 21 * sys/pci/isp_pci.c 22 * sys/sbus/isp_sbus.c 23 * 24 * Is being actively maintained by Matthew Jacob (mjacob@netbsd.org). 25 * This driver also is shared source with FreeBSD, OpenBSD, Linux, Solaris, 26 * Linux versions. This tends to be an interesting maintenance problem. 27 * 28 * Please coordinate with Matthew Jacob on changes you wish to make here. 29 */ 30 /* 31 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 32 */ 33 /* 34 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 35 * All rights reserved. 36 * 37 * Additional Copyright (C) 2000, 2001 by Matthew Jacob 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: isp_pci.c,v 1.87 2002/11/25 02:16:50 thorpej Exp $"); 61 62 #include <dev/ic/isp_netbsd.h> 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcidevs.h> 66 #include <uvm/uvm_extern.h> 67 #include <sys/reboot.h> 68 69 static u_int16_t isp_pci_rd_reg(struct ispsoftc *, int); 70 static void isp_pci_wr_reg(struct ispsoftc *, int, u_int16_t); 71 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 72 static u_int16_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 73 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, u_int16_t); 74 #endif 75 static int 76 isp_pci_rd_isr(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 77 static int 78 isp_pci_rd_isr_2300(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 79 static int isp_pci_mbxdma(struct ispsoftc *); 80 static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *, 81 u_int16_t *, u_int16_t); 82 static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, u_int16_t); 83 static void isp_pci_reset1(struct ispsoftc *); 84 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 85 static int isp_pci_intr(void *); 86 87 #if defined(ISP_DISABLE_1020_SUPPORT) 88 #define ISP_1040_RISC_CODE NULL 89 #else 90 #define ISP_1040_RISC_CODE (u_int16_t *) isp_1040_risc_code 91 #include <dev/microcode/isp/asm_1040.h> 92 #endif 93 94 #if defined(ISP_DISABLE_1080_SUPPORT) 95 #define ISP_1080_RISC_CODE NULL 96 #else 97 #define ISP_1080_RISC_CODE (u_int16_t *) isp_1080_risc_code 98 #include <dev/microcode/isp/asm_1080.h> 99 #endif 100 101 #if defined(ISP_DISABLE_12160_SUPPORT) 102 #define ISP_12160_RISC_CODE NULL 103 #else 104 #define ISP_12160_RISC_CODE (u_int16_t *) isp_12160_risc_code 105 #include <dev/microcode/isp/asm_12160.h> 106 #endif 107 108 #if defined(ISP_DISABLE_2100_SUPPORT) 109 #define ISP_2100_RISC_CODE NULL 110 #else 111 #define ISP_2100_RISC_CODE (u_int16_t *) isp_2100_risc_code 112 #include <dev/microcode/isp/asm_2100.h> 113 #endif 114 115 #if defined(ISP_DISABLE_2200_SUPPORT) 116 #define ISP_2200_RISC_CODE NULL 117 #else 118 #define ISP_2200_RISC_CODE (u_int16_t *) isp_2200_risc_code 119 #include <dev/microcode/isp/asm_2200.h> 120 #endif 121 122 #if defined(ISP_DISABLE_2300_SUPPORT) 123 #define ISP_2300_RISC_CODE NULL 124 #else 125 #define ISP_2300_RISC_CODE (u_int16_t *) isp_2300_risc_code 126 #include <dev/microcode/isp/asm_2300.h> 127 #endif 128 129 #ifndef ISP_DISABLE_1020_SUPPORT 130 static struct ispmdvec mdvec = { 131 isp_pci_rd_isr, 132 isp_pci_rd_reg, 133 isp_pci_wr_reg, 134 isp_pci_mbxdma, 135 isp_pci_dmasetup, 136 isp_pci_dmateardown, 137 NULL, 138 isp_pci_reset1, 139 isp_pci_dumpregs, 140 ISP_1040_RISC_CODE, 141 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 142 }; 143 #endif 144 145 #ifndef ISP_DISABLE_1080_SUPPORT 146 static struct ispmdvec mdvec_1080 = { 147 isp_pci_rd_isr, 148 isp_pci_rd_reg_1080, 149 isp_pci_wr_reg_1080, 150 isp_pci_mbxdma, 151 isp_pci_dmasetup, 152 isp_pci_dmateardown, 153 NULL, 154 isp_pci_reset1, 155 isp_pci_dumpregs, 156 ISP_1080_RISC_CODE, 157 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 158 }; 159 #endif 160 161 #ifndef ISP_DISABLE_12160_SUPPORT 162 static struct ispmdvec mdvec_12160 = { 163 isp_pci_rd_isr, 164 isp_pci_rd_reg_1080, 165 isp_pci_wr_reg_1080, 166 isp_pci_mbxdma, 167 isp_pci_dmasetup, 168 isp_pci_dmateardown, 169 NULL, 170 isp_pci_reset1, 171 isp_pci_dumpregs, 172 ISP_12160_RISC_CODE, 173 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 174 }; 175 #endif 176 177 #ifndef ISP_DISABLE_2100_SUPPORT 178 static struct ispmdvec mdvec_2100 = { 179 isp_pci_rd_isr, 180 isp_pci_rd_reg, 181 isp_pci_wr_reg, 182 isp_pci_mbxdma, 183 isp_pci_dmasetup, 184 isp_pci_dmateardown, 185 NULL, 186 isp_pci_reset1, 187 isp_pci_dumpregs, 188 ISP_2100_RISC_CODE 189 }; 190 #endif 191 192 #ifndef ISP_DISABLE_2200_SUPPORT 193 static struct ispmdvec mdvec_2200 = { 194 isp_pci_rd_isr, 195 isp_pci_rd_reg, 196 isp_pci_wr_reg, 197 isp_pci_mbxdma, 198 isp_pci_dmasetup, 199 isp_pci_dmateardown, 200 NULL, 201 isp_pci_reset1, 202 isp_pci_dumpregs, 203 ISP_2200_RISC_CODE 204 }; 205 #endif 206 207 #ifndef ISP_DISABLE_2300_SUPPORT 208 static struct ispmdvec mdvec_2300 = { 209 isp_pci_rd_isr_2300, 210 isp_pci_rd_reg, 211 isp_pci_wr_reg, 212 isp_pci_mbxdma, 213 isp_pci_dmasetup, 214 isp_pci_dmateardown, 215 NULL, 216 isp_pci_reset1, 217 isp_pci_dumpregs, 218 ISP_2300_RISC_CODE 219 }; 220 #endif 221 222 #ifndef PCI_VENDOR_QLOGIC 223 #define PCI_VENDOR_QLOGIC 0x1077 224 #endif 225 226 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 227 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 228 #endif 229 230 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 231 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 232 #endif 233 234 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 235 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 236 #endif 237 238 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 239 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 240 #endif 241 242 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 243 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 244 #endif 245 246 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 247 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 248 #endif 249 250 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 251 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 252 #endif 253 254 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 255 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 256 #endif 257 258 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 259 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 260 #endif 261 262 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 263 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 264 #endif 265 266 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 267 268 #define PCI_QLOGIC_ISP1080 \ 269 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 270 271 #define PCI_QLOGIC_ISP1240 \ 272 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 273 274 #define PCI_QLOGIC_ISP1280 \ 275 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 276 277 #define PCI_QLOGIC_ISP10160 \ 278 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 279 280 #define PCI_QLOGIC_ISP12160 \ 281 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 282 283 #define PCI_QLOGIC_ISP2100 \ 284 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 285 286 #define PCI_QLOGIC_ISP2200 \ 287 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 288 289 #define PCI_QLOGIC_ISP2300 \ 290 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 291 292 #define PCI_QLOGIC_ISP2312 \ 293 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 294 295 #define IO_MAP_REG 0x10 296 #define MEM_MAP_REG 0x14 297 #define PCIR_ROMADDR 0x30 298 299 #define PCI_DFLT_LTNCY 0x40 300 #define PCI_DFLT_LNSZ 0x10 301 302 303 static int isp_pci_probe(struct device *, struct cfdata *, void *); 304 static void isp_pci_attach(struct device *, struct device *, void *); 305 306 struct isp_pcisoftc { 307 struct ispsoftc pci_isp; 308 pci_chipset_tag_t pci_pc; 309 pcitag_t pci_tag; 310 bus_space_tag_t pci_st; 311 bus_space_handle_t pci_sh; 312 bus_dmamap_t *pci_xfer_dmap; 313 void * pci_ih; 314 int16_t pci_poff[_NREG_BLKS]; 315 }; 316 317 CFATTACH_DECL(isp_pci, sizeof (struct isp_pcisoftc), 318 isp_pci_probe, isp_pci_attach, NULL, NULL); 319 320 #ifdef DEBUG 321 const char vstring[] = 322 "Qlogic ISP Driver, NetBSD (pci) Platform Version %d.%d Core Version %d.%d"; 323 #endif 324 325 static int 326 isp_pci_probe(struct device *parent, struct cfdata *match, void *aux) 327 { 328 struct pci_attach_args *pa = aux; 329 switch (pa->pa_id) { 330 #ifndef ISP_DISABLE_1020_SUPPORT 331 case PCI_QLOGIC_ISP: 332 return (1); 333 #endif 334 #ifndef ISP_DISABLE_1080_SUPPORT 335 case PCI_QLOGIC_ISP1080: 336 case PCI_QLOGIC_ISP1240: 337 case PCI_QLOGIC_ISP1280: 338 return (1); 339 #endif 340 #ifndef ISP_DISABLE_12160_SUPPORT 341 case PCI_QLOGIC_ISP10160: 342 case PCI_QLOGIC_ISP12160: 343 return (1); 344 #endif 345 #ifndef ISP_DISABLE_2100_SUPPORT 346 case PCI_QLOGIC_ISP2100: 347 return (1); 348 #endif 349 #ifndef ISP_DISABLE_2200_SUPPORT 350 case PCI_QLOGIC_ISP2200: 351 return (1); 352 #endif 353 #ifndef ISP_DISABLE_2300_SUPPORT 354 case PCI_QLOGIC_ISP2300: 355 case PCI_QLOGIC_ISP2312: 356 return (1); 357 #endif 358 default: 359 return (0); 360 } 361 } 362 363 364 static void 365 isp_pci_attach(struct device *parent, struct device *self, void *aux) 366 { 367 #ifdef DEBUG 368 static char oneshot = 1; 369 #endif 370 static const char nomem[] = "\n%s: no mem for sdparam table\n"; 371 u_int32_t data, rev, linesz = PCI_DFLT_LNSZ; 372 struct pci_attach_args *pa = aux; 373 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self; 374 struct ispsoftc *isp = &pcs->pci_isp; 375 bus_space_tag_t st, iot, memt; 376 bus_space_handle_t sh, ioh, memh; 377 pci_intr_handle_t ih; 378 char *dstring; 379 const char *intrstr; 380 int ioh_valid, memh_valid; 381 382 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 383 PCI_MAPREG_TYPE_IO, 0, 384 &iot, &ioh, NULL, NULL) == 0); 385 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, 386 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 387 &memt, &memh, NULL, NULL) == 0); 388 if (memh_valid) { 389 st = memt; 390 sh = memh; 391 } else if (ioh_valid) { 392 st = iot; 393 sh = ioh; 394 } else { 395 printf(": unable to map device registers\n"); 396 return; 397 } 398 dstring = "\n"; 399 400 pcs->pci_st = st; 401 pcs->pci_sh = sh; 402 pcs->pci_pc = pa->pa_pc; 403 pcs->pci_tag = pa->pa_tag; 404 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 405 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 406 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 407 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 408 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 409 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff; 410 411 #ifndef ISP_DISABLE_1020_SUPPORT 412 if (pa->pa_id == PCI_QLOGIC_ISP) { 413 dstring = ": QLogic 1020 Ultra Wide SCSI HBA\n"; 414 isp->isp_mdvec = &mdvec; 415 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 416 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 417 if (isp->isp_param == NULL) { 418 printf(nomem, isp->isp_name); 419 return; 420 } 421 memset(isp->isp_param, 0, sizeof (sdparam)); 422 } 423 #endif 424 #ifndef ISP_DISABLE_1080_SUPPORT 425 if (pa->pa_id == PCI_QLOGIC_ISP1080) { 426 dstring = ": QLogic 1080 Ultra-2 Wide SCSI HBA\n"; 427 isp->isp_mdvec = &mdvec_1080; 428 isp->isp_type = ISP_HA_SCSI_1080; 429 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 430 if (isp->isp_param == NULL) { 431 printf(nomem, isp->isp_name); 432 return; 433 } 434 memset(isp->isp_param, 0, sizeof (sdparam)); 435 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 436 ISP1080_DMA_REGS_OFF; 437 } 438 if (pa->pa_id == PCI_QLOGIC_ISP1240) { 439 dstring = ": QLogic Dual Channel Ultra Wide SCSI HBA\n"; 440 isp->isp_mdvec = &mdvec_1080; 441 isp->isp_type = ISP_HA_SCSI_1240; 442 isp->isp_param = 443 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 444 if (isp->isp_param == NULL) { 445 printf(nomem, isp->isp_name); 446 return; 447 } 448 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 449 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 450 ISP1080_DMA_REGS_OFF; 451 } 452 if (pa->pa_id == PCI_QLOGIC_ISP1280) { 453 dstring = ": QLogic Dual Channel Ultra-2 Wide SCSI HBA\n"; 454 isp->isp_mdvec = &mdvec_1080; 455 isp->isp_type = ISP_HA_SCSI_1280; 456 isp->isp_param = 457 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 458 if (isp->isp_param == NULL) { 459 printf(nomem, isp->isp_name); 460 return; 461 } 462 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 463 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 464 ISP1080_DMA_REGS_OFF; 465 } 466 #endif 467 #ifndef ISP_DISABLE_12160_SUPPORT 468 if (pa->pa_id == PCI_QLOGIC_ISP10160) { 469 dstring = ": QLogic Ultra-3 Wide SCSI HBA\n"; 470 isp->isp_mdvec = &mdvec_12160; 471 isp->isp_type = ISP_HA_SCSI_10160; 472 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 473 if (isp->isp_param == NULL) { 474 printf(nomem, isp->isp_name); 475 return; 476 } 477 memset(isp->isp_param, 0, sizeof (sdparam)); 478 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 479 ISP1080_DMA_REGS_OFF; 480 } 481 if (pa->pa_id == PCI_QLOGIC_ISP12160) { 482 dstring = ": QLogic Dual Channel Ultra-3 Wide SCSI HBA\n"; 483 isp->isp_mdvec = &mdvec_12160; 484 isp->isp_type = ISP_HA_SCSI_12160; 485 isp->isp_param = 486 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 487 if (isp->isp_param == NULL) { 488 printf(nomem, isp->isp_name); 489 return; 490 } 491 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 492 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 493 ISP1080_DMA_REGS_OFF; 494 } 495 #endif 496 #ifndef ISP_DISABLE_2100_SUPPORT 497 if (pa->pa_id == PCI_QLOGIC_ISP2100) { 498 dstring = ": QLogic FC-AL HBA\n"; 499 isp->isp_mdvec = &mdvec_2100; 500 isp->isp_type = ISP_HA_FC_2100; 501 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 502 if (isp->isp_param == NULL) { 503 printf(nomem, isp->isp_name); 504 return; 505 } 506 memset(isp->isp_param, 0, sizeof (fcparam)); 507 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 508 PCI_MBOX_REGS2100_OFF; 509 if (rev < 3) { 510 /* 511 * XXX: Need to get the actual revision 512 * XXX: number of the 2100 FB. At any rate, 513 * XXX: lower cache line size for early revision 514 * XXX; boards. 515 */ 516 linesz = 1; 517 } 518 } 519 #endif 520 #ifndef ISP_DISABLE_2200_SUPPORT 521 if (pa->pa_id == PCI_QLOGIC_ISP2200) { 522 dstring = ": QLogic FC-AL and Fabric HBA\n"; 523 isp->isp_mdvec = &mdvec_2200; 524 isp->isp_type = ISP_HA_FC_2200; 525 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 526 if (isp->isp_param == NULL) { 527 printf(nomem, isp->isp_name); 528 return; 529 } 530 memset(isp->isp_param, 0, sizeof (fcparam)); 531 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 532 PCI_MBOX_REGS2100_OFF; 533 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 534 } 535 #endif 536 #ifndef ISP_DISABLE_2300_SUPPORT 537 if (pa->pa_id == PCI_QLOGIC_ISP2300 || 538 pa->pa_id == PCI_QLOGIC_ISP2312) { 539 isp->isp_mdvec = &mdvec_2300; 540 if (pa->pa_id == PCI_QLOGIC_ISP2300) { 541 dstring = ": QLogic FC-AL and 2Gbps Fabric HBA\n"; 542 isp->isp_type = ISP_HA_FC_2300; 543 } else { 544 dstring = 545 ": QLogic Dual Port FC-AL and 2Gbps Fabric HBA\n"; 546 isp->isp_type = ISP_HA_FC_2312; 547 isp->isp_port = pa->pa_function; 548 } 549 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 550 if (isp->isp_param == NULL) { 551 printf(nomem, isp->isp_name); 552 return; 553 } 554 memset(isp->isp_param, 0, sizeof (fcparam)); 555 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 556 PCI_MBOX_REGS2300_OFF; 557 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 558 } 559 #endif 560 /* 561 * Set up logging levels. 562 */ 563 #ifdef ISP_LOGDEFAULT 564 isp->isp_dblev = ISP_LOGDEFAULT; 565 #else 566 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 567 if (bootverbose) 568 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 569 #ifdef SCSIDEBUG 570 isp->isp_dblev |= ISP_LOGDEBUG0|ISP_LOGDEBUG1|ISP_LOGDEBUG2; 571 #endif 572 #endif 573 if (isp->isp_dblev & ISP_LOGCONFIG) { 574 printf("\n"); 575 } else { 576 printf(dstring); 577 } 578 579 #ifdef DEBUG 580 if (oneshot) { 581 oneshot = 0; 582 isp_prt(isp, ISP_LOGCONFIG, vstring, 583 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 584 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 585 } 586 #endif 587 588 isp->isp_dmatag = pa->pa_dmat; 589 isp->isp_revision = rev; 590 591 /* 592 * Make sure that command register set sanely. 593 */ 594 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 595 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 596 597 /* 598 * Not so sure about these- but I think it's important that they get 599 * enabled...... 600 */ 601 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 602 if (IS_2300(isp)) { /* per QLogic errata */ 603 data &= ~PCI_COMMAND_INVALIDATE_ENABLE; 604 } 605 if (IS_23XX(isp)) { 606 isp->isp_touched = 1; 607 } 608 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 609 610 /* 611 * Make sure that the latency timer, cache line size, 612 * and ROM is disabled. 613 */ 614 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 615 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 616 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 617 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT); 618 data |= (linesz << PCI_CACHELINE_SHIFT); 619 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data); 620 621 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR); 622 data &= ~1; 623 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data); 624 625 if (pci_intr_map(pa, &ih)) { 626 printf("%s: couldn't map interrupt\n", isp->isp_name); 627 free(isp->isp_param, M_DEVBUF); 628 return; 629 } 630 intrstr = pci_intr_string(pa->pa_pc, ih); 631 if (intrstr == NULL) 632 intrstr = "<I dunno>"; 633 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 634 isp_pci_intr, isp); 635 if (pcs->pci_ih == NULL) { 636 printf("%s: couldn't establish interrupt at %s\n", 637 isp->isp_name, intrstr); 638 free(isp->isp_param, M_DEVBUF); 639 return; 640 } 641 642 printf("%s: interrupting at %s\n", isp->isp_name, intrstr); 643 644 if (IS_FC(isp)) { 645 DEFAULT_NODEWWN(isp) = 0x400000007F000002ULL; 646 DEFAULT_PORTWWN(isp) = 0x400000007F000002ULL; 647 } 648 649 isp->isp_confopts = self->dv_cfdata->cf_flags; 650 isp->isp_role = ISP_DEFAULT_ROLES; 651 ISP_LOCK(isp); 652 isp->isp_osinfo.no_mbox_ints = 1; 653 isp_reset(isp); 654 if (isp->isp_state != ISP_RESETSTATE) { 655 ISP_UNLOCK(isp); 656 free(isp->isp_param, M_DEVBUF); 657 return; 658 } 659 ENABLE_INTS(isp); 660 isp_init(isp); 661 if (isp->isp_state != ISP_INITSTATE) { 662 isp_uninit(isp); 663 ISP_UNLOCK(isp); 664 free(isp->isp_param, M_DEVBUF); 665 return; 666 } 667 /* 668 * Do platform attach. 669 */ 670 ISP_UNLOCK(isp); 671 isp_attach(isp); 672 if (isp->isp_state != ISP_RUNSTATE) { 673 ISP_LOCK(isp); 674 isp_uninit(isp); 675 free(isp->isp_param, M_DEVBUF); 676 ISP_UNLOCK(isp); 677 } 678 } 679 680 #define IspVirt2Off(a, x) \ 681 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 682 _BLK_REG_SHFT] + ((x) & 0xff)) 683 684 #define BXR2(pcs, off) \ 685 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 686 #define BXW2(pcs, off, v) \ 687 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 688 689 690 static INLINE int 691 isp_pci_rd_debounced(struct ispsoftc *isp, int off, u_int16_t *rp) 692 { 693 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 694 u_int16_t val0, val1; 695 int i = 0; 696 697 do { 698 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 699 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 700 } while (val0 != val1 && ++i < 1000); 701 if (val0 != val1) { 702 return (1); 703 } 704 *rp = val0; 705 return (0); 706 } 707 708 static int 709 isp_pci_rd_isr(struct ispsoftc *isp, u_int16_t *isrp, 710 u_int16_t *semap, u_int16_t *mbp) 711 { 712 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 713 u_int16_t isr, sema; 714 715 if (IS_2100(isp)) { 716 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 717 return (0); 718 } 719 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 720 return (0); 721 } 722 } else { 723 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 724 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 725 } 726 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 727 isr &= INT_PENDING_MASK(isp); 728 sema &= BIU_SEMA_LOCK; 729 if (isr == 0 && sema == 0) { 730 return (0); 731 } 732 *isrp = isr; 733 if ((*semap = sema) != 0) { 734 if (IS_2100(isp)) { 735 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 736 return (0); 737 } 738 } else { 739 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 740 } 741 } 742 return (1); 743 } 744 745 #ifndef ISP_DISABLE_2300_SUPPORT 746 static int 747 isp_pci_rd_isr_2300(struct ispsoftc *isp, u_int16_t *isrp, 748 u_int16_t *semap, u_int16_t *mbox0p) 749 { 750 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 751 u_int32_t r2hisr; 752 753 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT)) { 754 *isrp = 0; 755 return (0); 756 } 757 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 758 IspVirt2Off(pcs, BIU_R2HSTSLO)); 759 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 760 if ((r2hisr & BIU_R2HST_INTR) == 0) { 761 *isrp = 0; 762 return (0); 763 } 764 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 765 case ISPR2HST_ROM_MBX_OK: 766 case ISPR2HST_ROM_MBX_FAIL: 767 case ISPR2HST_MBX_OK: 768 case ISPR2HST_MBX_FAIL: 769 case ISPR2HST_ASYNC_EVENT: 770 *isrp = r2hisr & 0xffff; 771 *mbox0p = (r2hisr >> 16); 772 *semap = 1; 773 return (1); 774 case ISPR2HST_RIO_16: 775 *isrp = r2hisr & 0xffff; 776 *mbox0p = ASYNC_RIO1; 777 *semap = 1; 778 return (1); 779 case ISPR2HST_FPOST: 780 *isrp = r2hisr & 0xffff; 781 *mbox0p = ASYNC_CMD_CMPLT; 782 *semap = 1; 783 return (1); 784 case ISPR2HST_FPOST_CTIO: 785 *isrp = r2hisr & 0xffff; 786 *mbox0p = ASYNC_CTIO_DONE; 787 *semap = 1; 788 return (1); 789 case ISPR2HST_RSPQ_UPDATE: 790 *isrp = r2hisr & 0xffff; 791 *mbox0p = 0; 792 *semap = 0; 793 return (1); 794 default: 795 return (0); 796 } 797 } 798 #endif 799 800 static u_int16_t 801 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 802 { 803 u_int16_t rv; 804 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 805 int oldconf = 0; 806 807 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 808 /* 809 * We will assume that someone has paused the RISC processor. 810 */ 811 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 812 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 813 oldconf | BIU_PCI_CONF1_SXP); 814 } 815 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 816 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 817 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 818 } 819 return (rv); 820 } 821 822 static void 823 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val) 824 { 825 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 826 int oldconf = 0; 827 828 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 829 /* 830 * We will assume that someone has paused the RISC processor. 831 */ 832 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 833 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 834 oldconf | BIU_PCI_CONF1_SXP); 835 } 836 BXW2(pcs, IspVirt2Off(isp, regoff), val); 837 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 838 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 839 } 840 } 841 842 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 843 static u_int16_t 844 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 845 { 846 u_int16_t rv, oc = 0; 847 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 848 849 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 850 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 851 u_int16_t tc; 852 /* 853 * We will assume that someone has paused the RISC processor. 854 */ 855 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 856 tc = oc & ~BIU_PCI1080_CONF1_DMA; 857 if (regoff & SXP_BANK1_SELECT) 858 tc |= BIU_PCI1080_CONF1_SXP1; 859 else 860 tc |= BIU_PCI1080_CONF1_SXP0; 861 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 862 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 863 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 864 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 865 oc | BIU_PCI1080_CONF1_DMA); 866 } 867 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 868 if (oc) { 869 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 870 } 871 return (rv); 872 } 873 874 static void 875 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val) 876 { 877 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 878 int oc = 0; 879 880 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 881 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 882 u_int16_t tc; 883 /* 884 * We will assume that someone has paused the RISC processor. 885 */ 886 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 887 tc = oc & ~BIU_PCI1080_CONF1_DMA; 888 if (regoff & SXP_BANK1_SELECT) 889 tc |= BIU_PCI1080_CONF1_SXP1; 890 else 891 tc |= BIU_PCI1080_CONF1_SXP0; 892 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 893 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 894 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 895 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 896 oc | BIU_PCI1080_CONF1_DMA); 897 } 898 BXW2(pcs, IspVirt2Off(isp, regoff), val); 899 if (oc) { 900 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 901 } 902 } 903 #endif 904 905 static int 906 isp_pci_mbxdma(struct ispsoftc *isp) 907 { 908 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 909 bus_dma_tag_t dmat = isp->isp_dmatag; 910 bus_dma_segment_t sg; 911 bus_size_t len; 912 fcparam *fcp; 913 int rs, i; 914 915 if (isp->isp_rquest_dma) /* been here before? */ 916 return (0); 917 918 len = isp->isp_maxcmds * sizeof (XS_T *); 919 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK); 920 if (isp->isp_xflist == NULL) { 921 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array"); 922 return (1); 923 } 924 memset(isp->isp_xflist, 0, len); 925 len = isp->isp_maxcmds * sizeof (bus_dmamap_t); 926 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 927 if (pcs->pci_xfer_dmap == NULL) { 928 free(isp->isp_xflist, M_DEVBUF); 929 isp->isp_xflist = NULL; 930 isp_prt(isp, ISP_LOGERR, "cannot malloc dma map array"); 931 return (1); 932 } 933 for (i = 0; i < isp->isp_maxcmds; i++) { 934 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1, 935 MAXPHYS, 0, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) { 936 isp_prt(isp, ISP_LOGERR, "cannot create dma maps"); 937 break; 938 } 939 } 940 if (i < isp->isp_maxcmds) { 941 while (--i >= 0) { 942 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 943 } 944 free(isp->isp_xflist, M_DEVBUF); 945 free(pcs->pci_xfer_dmap, M_DEVBUF); 946 isp->isp_xflist = NULL; 947 pcs->pci_xfer_dmap = NULL; 948 return (1); 949 } 950 951 /* 952 * Allocate and map the request queue. 953 */ 954 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 955 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 956 BUS_DMA_NOWAIT) || 957 bus_dmamem_map(isp->isp_dmatag, &sg, rs, len, 958 (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 959 goto dmafail; 960 } 961 962 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 963 &isp->isp_rqdmap) || bus_dmamap_load(dmat, isp->isp_rqdmap, 964 (caddr_t)isp->isp_rquest, len, NULL, 965 BUS_DMA_NOWAIT)) { 966 goto dmafail; 967 } 968 isp->isp_rquest_dma = isp->isp_rqdmap->dm_segs[0].ds_addr; 969 970 /* 971 * Allocate and map the result queue. 972 */ 973 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 974 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 975 BUS_DMA_NOWAIT) || 976 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&isp->isp_result, 977 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 978 goto dmafail; 979 } 980 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 981 &isp->isp_rsdmap) || bus_dmamap_load(isp->isp_dmatag, 982 isp->isp_rsdmap, (caddr_t)isp->isp_result, len, NULL, 983 BUS_DMA_NOWAIT)) { 984 goto dmafail; 985 } 986 isp->isp_result_dma = isp->isp_rsdmap->dm_segs[0].ds_addr; 987 988 if (IS_SCSI(isp)) { 989 return (0); 990 } 991 992 fcp = isp->isp_param; 993 len = ISP2100_SCRLEN; 994 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 995 BUS_DMA_NOWAIT) || 996 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&fcp->isp_scratch, 997 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 998 goto dmafail; 999 } 1000 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 1001 &isp->isp_scdmap) || bus_dmamap_load(dmat, 1002 isp->isp_scdmap, (caddr_t)fcp->isp_scratch, len, NULL, 1003 BUS_DMA_NOWAIT)) { 1004 goto dmafail; 1005 } 1006 fcp->isp_scdma = isp->isp_scdmap->dm_segs[0].ds_addr; 1007 return (0); 1008 dmafail: 1009 isp_prt(isp, ISP_LOGERR, "mailbox dma setup failure"); 1010 for (i = 0; i < isp->isp_maxcmds; i++) { 1011 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 1012 } 1013 free(isp->isp_xflist, M_DEVBUF); 1014 free(pcs->pci_xfer_dmap, M_DEVBUF); 1015 isp->isp_xflist = NULL; 1016 pcs->pci_xfer_dmap = NULL; 1017 return (1); 1018 } 1019 1020 static int 1021 isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, ispreq_t *rq, 1022 u_int16_t *nxtip, u_int16_t optr) 1023 { 1024 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1025 bus_dmamap_t dmap; 1026 u_int16_t starti = isp->isp_reqidx, nxti = *nxtip; 1027 ispreq_t *qep; 1028 int segcnt, seg, error, ovseg, seglim, drq; 1029 1030 qep = (ispreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, starti); 1031 dmap = pcs->pci_xfer_dmap[isp_handle_index(rq->req_handle)]; 1032 if (xs->datalen == 0) { 1033 rq->req_seg_count = 1; 1034 goto mbxsync; 1035 } 1036 if (xs->xs_control & XS_CTL_DATA_IN) { 1037 drq = REQFLAG_DATA_IN; 1038 } else { 1039 drq = REQFLAG_DATA_OUT; 1040 } 1041 1042 if (IS_FC(isp)) { 1043 seglim = ISP_RQDSEG_T2; 1044 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen; 1045 ((ispreqt2_t *)rq)->req_flags |= drq; 1046 } else { 1047 rq->req_flags |= drq; 1048 if (XS_CDBLEN(xs) > 12) { 1049 seglim = 0; 1050 } else { 1051 seglim = ISP_RQDSEG; 1052 } 1053 } 1054 error = bus_dmamap_load(isp->isp_dmatag, dmap, xs->data, xs->datalen, 1055 NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ? 1056 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 1057 ((xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1058 if (error) { 1059 isp_prt(isp, ISP_LOGWARN, "unable to load dma (%d)", error); 1060 XS_SETERR(xs, HBA_BOTCH); 1061 if (error == EAGAIN || error == ENOMEM) 1062 return (CMD_EAGAIN); 1063 else 1064 return (CMD_COMPLETE); 1065 } 1066 1067 segcnt = dmap->dm_nsegs; 1068 1069 isp_prt(isp, ISP_LOGDEBUG2, "%d byte %s %p in %d segs", 1070 xs->datalen, (xs->xs_control & XS_CTL_DATA_IN)? "read to" : 1071 "write from", xs->data, segcnt); 1072 1073 for (seg = 0, rq->req_seg_count = 0; 1074 seglim && seg < segcnt && rq->req_seg_count < seglim; 1075 seg++, rq->req_seg_count++) { 1076 if (IS_FC(isp)) { 1077 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1078 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1079 dmap->dm_segs[seg].ds_len; 1080 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1081 dmap->dm_segs[seg].ds_addr; 1082 } else { 1083 rq->req_dataseg[rq->req_seg_count].ds_count = 1084 dmap->dm_segs[seg].ds_len; 1085 rq->req_dataseg[rq->req_seg_count].ds_base = 1086 dmap->dm_segs[seg].ds_addr; 1087 } 1088 isp_prt(isp, ISP_LOGDEBUG2, "seg0.[%d]={0x%lx,%lu}", 1089 rq->req_seg_count, (long) dmap->dm_segs[seg].ds_addr, 1090 (unsigned long) dmap->dm_segs[seg].ds_len); 1091 } 1092 1093 if (seg == segcnt) { 1094 goto dmasync; 1095 } 1096 1097 do { 1098 u_int16_t onxti; 1099 ispcontreq_t *crq, *cqe, local; 1100 1101 crq = &local; 1102 1103 cqe = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1104 onxti = nxti; 1105 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 1106 if (nxti == optr) { 1107 isp_prt(isp, /* ISP_LOGDEBUG0 */ ISP_LOGERR, "Request Queue Overflow++"); 1108 bus_dmamap_unload(isp->isp_dmatag, dmap); 1109 XS_SETERR(xs, HBA_BOTCH); 1110 return (CMD_EAGAIN); 1111 } 1112 rq->req_header.rqs_entry_count++; 1113 memset((void *)crq, 0, sizeof (*crq)); 1114 crq->req_header.rqs_entry_count = 1; 1115 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1116 1117 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG; 1118 rq->req_seg_count++, seg++, ovseg++) { 1119 crq->req_dataseg[ovseg].ds_count = 1120 dmap->dm_segs[seg].ds_len; 1121 crq->req_dataseg[ovseg].ds_base = 1122 dmap->dm_segs[seg].ds_addr; 1123 isp_prt(isp, ISP_LOGDEBUG2, "seg%d.[%d]={0x%lx,%lu}", 1124 rq->req_header.rqs_entry_count - 1, 1125 rq->req_seg_count, (long)dmap->dm_segs[seg].ds_addr, 1126 (unsigned long) dmap->dm_segs[seg].ds_len); 1127 } 1128 isp_put_cont_req(isp, crq, cqe); 1129 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 1130 } while (seg < segcnt); 1131 1132 1133 dmasync: 1134 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1135 (xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD : 1136 BUS_DMASYNC_PREWRITE); 1137 1138 mbxsync: 1139 switch (rq->req_header.rqs_entry_type) { 1140 case RQSTYPE_REQUEST: 1141 isp_put_request(isp, rq, qep); 1142 break; 1143 case RQSTYPE_CMDONLY: 1144 isp_put_extended_request(isp, (ispextreq_t *)rq, 1145 (ispextreq_t *)qep); 1146 break; 1147 case RQSTYPE_T2RQS: 1148 isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) qep); 1149 break; 1150 } 1151 *nxtip = nxti; 1152 return (CMD_QUEUED); 1153 } 1154 1155 static int 1156 isp_pci_intr(void *arg) 1157 { 1158 u_int16_t isr, sema, mbox; 1159 struct ispsoftc *isp = arg; 1160 1161 isp->isp_intcnt++; 1162 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 1163 isp->isp_intbogus++; 1164 return (0); 1165 } else { 1166 isp->isp_osinfo.onintstack = 1; 1167 isp_intr(isp, isr, sema, mbox); 1168 isp->isp_osinfo.onintstack = 0; 1169 return (1); 1170 } 1171 } 1172 1173 static void 1174 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int16_t handle) 1175 { 1176 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1177 bus_dmamap_t dmap = pcs->pci_xfer_dmap[isp_handle_index(handle)]; 1178 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1179 xs->xs_control & XS_CTL_DATA_IN ? 1180 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1181 bus_dmamap_unload(isp->isp_dmatag, dmap); 1182 } 1183 1184 static void 1185 isp_pci_reset1(struct ispsoftc *isp) 1186 { 1187 /* Make sure the BIOS is disabled */ 1188 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1189 if (isp->isp_osinfo.no_mbox_ints == 0) { 1190 ENABLE_INTS(isp); 1191 } 1192 1193 } 1194 1195 static void 1196 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1197 { 1198 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1199 if (msg) 1200 printf("%s: %s\n", isp->isp_name, msg); 1201 if (IS_SCSI(isp)) 1202 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1203 else 1204 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1205 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1206 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1207 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1208 1209 1210 if (IS_SCSI(isp)) { 1211 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1212 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1213 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1214 ISP_READ(isp, CDMA_FIFO_STS)); 1215 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1216 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1217 ISP_READ(isp, DDMA_FIFO_STS)); 1218 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1219 ISP_READ(isp, SXP_INTERRUPT), 1220 ISP_READ(isp, SXP_GROSS_ERR), 1221 ISP_READ(isp, SXP_PINS_CTRL)); 1222 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1223 } 1224 printf(" mbox regs: %x %x %x %x %x\n", 1225 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1226 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1227 ISP_READ(isp, OUTMAILBOX4)); 1228 printf(" PCI Status Command/Status=%x\n", 1229 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG)); 1230 } 1231