1 /* $NetBSD: nside.c,v 1.1 2010/11/10 22:34:24 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: nside.c,v 1.1 2010/11/10 22:34:24 skrll Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pciidereg.h> 36 #include <dev/pci/pciidevar.h> 37 #include <dev/pci/pciide_natsemi_reg.h> 38 39 static void natsemi_chip_map(struct pciide_softc*, struct pci_attach_args*); 40 static void natsemi_setup_channel(struct ata_channel*); 41 static int natsemi_pci_intr(void *); 42 static void natsemi_irqack(struct ata_channel *); 43 44 static int nside_match(device_t, cfdata_t, void *); 45 static void nside_attach(device_t, device_t, void *); 46 47 struct nside_softc { 48 struct pciide_softc pciide_sc; 49 struct pci_attach_args pcib_pa; 50 }; 51 52 CFATTACH_DECL_NEW(nside, sizeof(struct nside_softc), 53 nside_match, nside_attach, NULL, NULL); 54 55 static const struct pciide_product_desc pciide_natsemi_products[] = { 56 { PCI_PRODUCT_NS_PC87415, /* National Semi PC87415 IDE */ 57 0, 58 "National Semiconductor PC87415 IDE Controller", 59 natsemi_chip_map, 60 }, 61 { 0, 62 0, 63 NULL, 64 NULL 65 } 66 }; 67 68 static int 69 nside_match(device_t parent, cfdata_t match, void *aux) 70 { 71 struct pci_attach_args *pa = aux; 72 73 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 74 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 75 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 76 if (pciide_lookup_product(pa->pa_id, pciide_natsemi_products)) 77 return 2; 78 } 79 return 0; 80 } 81 82 static void 83 nside_attach(device_t parent, device_t self, void *aux) 84 { 85 struct pci_attach_args *pa = aux; 86 struct pciide_softc *sc = device_private(self); 87 88 sc->sc_wdcdev.sc_atac.atac_dev = self; 89 90 pciide_common_attach(sc, pa, 91 pciide_lookup_product(pa->pa_id, pciide_natsemi_products)); 92 } 93 94 static void 95 natsemi_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 96 { 97 struct pciide_channel *cp; 98 int channel; 99 pcireg_t interface, ctl; 100 101 if (pciide_chipen(sc, pa) == 0) 102 return; 103 104 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 105 "bus-master DMA support present"); 106 pciide_mapreg_dma(sc, pa); 107 aprint_verbose("\n"); 108 109 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 110 111 if (sc->sc_dma_ok) { 112 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 113 sc->sc_wdcdev.irqack = natsemi_irqack; 114 } 115 116 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CCBT, 0xb7); 117 118 /* 119 * Mask off interrupts from both channels, appropriate channel(s) 120 * will be unmasked later. 121 */ 122 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2, 123 pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) | 124 NATSEMI_CHMASK(0) | NATSEMI_CHMASK(1)); 125 126 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 127 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 128 sc->sc_wdcdev.sc_atac.atac_set_modes = natsemi_setup_channel; 129 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 130 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 131 132 interface = PCI_INTERFACE(pa->pa_class); 133 interface &= ~PCIIDE_CHANSTATUS_EN; /* Reserved on PC87415 */ 134 135 /* If we're in PCIIDE mode, unmask INTA, otherwise mask it. */ 136 ctl = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1); 137 if (interface & (PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1))) 138 ctl &= ~NATSEMI_CTRL1_INTAMASK; 139 else 140 ctl |= NATSEMI_CTRL1_INTAMASK; 141 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1, ctl); 142 143 wdc_allocate_regs(&sc->sc_wdcdev); 144 145 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; channel++) { 146 cp = &sc->pciide_channels[channel]; 147 if (pciide_chansetup(sc, channel, interface) == 0) 148 continue; 149 150 pciide_mapchan(pa, cp, interface, natsemi_pci_intr); 151 152 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2, 153 pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) & 154 ~(NATSEMI_CHMASK(channel))); 155 } 156 } 157 158 void 159 natsemi_setup_channel(struct ata_channel *chp) 160 { 161 struct ata_drive_datas *drvp; 162 int drive, ndrives = 0; 163 uint32_t idedma_ctl = 0; 164 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 165 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 166 uint8_t tim; 167 168 /* setup DMA if needed */ 169 pciide_channel_dma_setup(cp); 170 171 for (drive = 0; drive < 2; drive++) { 172 drvp = &chp->ch_drive[drive]; 173 /* If no drive, skip */ 174 if ((drvp->drive_flags & DRIVE) == 0) 175 continue; 176 177 ndrives++; 178 /* add timing values, setup DMA if needed */ 179 if ((drvp->drive_flags & DRIVE_DMA) == 0) { 180 tim = natsemi_pio_pulse[drvp->PIO_mode] | 181 (natsemi_pio_recover[drvp->PIO_mode] << 4); 182 } else { 183 /* 184 * use Multiword DMA 185 * Timings will be used for both PIO and DMA, 186 * so adjust DMA mode if needed 187 */ 188 if (drvp->PIO_mode >= 3 && 189 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 190 drvp->DMA_mode = drvp->PIO_mode - 2; 191 } 192 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 193 tim = natsemi_dma_pulse[drvp->DMA_mode] | 194 (natsemi_dma_recover[drvp->DMA_mode] << 4); 195 196 } 197 198 pciide_pci_write(sc->sc_pc, sc->sc_tag, 199 NATSEMI_RTREG(chp->ch_channel, drive), tim); 200 pciide_pci_write(sc->sc_pc, sc->sc_tag, 201 NATSEMI_WTREG(chp->ch_channel, drive), tim); 202 } 203 204 if (idedma_ctl != 0) { 205 /* Add software bits in status register */ 206 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 207 idedma_ctl); 208 209 } 210 /* Go ahead and ack interrupts generated during probe. */ 211 natsemi_irqack(chp); 212 } 213 214 void 215 natsemi_irqack(struct ata_channel *chp) 216 { 217 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 218 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 219 uint8_t clr; 220 221 /* Errata: The "clear" bits are in the wrong register *sigh* */ 222 clr = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0); 223 clr |= bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0) & 224 (IDEDMA_CTL_ERR | IDEDMA_CTL_INTR); 225 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, clr); 226 } 227 228 int 229 natsemi_pci_intr(void *arg) 230 { 231 struct pciide_softc *sc = arg; 232 struct pciide_channel *cp; 233 struct ata_channel *wdc_cp; 234 int i, rv, crv; 235 uint8_t msk; 236 237 rv = 0; 238 msk = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2); 239 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 240 cp = &sc->pciide_channels[i]; 241 wdc_cp = &cp->ata_channel; 242 243 /* If a compat channel skip. */ 244 if (cp->compat) 245 continue; 246 247 /* If this channel is masked, skip it. */ 248 if (msk & NATSEMI_CHMASK(i)) 249 continue; 250 251 crv = wdcintr(wdc_cp); 252 if (crv == 0) 253 ; /* leave alone */ 254 else if (crv == 1) 255 rv = 1; /* claim the intr */ 256 else if (rv == 0) /* crv should be -1 in this case */ 257 rv = crv; /* if we've done no better, take it */ 258 } 259 return (rv); 260 } 261