xref: /netbsd/sys/dev/pci/pci.c (revision bf9ec67e) 
1 /*	$NetBSD: pci.c,v 1.65 2002/05/18 21:40:41 sommerfeld Exp $	*/
2 
3 /*
4  * Copyright (c) 1995, 1996, 1997, 1998
5  *     Christopher G. Demetriou.  All rights reserved.
6  * Copyright (c) 1994 Charles M. Hannum.  All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product includes software developed by Charles M. Hannum.
19  * 4. The name of the author may not be used to endorse or promote products
20  *    derived from this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 /*
35  * PCI bus autoconfiguration.
36  */
37 
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.65 2002/05/18 21:40:41 sommerfeld Exp $");
40 
41 #include "opt_pci.h"
42 
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/device.h>
46 
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcidevs.h>
50 
51 #ifdef PCI_CONFIG_DUMP
52 int pci_config_dump = 1;
53 #else
54 int pci_config_dump = 0;
55 #endif
56 
57 int pcimatch __P((struct device *, struct cfdata *, void *));
58 void pciattach __P((struct device *, struct device *, void *));
59 
60 struct cfattach pci_ca = {
61 	sizeof(struct pci_softc), pcimatch, pciattach
62 };
63 
64 int	pciprint __P((void *, const char *));
65 int	pcisubmatch __P((struct device *, struct cfdata *, void *));
66 
67 /*
68  * Important note about PCI-ISA bridges:
69  *
70  * Callbacks are used to configure these devices so that ISA/EISA bridges
71  * can attach their child busses after PCI configuration is done.
72  *
73  * This works because:
74  *	(1) there can be at most one ISA/EISA bridge per PCI bus, and
75  *	(2) any ISA/EISA bridges must be attached to primary PCI
76  *	    busses (i.e. bus zero).
77  *
78  * That boils down to: there can only be one of these outstanding
79  * at a time, it is cleared when configuring PCI bus 0 before any
80  * subdevices have been found, and it is run after all subdevices
81  * of PCI bus 0 have been found.
82  *
83  * This is needed because there are some (legacy) PCI devices which
84  * can show up as ISA/EISA devices as well (the prime example of which
85  * are VGA controllers).  If you attach ISA from a PCI-ISA/EISA bridge,
86  * and the bridge is seen before the video board is, the board can show
87  * up as an ISA device, and that can (bogusly) complicate the PCI device's
88  * attach code, or make the PCI device not be properly attached at all.
89  *
90  * We use the generic config_defer() facility to achieve this.
91  */
92 
93 int
94 pcimatch(parent, cf, aux)
95 	struct device *parent;
96 	struct cfdata *cf;
97 	void *aux;
98 {
99 	struct pcibus_attach_args *pba = aux;
100 
101 	if (strcmp(pba->pba_busname, cf->cf_driver->cd_name))
102 		return (0);
103 
104 	/* Check the locators */
105 	if (cf->pcibuscf_bus != PCIBUS_UNK_BUS &&
106 	    cf->pcibuscf_bus != pba->pba_bus)
107 		return (0);
108 
109 	/* sanity */
110 	if (pba->pba_bus < 0 || pba->pba_bus > 255)
111 		return (0);
112 
113 	/*
114 	 * XXX check other (hardware?) indicators
115 	 */
116 
117 	return (1);
118 }
119 
120 void
121 pciattach(parent, self, aux)
122 	struct device *parent, *self;
123 	void *aux;
124 {
125 	struct pcibus_attach_args *pba = aux;
126 	struct pci_softc *sc = (struct pci_softc *)self;
127 	int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled;
128 	const char *sep = "";
129 
130 	pci_attach_hook(parent, self, pba);
131 	printf("\n");
132 
133 	io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED);
134 	mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED);
135 	mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY);
136 	mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY);
137 	mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY);
138 
139 	if (io_enabled == 0 && mem_enabled == 0) {
140 		printf("%s: no spaces enabled!\n", self->dv_xname);
141 		return;
142 	}
143 
144 #define	PRINT(s)	do { printf("%s%s", sep, s); sep = ", "; } while (0)
145 
146 	printf("%s: ", self->dv_xname);
147 
148 	if (io_enabled)
149 		PRINT("i/o space");
150 	if (mem_enabled)
151 		PRINT("memory space");
152 	printf(" enabled");
153 
154 	if (mrl_enabled || mrm_enabled || mwi_enabled) {
155 		if (mrl_enabled)
156 			PRINT("rd/line");
157 		if (mrm_enabled)
158 			PRINT("rd/mult");
159 		if (mwi_enabled)
160 			PRINT("wr/inv");
161 		printf(" ok");
162 	}
163 
164 	printf("\n");
165 
166 #undef PRINT
167 
168 	sc->sc_iot = pba->pba_iot;
169 	sc->sc_memt = pba->pba_memt;
170 	sc->sc_dmat = pba->pba_dmat;
171 	sc->sc_pc = pba->pba_pc;
172 	sc->sc_bus = pba->pba_bus;
173 	sc->sc_bridgetag = pba->pba_bridgetag;
174 	sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus);
175 	sc->sc_intrswiz = pba->pba_intrswiz;
176 	sc->sc_intrtag = pba->pba_intrtag;
177 	sc->sc_flags = pba->pba_flags;
178 	pci_enumerate_bus(sc, NULL, NULL);
179 }
180 
181 int
182 pciprint(aux, pnp)
183 	void *aux;
184 	const char *pnp;
185 {
186 	struct pci_attach_args *pa = aux;
187 	char devinfo[256];
188 	const struct pci_quirkdata *qd;
189 
190 	if (pnp) {
191 		pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo);
192 		printf("%s at %s", devinfo, pnp);
193 	}
194 	printf(" dev %d function %d", pa->pa_device, pa->pa_function);
195 	if (pci_config_dump) {
196 		printf(": ");
197 		pci_conf_print(pa->pa_pc, pa->pa_tag, NULL);
198 		if (!pnp)
199 			pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo);
200 		printf("%s at %s", devinfo, pnp ? pnp : "?");
201 		printf(" dev %d function %d (", pa->pa_device, pa->pa_function);
202 #ifdef __i386__
203 		printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx",
204 		    *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag,
205 		    (long)pa->pa_intrswiz, (long)pa->pa_intrpin);
206 #else
207 		printf("intrswiz %#lx, intrpin %#lx",
208 		    (long)pa->pa_intrswiz, (long)pa->pa_intrpin);
209 #endif
210 		printf(", i/o %s, mem %s,",
211 		    pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off",
212 		    pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off");
213 		qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id),
214 		    PCI_PRODUCT(pa->pa_id));
215 		if (qd == NULL) {
216 			printf(" no quirks");
217 		} else {
218 			bitmask_snprintf(qd->quirks,
219 			    "\20\1multifn", devinfo, sizeof (devinfo));
220 			printf(" quirks %s", devinfo);
221 		}
222 		printf(")");
223 	}
224 	return (UNCONF);
225 }
226 
227 int
228 pcisubmatch(parent, cf, aux)
229 	struct device *parent;
230 	struct cfdata *cf;
231 	void *aux;
232 {
233 	struct pci_attach_args *pa = aux;
234 
235 	if (cf->pcicf_dev != PCI_UNK_DEV &&
236 	    cf->pcicf_dev != pa->pa_device)
237 		return (0);
238 	if (cf->pcicf_function != PCI_UNK_FUNCTION &&
239 	    cf->pcicf_function != pa->pa_function)
240 		return (0);
241 	return ((*cf->cf_attach->ca_match)(parent, cf, aux));
242 }
243 
244 int
245 pci_probe_device(struct pci_softc *sc, pcitag_t tag,
246     int (*match)(struct pci_attach_args *), struct pci_attach_args *pap)
247 {
248 	pci_chipset_tag_t pc = sc->sc_pc;
249 	struct pci_attach_args pa;
250 	pcireg_t id, csr, class, intr, bhlcr;
251 	int ret, pin, bus, device, function;
252 
253 	pci_decompose_tag(pc, tag, &bus, &device, &function);
254 
255 	id = pci_conf_read(pc, tag, PCI_ID_REG);
256 	csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
257 	class = pci_conf_read(pc, tag, PCI_CLASS_REG);
258 	intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
259 	bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG);
260 
261 	/* Invalid vendor ID value? */
262 	if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
263 		return (NULL);
264 	/* XXX Not invalid, but we've done this ~forever. */
265 	if (PCI_VENDOR(id) == 0)
266 		return (NULL);
267 
268 	pa.pa_iot = sc->sc_iot;
269 	pa.pa_memt = sc->sc_memt;
270 	pa.pa_dmat = sc->sc_dmat;
271 	pa.pa_pc = pc;
272 	pa.pa_bus = bus;
273 	pa.pa_device = device;
274 	pa.pa_function = function;
275 	pa.pa_tag = tag;
276 	pa.pa_id = id;
277 	pa.pa_class = class;
278 
279 	/*
280 	 * Set up memory, I/O enable, and PCI command flags
281 	 * as appropriate.
282 	 */
283 	pa.pa_flags = sc->sc_flags;
284 	if ((csr & PCI_COMMAND_IO_ENABLE) == 0)
285 		pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED;
286 	if ((csr & PCI_COMMAND_MEM_ENABLE) == 0)
287 		pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED;
288 
289 	/*
290 	 * If the cache line size is not configured, then
291 	 * clear the MRL/MRM/MWI command-ok flags.
292 	 */
293 	if (PCI_CACHELINE(bhlcr) == 0)
294 		pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY|
295 		    PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY);
296 
297 	if (sc->sc_bridgetag == NULL) {
298 		pa.pa_intrswiz = 0;
299 		pa.pa_intrtag = tag;
300 	} else {
301 		pa.pa_intrswiz = sc->sc_intrswiz + device;
302 		pa.pa_intrtag = sc->sc_intrtag;
303 	}
304 	pin = PCI_INTERRUPT_PIN(intr);
305 	pa.pa_rawintrpin = pin;
306 	if (pin == PCI_INTERRUPT_PIN_NONE) {
307 		/* no interrupt */
308 		pa.pa_intrpin = 0;
309 	} else {
310 		/*
311 		 * swizzle it based on the number of busses we're
312 		 * behind and our device number.
313 		 */
314 		pa.pa_intrpin = 	/* XXX */
315 		    ((pin + pa.pa_intrswiz - 1) % 4) + 1;
316 	}
317 	pa.pa_intrline = PCI_INTERRUPT_LINE(intr);
318 
319 	if (match != NULL) {
320 		ret = (*match)(&pa);
321 		if (ret != 0 && pap != NULL)
322 			*pap = pa;
323 	} else {
324 		ret = config_found_sm(&sc->sc_dev, &pa, pciprint,
325 		    pcisubmatch) != NULL;
326 	}
327 
328 	return (ret);
329 }
330 
331 int
332 pci_get_capability(pc, tag, capid, offset, value)
333 	pci_chipset_tag_t pc;
334 	pcitag_t tag;
335 	int capid;
336 	int *offset;
337 	pcireg_t *value;
338 {
339 	pcireg_t reg;
340 	unsigned int ofs;
341 
342 	reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
343 	if (!(reg & PCI_STATUS_CAPLIST_SUPPORT))
344 		return (0);
345 
346 	/* Determine the Capability List Pointer register to start with. */
347 	reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
348 	switch (PCI_HDRTYPE_TYPE(reg)) {
349 	case 0:	/* standard device header */
350 		ofs = PCI_CAPLISTPTR_REG;
351 		break;
352 	case 2:	/* PCI-CardBus Bridge header */
353 		ofs = PCI_CARDBUS_CAPLISTPTR_REG;
354 		break;
355 	default:
356 		return (0);
357 	}
358 
359 	ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs));
360 	while (ofs != 0) {
361 #ifdef DIAGNOSTIC
362 		if ((ofs & 3) || (ofs < 0x40))
363 			panic("pci_get_capability");
364 #endif
365 		reg = pci_conf_read(pc, tag, ofs);
366 		if (PCI_CAPLIST_CAP(reg) == capid) {
367 			if (offset)
368 				*offset = ofs;
369 			if (value)
370 				*value = reg;
371 			return (1);
372 		}
373 		ofs = PCI_CAPLIST_NEXT(reg);
374 	}
375 
376 	return (0);
377 }
378 
379 int
380 pci_find_device(struct pci_attach_args *pa,
381 		int (*match)(struct pci_attach_args *))
382 {
383 	extern struct cfdriver pci_cd;
384 	struct device *pcidev;
385 	int i;
386 
387 	for (i = 0; i < pci_cd.cd_ndevs; i++) {
388 		pcidev = pci_cd.cd_devs[i];
389 		if (pcidev != NULL &&
390 		    pci_enumerate_bus((struct pci_softc *) pcidev,
391 		    		      match, pa) != 0)
392 			return (1);
393 	}
394 	return (0);
395 }
396 
397 /*
398  * Generic PCI bus enumeration routine.  Used unless machine-dependent
399  * code needs to provide something else.
400  */
401 int
402 pci_enumerate_bus_generic(struct pci_softc *sc,
403     int (*match)(struct pci_attach_args *), struct pci_attach_args *pap)
404 {
405 	pci_chipset_tag_t pc = sc->sc_pc;
406 	int device, function, nfunctions, ret;
407 	const struct pci_quirkdata *qd;
408 	pcireg_t id, bhlcr;
409 	pcitag_t tag;
410 #ifdef __PCI_BUS_DEVORDER
411 	char devs[32];
412 	int i;
413 #endif
414 
415 #ifdef __PCI_BUS_DEVORDER
416 	pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs);
417 	for (i = 0; (device = devs[i]) < 32 && device >= 0; i++)
418 #else
419 	for (device = 0; device < sc->sc_maxndevs; device++)
420 #endif
421 	{
422 		tag = pci_make_tag(pc, sc->sc_bus, device, 0);
423 		id = pci_conf_read(pc, tag, PCI_ID_REG);
424 
425 		/* Invalid vendor ID value? */
426 		if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
427 			continue;
428 		/* XXX Not invalid, but we've done this ~forever. */
429 		if (PCI_VENDOR(id) == 0)
430 			continue;
431 
432 		qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id));
433 
434 		bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG);
435 		if (PCI_HDRTYPE_MULTIFN(bhlcr) ||
436 		    (qd != NULL &&
437 		      (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0))
438 			nfunctions = 8;
439 		else
440 			nfunctions = 1;
441 
442 		for (function = 0; function < nfunctions; function++) {
443 			tag = pci_make_tag(pc, sc->sc_bus, device, function);
444 			ret = pci_probe_device(sc, tag, match, pap);
445 			if (match != NULL && ret != 0)
446 				return (ret);
447 		}
448 	}
449 	return (0);
450 }
451