1 /* $NetBSD: pci.c,v 1.74 2002/10/23 01:50:12 perry Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.74 2002/10/23 01:50:12 perry Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 51 #ifdef PCI_CONFIG_DUMP 52 int pci_config_dump = 1; 53 #else 54 int pci_config_dump = 0; 55 #endif 56 57 int pcimatch __P((struct device *, struct cfdata *, void *)); 58 void pciattach __P((struct device *, struct device *, void *)); 59 60 CFATTACH_DECL(pci, sizeof(struct pci_softc), 61 pcimatch, pciattach, NULL, NULL); 62 63 int pciprint __P((void *, const char *)); 64 int pcisubmatch __P((struct device *, struct cfdata *, void *)); 65 66 /* 67 * Important note about PCI-ISA bridges: 68 * 69 * Callbacks are used to configure these devices so that ISA/EISA bridges 70 * can attach their child busses after PCI configuration is done. 71 * 72 * This works because: 73 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 74 * (2) any ISA/EISA bridges must be attached to primary PCI 75 * busses (i.e. bus zero). 76 * 77 * That boils down to: there can only be one of these outstanding 78 * at a time, it is cleared when configuring PCI bus 0 before any 79 * subdevices have been found, and it is run after all subdevices 80 * of PCI bus 0 have been found. 81 * 82 * This is needed because there are some (legacy) PCI devices which 83 * can show up as ISA/EISA devices as well (the prime example of which 84 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 85 * and the bridge is seen before the video board is, the board can show 86 * up as an ISA device, and that can (bogusly) complicate the PCI device's 87 * attach code, or make the PCI device not be properly attached at all. 88 * 89 * We use the generic config_defer() facility to achieve this. 90 */ 91 92 int 93 pcimatch(parent, cf, aux) 94 struct device *parent; 95 struct cfdata *cf; 96 void *aux; 97 { 98 struct pcibus_attach_args *pba = aux; 99 100 if (strcmp(pba->pba_busname, cf->cf_name)) 101 return (0); 102 103 /* Check the locators */ 104 if (cf->pcibuscf_bus != PCIBUS_UNK_BUS && 105 cf->pcibuscf_bus != pba->pba_bus) 106 return (0); 107 108 /* sanity */ 109 if (pba->pba_bus < 0 || pba->pba_bus > 255) 110 return (0); 111 112 /* 113 * XXX check other (hardware?) indicators 114 */ 115 116 return (1); 117 } 118 119 void 120 pciattach(parent, self, aux) 121 struct device *parent, *self; 122 void *aux; 123 { 124 struct pcibus_attach_args *pba = aux; 125 struct pci_softc *sc = (struct pci_softc *)self; 126 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 127 const char *sep = ""; 128 129 pci_attach_hook(parent, self, pba); 130 printf("\n"); 131 132 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 133 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 134 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 135 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 136 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 137 138 if (io_enabled == 0 && mem_enabled == 0) { 139 printf("%s: no spaces enabled!\n", self->dv_xname); 140 return; 141 } 142 143 #define PRINT(str) do { printf("%s%s", sep, str); sep = ", "; } while (0) 144 145 printf("%s: ", self->dv_xname); 146 147 if (io_enabled) 148 PRINT("i/o space"); 149 if (mem_enabled) 150 PRINT("memory space"); 151 printf(" enabled"); 152 153 if (mrl_enabled || mrm_enabled || mwi_enabled) { 154 if (mrl_enabled) 155 PRINT("rd/line"); 156 if (mrm_enabled) 157 PRINT("rd/mult"); 158 if (mwi_enabled) 159 PRINT("wr/inv"); 160 printf(" ok"); 161 } 162 163 printf("\n"); 164 165 #undef PRINT 166 167 sc->sc_iot = pba->pba_iot; 168 sc->sc_memt = pba->pba_memt; 169 sc->sc_dmat = pba->pba_dmat; 170 sc->sc_pc = pba->pba_pc; 171 sc->sc_bus = pba->pba_bus; 172 sc->sc_bridgetag = pba->pba_bridgetag; 173 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 174 sc->sc_intrswiz = pba->pba_intrswiz; 175 sc->sc_intrtag = pba->pba_intrtag; 176 sc->sc_flags = pba->pba_flags; 177 pci_enumerate_bus(sc, NULL, NULL); 178 } 179 180 int 181 pciprint(aux, pnp) 182 void *aux; 183 const char *pnp; 184 { 185 struct pci_attach_args *pa = aux; 186 char devinfo[256]; 187 const struct pci_quirkdata *qd; 188 189 if (pnp) { 190 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 191 printf("%s at %s", devinfo, pnp); 192 } 193 printf(" dev %d function %d", pa->pa_device, pa->pa_function); 194 if (pci_config_dump) { 195 printf(": "); 196 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 197 if (!pnp) 198 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 199 printf("%s at %s", devinfo, pnp ? pnp : "?"); 200 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 201 #ifdef __i386__ 202 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 203 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 204 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 205 #else 206 printf("intrswiz %#lx, intrpin %#lx", 207 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 208 #endif 209 printf(", i/o %s, mem %s,", 210 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 211 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 212 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 213 PCI_PRODUCT(pa->pa_id)); 214 if (qd == NULL) { 215 printf(" no quirks"); 216 } else { 217 bitmask_snprintf(qd->quirks, 218 "\20\1multifn", devinfo, sizeof (devinfo)); 219 printf(" quirks %s", devinfo); 220 } 221 printf(")"); 222 } 223 return (UNCONF); 224 } 225 226 int 227 pcisubmatch(parent, cf, aux) 228 struct device *parent; 229 struct cfdata *cf; 230 void *aux; 231 { 232 struct pci_attach_args *pa = aux; 233 234 if (cf->pcicf_dev != PCI_UNK_DEV && 235 cf->pcicf_dev != pa->pa_device) 236 return (0); 237 if (cf->pcicf_function != PCI_UNK_FUNCTION && 238 cf->pcicf_function != pa->pa_function) 239 return (0); 240 return (config_match(parent, cf, aux)); 241 } 242 243 int 244 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 245 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 246 { 247 pci_chipset_tag_t pc = sc->sc_pc; 248 struct pci_attach_args pa; 249 pcireg_t id, csr, class, intr, bhlcr; 250 int ret, pin, bus, device, function; 251 252 pci_decompose_tag(pc, tag, &bus, &device, &function); 253 254 id = pci_conf_read(pc, tag, PCI_ID_REG); 255 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 256 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 257 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 258 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 259 260 /* Invalid vendor ID value? */ 261 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 262 return (0); 263 /* XXX Not invalid, but we've done this ~forever. */ 264 if (PCI_VENDOR(id) == 0) 265 return (0); 266 267 pa.pa_iot = sc->sc_iot; 268 pa.pa_memt = sc->sc_memt; 269 pa.pa_dmat = sc->sc_dmat; 270 pa.pa_pc = pc; 271 pa.pa_bus = bus; 272 pa.pa_device = device; 273 pa.pa_function = function; 274 pa.pa_tag = tag; 275 pa.pa_id = id; 276 pa.pa_class = class; 277 278 /* 279 * Set up memory, I/O enable, and PCI command flags 280 * as appropriate. 281 */ 282 pa.pa_flags = sc->sc_flags; 283 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 284 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 285 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 286 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 287 288 /* 289 * If the cache line size is not configured, then 290 * clear the MRL/MRM/MWI command-ok flags. 291 */ 292 if (PCI_CACHELINE(bhlcr) == 0) 293 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 294 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 295 296 if (sc->sc_bridgetag == NULL) { 297 pa.pa_intrswiz = 0; 298 pa.pa_intrtag = tag; 299 } else { 300 pa.pa_intrswiz = sc->sc_intrswiz + device; 301 pa.pa_intrtag = sc->sc_intrtag; 302 } 303 pin = PCI_INTERRUPT_PIN(intr); 304 pa.pa_rawintrpin = pin; 305 if (pin == PCI_INTERRUPT_PIN_NONE) { 306 /* no interrupt */ 307 pa.pa_intrpin = 0; 308 } else { 309 /* 310 * swizzle it based on the number of busses we're 311 * behind and our device number. 312 */ 313 pa.pa_intrpin = /* XXX */ 314 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 315 } 316 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 317 318 if (match != NULL) { 319 ret = (*match)(&pa); 320 if (ret != 0 && pap != NULL) 321 *pap = pa; 322 } else { 323 ret = config_found_sm(&sc->sc_dev, &pa, pciprint, 324 pcisubmatch) != NULL; 325 } 326 327 return (ret); 328 } 329 330 int 331 pci_get_capability(pc, tag, capid, offset, value) 332 pci_chipset_tag_t pc; 333 pcitag_t tag; 334 int capid; 335 int *offset; 336 pcireg_t *value; 337 { 338 pcireg_t reg; 339 unsigned int ofs; 340 341 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 342 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 343 return (0); 344 345 /* Determine the Capability List Pointer register to start with. */ 346 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 347 switch (PCI_HDRTYPE_TYPE(reg)) { 348 case 0: /* standard device header */ 349 ofs = PCI_CAPLISTPTR_REG; 350 break; 351 case 2: /* PCI-CardBus Bridge header */ 352 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 353 break; 354 default: 355 return (0); 356 } 357 358 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 359 while (ofs != 0) { 360 #ifdef DIAGNOSTIC 361 if ((ofs & 3) || (ofs < 0x40)) 362 panic("pci_get_capability"); 363 #endif 364 reg = pci_conf_read(pc, tag, ofs); 365 if (PCI_CAPLIST_CAP(reg) == capid) { 366 if (offset) 367 *offset = ofs; 368 if (value) 369 *value = reg; 370 return (1); 371 } 372 ofs = PCI_CAPLIST_NEXT(reg); 373 } 374 375 return (0); 376 } 377 378 int 379 pci_find_device(struct pci_attach_args *pa, 380 int (*match)(struct pci_attach_args *)) 381 { 382 extern struct cfdriver pci_cd; 383 struct device *pcidev; 384 int i; 385 386 for (i = 0; i < pci_cd.cd_ndevs; i++) { 387 pcidev = pci_cd.cd_devs[i]; 388 if (pcidev != NULL && 389 pci_enumerate_bus((struct pci_softc *) pcidev, 390 match, pa) != 0) 391 return (1); 392 } 393 return (0); 394 } 395 396 /* 397 * Generic PCI bus enumeration routine. Used unless machine-dependent 398 * code needs to provide something else. 399 */ 400 int 401 pci_enumerate_bus_generic(struct pci_softc *sc, 402 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 403 { 404 pci_chipset_tag_t pc = sc->sc_pc; 405 int device, function, nfunctions, ret; 406 const struct pci_quirkdata *qd; 407 pcireg_t id, bhlcr; 408 pcitag_t tag; 409 #ifdef __PCI_BUS_DEVORDER 410 char devs[32]; 411 int i; 412 #endif 413 414 #ifdef __PCI_BUS_DEVORDER 415 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 416 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 417 #else 418 for (device = 0; device < sc->sc_maxndevs; device++) 419 #endif 420 { 421 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 422 id = pci_conf_read(pc, tag, PCI_ID_REG); 423 424 /* Invalid vendor ID value? */ 425 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 426 continue; 427 /* XXX Not invalid, but we've done this ~forever. */ 428 if (PCI_VENDOR(id) == 0) 429 continue; 430 431 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 432 433 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 434 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 435 (qd != NULL && 436 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 437 nfunctions = 8; 438 else 439 nfunctions = 1; 440 441 for (function = 0; function < nfunctions; function++) { 442 tag = pci_make_tag(pc, sc->sc_bus, device, function); 443 ret = pci_probe_device(sc, tag, match, pap); 444 if (match != NULL && ret != 0) 445 return (ret); 446 } 447 } 448 return (0); 449 } 450 451 /* 452 * Power Management Capability (Rev 2.2) 453 */ 454 455 int 456 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, int newstate) 457 { 458 int offset; 459 pcireg_t value, cap, now; 460 461 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 462 return (EOPNOTSUPP); 463 464 cap = value >> 16; 465 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 466 now = value & PCI_PMCSR_STATE_MASK; 467 value &= ~PCI_PMCSR_STATE_MASK; 468 switch (newstate) { 469 case PCI_PWR_D0: 470 if (now == PCI_PMCSR_STATE_D0) 471 return (0); 472 value |= PCI_PMCSR_STATE_D0; 473 break; 474 case PCI_PWR_D1: 475 if (now == PCI_PMCSR_STATE_D1) 476 return (0); 477 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) 478 return (EINVAL); 479 if (!(cap & PCI_PMCR_D1SUPP)) 480 return (EOPNOTSUPP); 481 value |= PCI_PMCSR_STATE_D1; 482 break; 483 case PCI_PWR_D2: 484 if (now == PCI_PMCSR_STATE_D2) 485 return (0); 486 if (now == PCI_PMCSR_STATE_D3) 487 return (EINVAL); 488 if (!(cap & PCI_PMCR_D2SUPP)) 489 return (EOPNOTSUPP); 490 value |= PCI_PMCSR_STATE_D2; 491 break; 492 case PCI_PWR_D3: 493 if (now == PCI_PMCSR_STATE_D3) 494 return (0); 495 value |= PCI_PMCSR_STATE_D3; 496 break; 497 default: 498 return (EINVAL); 499 } 500 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 501 DELAY(1000); 502 503 return (0); 504 } 505 506 int 507 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag) 508 { 509 int offset; 510 pcireg_t value; 511 512 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 513 return (PCI_PWR_D0); 514 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 515 value &= PCI_PMCSR_STATE_MASK; 516 switch (value) { 517 case PCI_PMCSR_STATE_D0: 518 return (PCI_PWR_D0); 519 case PCI_PMCSR_STATE_D1: 520 return (PCI_PWR_D1); 521 case PCI_PMCSR_STATE_D2: 522 return (PCI_PWR_D2); 523 case PCI_PMCSR_STATE_D3: 524 return (PCI_PWR_D3); 525 } 526 527 return (PCI_PWR_D0); 528 } 529