1 /* $NetBSD: pciconf.c,v 1.20 2002/11/27 02:53:10 simonb Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 /* 42 * To do: 43 * - Perform all data structure allocation dynamically, don't have 44 * statically-sized arrays ("oops, you lose because you have too 45 * many slots filled!") 46 * - Do this in 2 passes, with an MD hook to control the behavior: 47 * (1) Configure the bus (possibly including expansion 48 * ROMs. 49 * (2) Another pass to disable expansion ROMs if they're 50 * mapped (since you're not supposed to leave them 51 * mapped when you're not using them). 52 * This would facilitate MD code executing the expansion ROMs 53 * if necessary (possibly with an x86 emulator) to configure 54 * devices (e.g. VGA cards). 55 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration 56 * information around & be able to reconfigure on the fly 57 * - Deal with segments (See IA64 System Abstraction Layer) 58 * - Deal with subtractive bridges (& non-spec positive/subtractive decode) 59 * - Deal with ISA/VGA/VGA palette snooping 60 * - Deal with device capabilities on bridges 61 * - Worry about changing a bridge to/from transparency 62 * From thorpej (05/25/01) 63 * - Try to handle devices that are already configured (perhaps using that 64 * as a hint to where we put other devices) 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.20 2002/11/27 02:53:10 simonb Exp $"); 69 70 #include "opt_pci.h" 71 72 #include <sys/param.h> 73 #include <sys/extent.h> 74 #include <sys/queue.h> 75 #include <sys/systm.h> 76 #include <sys/malloc.h> 77 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pciconf.h> 80 #include <dev/pci/pcidevs.h> 81 82 int pci_conf_debug = 0; 83 84 #if !defined(MIN) 85 #define MIN(a,b) (((a)<(b))?(a):(b)) 86 #define MAX(a,b) (((a)>(b))?(a):(b)) 87 #endif 88 89 /* per-bus constants. */ 90 #define MAX_CONF_DEV 32 /* Arbitrary */ 91 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 92 #define MAX_CONF_IO (3 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 93 94 struct _s_pciconf_bus_t; /* Forward declaration */ 95 96 typedef struct _s_pciconf_dev_t { 97 int ipin; 98 int iline; 99 int min_gnt; 100 int max_lat; 101 int enable; 102 pcitag_t tag; 103 pci_chipset_tag_t pc; 104 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 105 } pciconf_dev_t; 106 107 typedef struct _s_pciconf_win_t { 108 pciconf_dev_t *dev; 109 int reg; /* 0 for busses */ 110 int align; 111 int prefetch; 112 u_int64_t size; 113 u_int64_t address; 114 } pciconf_win_t; 115 116 typedef struct _s_pciconf_bus_t { 117 int busno; 118 int next_busno; 119 int last_busno; 120 int max_mingnt; 121 int min_maxlat; 122 int cacheline_size; 123 int prefetch; 124 int fast_b2b; 125 int freq_66; 126 int def_ltim; 127 int max_ltim; 128 int bandwidth_used; 129 int swiz; 130 int io_32bit; 131 int pmem_64bit; 132 133 int ndevs; 134 pciconf_dev_t device[MAX_CONF_DEV]; 135 136 /* These should be sorted in order of decreasing size */ 137 int nmemwin; 138 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 139 int niowin; 140 pciconf_win_t pciiowin[MAX_CONF_IO]; 141 142 bus_size_t io_total; 143 bus_size_t mem_total; 144 bus_size_t pmem_total; 145 146 struct extent *ioext; 147 struct extent *memext; 148 struct extent *pmemext; 149 150 pci_chipset_tag_t pc; 151 struct _s_pciconf_bus_t *parent_bus; 152 } pciconf_bus_t; 153 154 static int probe_bus(pciconf_bus_t *); 155 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 156 static void set_busreg(pci_chipset_tag_t, pcitag_t, int, int, int); 157 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int); 158 static int setup_iowins(pciconf_bus_t *); 159 static int setup_memwins(pciconf_bus_t *); 160 static int configure_bridge(pciconf_dev_t *); 161 static int configure_bus(pciconf_bus_t *); 162 static u_int64_t pci_allocate_range(struct extent *, u_int64_t, int); 163 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 164 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 165 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 166 167 static void print_tag(pci_chipset_tag_t, pcitag_t); 168 169 static void 170 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 171 { 172 int bus, dev, func; 173 174 pci_decompose_tag(pc, tag, &bus, &dev, &func); 175 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 176 } 177 178 /************************************************************************/ 179 /************************************************************************/ 180 /*********************** Bus probing routines ***********************/ 181 /************************************************************************/ 182 /************************************************************************/ 183 static pciconf_win_t * 184 get_io_desc(pciconf_bus_t *pb, bus_size_t size) 185 { 186 int i, n; 187 188 n = pb->niowin; 189 for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--) 190 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 191 return &pb->pciiowin[i]; 192 } 193 194 static pciconf_win_t * 195 get_mem_desc(pciconf_bus_t *pb, bus_size_t size) 196 { 197 int i, n; 198 199 n = pb->nmemwin; 200 for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--) 201 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 202 return &pb->pcimemwin[i]; 203 } 204 205 /* 206 * Set up bus common stuff, then loop over devices & functions. 207 * If we find something, call pci_do_device_query()). 208 */ 209 static int 210 probe_bus(pciconf_bus_t *pb) 211 { 212 int device, maxdevs; 213 #ifdef __PCI_BUS_DEVORDER 214 char devs[32]; 215 int i; 216 #endif 217 218 maxdevs = pci_bus_maxdevs(pb->pc, pb->busno); 219 pb->ndevs = 0; 220 pb->niowin = 0; 221 pb->nmemwin = 0; 222 pb->freq_66 = 1; 223 pb->fast_b2b = 1; 224 pb->prefetch = 1; 225 pb->max_mingnt = 0; /* we are looking for the maximum */ 226 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 227 pb->bandwidth_used = 0; 228 229 #ifdef __PCI_BUS_DEVORDER 230 pci_bus_devorder(pb->pc, pb->busno, devs); 231 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) { 232 #else 233 for (device = 0; device < maxdevs; device++) { 234 #endif 235 pcitag_t tag; 236 pcireg_t id, bhlcr; 237 int function, nfunction; 238 int confmode; 239 240 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 241 if (pci_conf_debug) { 242 print_tag(pb->pc, tag); 243 } 244 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 245 246 if (pci_conf_debug) { 247 printf("id=%x: Vendor=%x, Product=%x\n", 248 id, PCI_VENDOR(id),PCI_PRODUCT(id)); 249 } 250 /* Invalid vendor ID value? */ 251 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 252 continue; 253 254 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 255 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 256 for (function = 0 ; function < nfunction ; function++) { 257 tag = pci_make_tag(pb->pc, pb->busno, device, function); 258 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 259 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 260 continue; 261 if (pb->ndevs+1 < MAX_CONF_DEV) { 262 if (pci_conf_debug) { 263 print_tag(pb->pc, tag); 264 printf("Found dev 0x%04x 0x%04x -- " 265 "really probing.\n", 266 PCI_VENDOR(id), PCI_PRODUCT(id)); 267 } 268 #ifdef __HAVE_PCI_CONF_HOOK 269 confmode = pci_conf_hook(pb->pc, pb->busno, 270 device, function, id); 271 if (confmode == 0) 272 continue; 273 #else 274 /* 275 * Don't enable expansion ROMS -- some cards 276 * share address decoders between the EXPROM 277 * and PCI memory space, and enabling the ROM 278 * when not needed will cause all sorts of 279 * lossage. 280 */ 281 confmode = PCI_CONF_ALL & ~PCI_CONF_MAP_ROM; 282 #endif 283 if (pci_do_device_query(pb, tag, device, 284 function, confmode)) 285 return -1; 286 pb->ndevs++; 287 } 288 } 289 } 290 return 0; 291 } 292 293 static void 294 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 295 { 296 pb->busno = parent->next_busno; 297 pb->next_busno = pb->busno + 1; 298 } 299 300 static void 301 set_busreg(pci_chipset_tag_t pc, pcitag_t tag, int prim, int sec, int sub) 302 { 303 pcireg_t busreg; 304 305 busreg = prim << PCI_BRIDGE_BUS_PRIMARY_SHIFT; 306 busreg |= sec << PCI_BRIDGE_BUS_SECONDARY_SHIFT; 307 busreg |= sub << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 308 pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG, busreg); 309 } 310 311 static pciconf_bus_t * 312 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 313 { 314 pciconf_bus_t *pb; 315 pcireg_t io, pmem; 316 pciconf_win_t *pi, *pm; 317 318 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 319 if (!pb) 320 panic("Unable to allocate memory for PCI configuration."); 321 322 pb->cacheline_size = parent->cacheline_size; 323 pb->parent_bus = parent; 324 alloc_busno(parent, pb); 325 326 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 0xff); 327 328 pb->swiz = parent->swiz + dev; 329 330 pb->ioext = NULL; 331 pb->memext = NULL; 332 pb->pmemext = NULL; 333 pb->pc = parent->pc; 334 pb->io_total = pb->mem_total = pb->pmem_total = 0; 335 336 pb->io_32bit = 0; 337 if (parent->io_32bit) { 338 io = pci_conf_read(parent->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 339 if (PCI_BRIDGE_IO_32BITS(io)) { 340 pb->io_32bit = 1; 341 } 342 } 343 344 pb->pmem_64bit = 0; 345 if (parent->pmem_64bit) { 346 pmem = pci_conf_read(parent->pc, pd->tag, 347 PCI_BRIDGE_PREFETCHMEM_REG); 348 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) { 349 pb->pmem_64bit = 1; 350 } 351 } 352 353 if (probe_bus(pb)) { 354 printf("Failed to probe bus %d\n", pb->busno); 355 goto err; 356 } 357 358 /* We have found all subordinate busses now, reprogram busreg. */ 359 pb->last_busno = pb->next_busno-1; 360 parent->next_busno = pb->next_busno; 361 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 362 pb->last_busno); 363 if (pci_conf_debug) 364 printf("PCI bus bridge (parent %d) covers busses %d-%d\n", 365 parent->busno, pb->busno, pb->last_busno); 366 367 if (pb->io_total > 0) { 368 if (parent->niowin >= MAX_CONF_IO) { 369 printf("pciconf: too many I/O windows\n"); 370 goto err; 371 } 372 pb->io_total |= 0xfff; /* Round up */ 373 pi = get_io_desc(parent, pb->io_total); 374 pi->dev = pd; 375 pi->reg = 0; 376 pi->size = pb->io_total; 377 pi->align = 0x1000; /* 4K alignment */ 378 pi->prefetch = 0; 379 parent->niowin++; 380 parent->io_total += pb->io_total; 381 } 382 383 if (pb->mem_total > 0) { 384 if (parent->nmemwin >= MAX_CONF_MEM) { 385 printf("pciconf: too many MEM windows\n"); 386 goto err; 387 } 388 pb->mem_total |= 0xfffff; /* Round up */ 389 pm = get_mem_desc(parent, pb->mem_total); 390 pm->dev = pd; 391 pm->reg = 0; 392 pm->size = pb->mem_total; 393 pm->align = 0x100000; /* 1M alignment */ 394 pm->prefetch = 0; 395 parent->nmemwin++; 396 parent->mem_total += pb->mem_total; 397 } 398 399 if (pb->pmem_total > 0) { 400 if (parent->nmemwin >= MAX_CONF_MEM) { 401 printf("pciconf: too many MEM windows\n"); 402 goto err; 403 } 404 pb->pmem_total |= 0xfffff; /* Round up */ 405 pm = get_mem_desc(parent, pb->pmem_total); 406 pm->dev = pd; 407 pm->reg = 0; 408 pm->size = pb->pmem_total; 409 pm->align = 0x100000; /* 1M alignment */ 410 pm->prefetch = 1; 411 parent->nmemwin++; 412 parent->pmem_total += pb->pmem_total; 413 } 414 415 return pb; 416 err: 417 free(pb, M_DEVBUF); 418 return NULL; 419 } 420 421 static int 422 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, int mode) 423 { 424 pciconf_dev_t *pd; 425 pciconf_win_t *pi, *pm; 426 pcireg_t class, cmd, icr, bar, mask, bar64, mask64; 427 u_int64_t size; 428 int br, width; 429 430 pd = &pb->device[pb->ndevs]; 431 pd->pc = pb->pc; 432 pd->tag = tag; 433 pd->ppb = NULL; 434 pd->enable = mode; 435 436 class = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 437 438 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 439 440 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE) { 441 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 442 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 443 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 444 } else if (pci_conf_debug) { 445 print_tag(pb->pc, tag); 446 printf("device is a bridge; not clearing enables\n"); 447 } 448 449 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 450 pb->fast_b2b = 0; 451 452 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 453 pb->freq_66 = 0; 454 455 if ( (PCI_CLASS(class) == PCI_CLASS_BRIDGE) 456 && (PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI)) { 457 pd->ppb = query_bus(pb, pd, dev); 458 if (pd->ppb == NULL) 459 return -1; 460 return 0; 461 } 462 463 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 464 pd->ipin = PCI_INTERRUPT_PIN(icr); 465 pd->iline = PCI_INTERRUPT_LINE(icr); 466 pd->min_gnt = PCI_MIN_GNT(icr); 467 pd->max_lat = PCI_MAX_LAT(icr); 468 if (pd->iline || pd->ipin) { 469 pci_conf_interrupt(pb->pc, pb->busno, dev, pd->ipin, pb->swiz, 470 &pd->iline); 471 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 472 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 473 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 474 } 475 476 if (pd->min_gnt != 0 || pd->max_lat != 0) { 477 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 478 pb->max_mingnt = pd->min_gnt; 479 480 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 481 pb->min_maxlat = pd->max_lat; 482 483 pb->bandwidth_used += pd->min_gnt * 4000000 / 484 (pd->min_gnt + pd->max_lat); 485 } 486 487 width = 4; 488 for (br = PCI_MAPREG_START; br < PCI_MAPREG_END; br += width) { 489 #if 0 490 /* XXX Should only ignore if IDE not in legacy mode? */ 491 if (PCI_CLASS(class) == PCI_CLASS_MASS_STORAGE && 492 PCI_SUBCLASS(class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 493 break; 494 } 495 #endif 496 bar = pci_conf_read(pb->pc, tag, br); 497 pci_conf_write(pb->pc, tag, br, 0xffffffff); 498 mask = pci_conf_read(pb->pc, tag, br); 499 pci_conf_write(pb->pc, tag, br, bar); 500 width = 4; 501 502 if ( (mode & PCI_CONF_MAP_IO) 503 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO)) { 504 /* 505 * Upper 16 bits must be one. Devices may hardwire 506 * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. 507 */ 508 mask |= 0xffff0000; 509 510 size = PCI_MAPREG_IO_SIZE(mask); 511 if (size == 0) { 512 if (pci_conf_debug) { 513 print_tag(pb->pc, tag); 514 printf("I/O BAR 0x%x is void\n", br); 515 } 516 continue; 517 } 518 519 if (pb->niowin >= MAX_CONF_IO) { 520 printf("pciconf: too many I/O windows\n"); 521 return -1; 522 } 523 524 pi = get_io_desc(pb, size); 525 pi->dev = pd; 526 pi->reg = br; 527 pi->size = (u_int64_t) size; 528 pi->align = 4; 529 pi->prefetch = 0; 530 if (pci_conf_debug) { 531 print_tag(pb->pc, tag); 532 printf("Register 0x%x, I/O size %llu\n", 533 br, pi->size); 534 } 535 pb->niowin++; 536 pb->io_total += size; 537 } else if ((mode & PCI_CONF_MAP_MEM) 538 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) { 539 switch (PCI_MAPREG_MEM_TYPE(mask)) { 540 case PCI_MAPREG_MEM_TYPE_32BIT: 541 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 542 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 543 break; 544 case PCI_MAPREG_MEM_TYPE_64BIT: 545 bar64 = pci_conf_read(pb->pc, tag, br + 4); 546 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 547 mask64 = pci_conf_read(pb->pc, tag, br + 4); 548 pci_conf_write(pb->pc, tag, br + 4, bar64); 549 size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( 550 (((u_int64_t) mask64) << 32) | mask); 551 width = 8; 552 break; 553 default: 554 print_tag(pb->pc, tag); 555 printf("reserved mapping type 0x%x\n", 556 PCI_MAPREG_MEM_TYPE(mask)); 557 continue; 558 } 559 560 if (size == 0) { 561 if (pci_conf_debug) { 562 print_tag(pb->pc, tag); 563 printf("MEM%d BAR 0x%x is void\n", 564 PCI_MAPREG_MEM_TYPE(mask) == 565 PCI_MAPREG_MEM_TYPE_64BIT ? 566 64 : 32, br); 567 } 568 continue; 569 } else { 570 if (pci_conf_debug) { 571 print_tag(pb->pc, tag); 572 printf("MEM%d BAR 0x%x has size %lx\n", 573 PCI_MAPREG_MEM_TYPE(mask) == 574 PCI_MAPREG_MEM_TYPE_64BIT ? 575 64 : 32, br, (unsigned long)size); 576 } 577 } 578 579 if (pb->nmemwin >= MAX_CONF_MEM) { 580 printf("pciconf: too many memory windows\n"); 581 return -1; 582 } 583 584 pm = get_mem_desc(pb, size); 585 pm->dev = pd; 586 pm->reg = br; 587 pm->size = size; 588 pm->align = 4; 589 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 590 if (pci_conf_debug) { 591 print_tag(pb->pc, tag); 592 printf("Register 0x%x, memory size %llu\n", 593 br, pm->size); 594 } 595 pb->nmemwin++; 596 if (pm->prefetch) { 597 pb->pmem_total += size; 598 } else { 599 pb->mem_total += size; 600 } 601 } 602 } 603 604 if (mode & PCI_CONF_MAP_ROM) { 605 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 606 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 607 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 608 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar); 609 610 if (mask != 0 && mask != 0xffffffff) { 611 if (pb->nmemwin >= MAX_CONF_MEM) { 612 printf("pciconf: too many memory windows\n"); 613 return -1; 614 } 615 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 616 617 pm = get_mem_desc(pb, size); 618 pm->dev = pd; 619 pm->reg = PCI_MAPREG_ROM; 620 pm->size = size; 621 pm->align = 4; 622 pm->prefetch = 1; 623 if (pci_conf_debug) { 624 print_tag(pb->pc, tag); 625 printf("Expansion ROM memory size %llu\n", pm->size); 626 } 627 pb->nmemwin++; 628 pb->pmem_total += size; 629 } 630 } else { 631 /* Ensure ROM is disabled */ 632 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 633 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 634 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 635 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 636 bar & ~PCI_MAPREG_ROM_ENABLE); 637 } 638 639 return 0; 640 } 641 642 /************************************************************************/ 643 /************************************************************************/ 644 /******************** Bus configuration routines ********************/ 645 /************************************************************************/ 646 /************************************************************************/ 647 static u_int64_t 648 pci_allocate_range(struct extent *ex, u_int64_t amt, int align) 649 { 650 int r; 651 u_long addr; 652 653 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr); 654 if (r) { 655 addr = (u_long) -1; 656 printf("extent_alloc(%p, %llu, %d) returned %d\n", 657 ex, amt, align, r); 658 extent_print(ex); 659 } 660 return (pcireg_t) addr; 661 } 662 663 static int 664 setup_iowins(pciconf_bus_t *pb) 665 { 666 pciconf_win_t *pi; 667 pciconf_dev_t *pd; 668 669 for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) { 670 if (pi->size == 0) 671 continue; 672 673 pd = pi->dev; 674 pi->address = pci_allocate_range(pb->ioext, pi->size, 675 pi->align); 676 if (pi->address == -1) { 677 print_tag(pd->pc, pd->tag); 678 printf("Failed to allocate PCI I/O space (%llu req)\n", 679 pi->size); 680 return -1; 681 } 682 if (!pb->io_32bit && pi->address > 0xFFFF) { 683 pi->address = 0; 684 pd->enable = 0; 685 } 686 if (pd->ppb && pi->reg == 0) { 687 pd->ppb->ioext = extent_create("pciconf", pi->address, 688 pi->address + pi->size, M_DEVBUF, NULL, 0, 689 EX_NOWAIT); 690 if (pd->ppb->ioext == NULL) { 691 print_tag(pd->pc, pd->tag); 692 printf("Failed to alloc I/O ext. for bus %d\n", 693 pd->ppb->busno); 694 return -1; 695 } 696 continue; 697 } 698 pd->enable |= PCI_CONF_ENABLE_IO; 699 if (pci_conf_debug) { 700 print_tag(pd->pc, pd->tag); 701 printf("Putting %llu I/O bytes @ %#llx (reg %x)\n", 702 pi->size, pi->address, pi->reg); 703 } 704 pci_conf_write(pd->pc, pd->tag, pi->reg, 705 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 706 } 707 return 0; 708 } 709 710 static int 711 setup_memwins(pciconf_bus_t *pb) 712 { 713 pciconf_win_t *pm; 714 pciconf_dev_t *pd; 715 pcireg_t base; 716 struct extent *ex; 717 718 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 719 if (pm->size == 0) 720 continue; 721 722 pd = pm->dev; 723 ex = (pm->prefetch) ? pb->pmemext : pb->memext; 724 pm->address = pci_allocate_range(ex, pm->size, pm->align); 725 if (pm->address == -1) { 726 print_tag(pd->pc, pd->tag); 727 printf( 728 "Failed to allocate PCI memory space (%llu req)\n", 729 pm->size); 730 return -1; 731 } 732 if (pd->ppb && pm->reg == 0) { 733 ex = extent_create("pciconf", pm->address, 734 pm->address + pm->size, M_DEVBUF, NULL, 0, 735 EX_NOWAIT); 736 if (ex == NULL) { 737 print_tag(pd->pc, pd->tag); 738 printf("Failed to alloc MEM ext. for bus %d\n", 739 pd->ppb->busno); 740 return -1; 741 } 742 if (pm->prefetch) { 743 pd->ppb->pmemext = ex; 744 } else { 745 pd->ppb->memext = ex; 746 } 747 continue; 748 } 749 if (pm->prefetch && !pb->pmem_64bit && 750 pm->address > 0xFFFFFFFFULL) { 751 pm->address = 0; 752 pd->enable = 0; 753 } else { 754 pd->enable |= PCI_CONF_ENABLE_MEM; 755 } 756 if (pm->reg != PCI_MAPREG_ROM) { 757 if (pci_conf_debug) { 758 print_tag(pd->pc, pd->tag); 759 printf( 760 "Putting %llu MEM bytes @ %#llx (reg %x)\n", 761 pm->size, pm->address, pm->reg); 762 } 763 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 764 base = PCI_MAPREG_MEM_ADDR(pm->address) | 765 PCI_MAPREG_MEM_TYPE(base); 766 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 767 if (PCI_MAPREG_MEM_TYPE(base) == 768 PCI_MAPREG_MEM_TYPE_64BIT) { 769 base = (pcireg_t) 770 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 771 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 772 base); 773 } 774 } 775 } 776 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 777 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 778 pd = pm->dev; 779 if (pci_conf_debug) { 780 print_tag(pd->pc, pd->tag); 781 printf( 782 "Putting %llu ROM bytes @ %#llx (reg %x)\n", 783 pm->size, pm->address, pm->reg); 784 } 785 base = (pcireg_t) (pm->address | PCI_MAPREG_ROM_ENABLE); 786 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 787 } 788 } 789 return 0; 790 } 791 792 /* 793 * Configure I/O, memory, and prefetcable memory spaces, then make 794 * a call to configure_bus(). 795 */ 796 static int 797 configure_bridge(pciconf_dev_t *pd) 798 { 799 unsigned long io_base, io_limit, mem_base, mem_limit; 800 pciconf_bus_t *pb; 801 pcireg_t io, iohigh, mem, cmd; 802 int rv; 803 804 pb = pd->ppb; 805 /* Configure I/O base & limit*/ 806 if (pb->ioext) { 807 io_base = pb->ioext->ex_start; 808 io_limit = pb->ioext->ex_end; 809 } else { 810 io_base = 0x1000; /* 4K */ 811 io_limit = 0x0000; 812 } 813 if (pb->io_32bit) { 814 iohigh = 815 ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) | 816 ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT); 817 } else { 818 if (io_limit > 0xFFFF) { 819 printf("Bus %d bridge does not support 32-bit I/O. ", 820 pb->busno); 821 printf("Disabling I/O accesses\n"); 822 io_base = 0x1000; /* 4K */ 823 io_limit = 0x0000; 824 } 825 iohigh = 0; 826 } 827 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG) & 828 (PCI_BRIDGE_STATIO_STATUS_MASK << PCI_BRIDGE_STATIO_STATUS_SHIFT); 829 io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK) 830 << PCI_BRIDGE_STATIO_IOBASE_SHIFT); 831 io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK) 832 << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT); 833 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 834 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 835 836 /* Configure mem base & limit */ 837 if (pb->memext) { 838 mem_base = pb->memext->ex_start; 839 mem_limit = pb->memext->ex_end; 840 } else { 841 mem_base = 0x100000; /* 1M */ 842 mem_limit = 0x000000; 843 } 844 #if ULONG_MAX > 0xffffffff 845 if (mem_limit > 0xFFFFFFFFULL) { 846 printf("Bus %d bridge MEM range out of range. ", pb->busno); 847 printf("Disabling MEM accesses\n"); 848 mem_base = 0x100000; /* 1M */ 849 mem_limit = 0x000000; 850 } 851 #endif 852 mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK) 853 << PCI_BRIDGE_MEMORY_BASE_SHIFT); 854 mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK) 855 << PCI_BRIDGE_MEMORY_LIMIT_SHIFT); 856 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 857 858 /* Configure prefetchable mem base & limit */ 859 if (pb->pmemext) { 860 mem_base = pb->pmemext->ex_start; 861 mem_limit = pb->pmemext->ex_end; 862 } else { 863 mem_base = 0x100000; /* 1M */ 864 mem_limit = 0x000000; 865 } 866 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG); 867 #if ULONG_MAX > 0xffffffff 868 if (!PCI_BRIDGE_PREFETCHMEM_64BITS(mem) && mem_limit > 0xFFFFFFFFULL) { 869 printf("Bus %d bridge does not support 64-bit PMEM. ", 870 pb->busno); 871 printf("Disabling prefetchable-MEM accesses\n"); 872 mem_base = 0x100000; /* 1M */ 873 mem_limit = 0x000000; 874 } 875 #endif 876 mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) 877 << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT); 878 mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) 879 << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT); 880 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem); 881 /* 882 * XXX -- 64-bit systems need a lot more than just this... 883 */ 884 if (sizeof(u_long) > 4) { 885 mem_base = (int64_t) mem_base >> 32; 886 mem_limit = (int64_t) mem_limit >> 32; 887 } 888 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG, 889 mem_base & 0xffffffff); 890 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG, 891 mem_limit & 0xffffffff); 892 893 rv = configure_bus(pb); 894 895 if (pb->ioext) 896 extent_destroy(pb->ioext); 897 if (pb->memext) 898 extent_destroy(pb->memext); 899 if (pb->pmemext) 900 extent_destroy(pb->pmemext); 901 if (rv == 0) { 902 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 903 cmd &= PCI_BRIDGE_CONTROL_MASK; 904 cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR) 905 << PCI_BRIDGE_CONTROL_SHIFT; 906 if (pb->fast_b2b) { 907 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B 908 << PCI_BRIDGE_CONTROL_SHIFT; 909 } 910 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 911 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 912 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 913 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 914 } 915 916 return rv; 917 } 918 919 /* 920 * Calculate latency values, allocate I/O and MEM segments, then set them 921 * up. If a PCI-PCI bridge is found, configure the bridge separately, 922 * which will cause a recursive call back here. 923 */ 924 static int 925 configure_bus(pciconf_bus_t *pb) 926 { 927 pciconf_dev_t *pd; 928 int def_ltim, max_ltim, band, bus_mhz; 929 930 if (pb->ndevs == 0) { 931 if (pci_conf_debug) 932 printf("PCI bus %d - no devices\n", pb->busno); 933 return (1); 934 } 935 bus_mhz = pb->freq_66 ? 66 : 33; 936 max_ltim = pb->max_mingnt * bus_mhz / 4; /* cvt to cycle count */ 937 band = 40000000; /* 0.25us cycles/sec */ 938 if (band < pb->bandwidth_used) { 939 printf("PCI bus %d: Warning: Total bandwidth exceeded!?\n", 940 pb->busno); 941 def_ltim = -1; 942 } else { 943 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 944 if (def_ltim > pb->min_maxlat) 945 def_ltim = pb->min_maxlat; 946 def_ltim = def_ltim * bus_mhz / 4; 947 } 948 def_ltim = (def_ltim + 7) & ~7; 949 max_ltim = (max_ltim + 7) & ~7; 950 951 pb->def_ltim = MIN( def_ltim, 255 ); 952 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 ); 953 954 /* 955 * Now we have what we need to initialize the devices. 956 * It would probably be better if we could allocate all of these 957 * for all busses at once, but "not right now". First, get a list 958 * of free memory ranges from the m.d. system. 959 */ 960 if (setup_iowins(pb) || setup_memwins(pb)) { 961 printf("PCI bus configuration failed: "); 962 printf("unable to assign all I/O and memory ranges."); 963 return -1; 964 } 965 966 /* 967 * Configure the latency for the devices, and enable them. 968 */ 969 for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) { 970 pcireg_t cmd, class, misc; 971 int ltim; 972 973 if (pci_conf_debug) { 974 print_tag(pd->pc, pd->tag); 975 printf("Configuring device.\n"); 976 } 977 class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 978 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 979 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 980 cmd |= PCI_COMMAND_SERR_ENABLE | PCI_COMMAND_PARITY_ENABLE; 981 if (pb->fast_b2b) 982 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 983 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 984 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) { 985 if (pd->enable & PCI_CONF_ENABLE_IO) 986 cmd |= PCI_COMMAND_IO_ENABLE; 987 if (pd->enable & PCI_CONF_ENABLE_MEM) 988 cmd |= PCI_COMMAND_MEM_ENABLE; 989 if (pd->enable & PCI_CONF_ENABLE_BM) 990 cmd |= PCI_COMMAND_MASTER_ENABLE; 991 ltim = pd->min_gnt * bus_mhz / 4; 992 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 993 } else { 994 cmd |= PCI_COMMAND_MASTER_ENABLE; 995 ltim = MIN (pb->def_ltim, pb->max_ltim); 996 } 997 if (!(pd->enable)) { 998 print_tag(pd->pc, pd->tag); 999 printf("Disabled due to lack of resources.\n"); 1000 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 1001 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 1002 } 1003 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 1004 1005 misc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 1006 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 1007 misc |= (ltim & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT; 1008 misc |= ((pb->cacheline_size >> 2) & PCI_CACHELINE_MASK) << 1009 PCI_CACHELINE_SHIFT; 1010 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 1011 1012 if (pd->ppb) { 1013 if (configure_bridge(pd) < 0) 1014 return -1; 1015 continue; 1016 } 1017 } 1018 1019 if (pci_conf_debug) { 1020 printf("PCI bus %d configured\n", pb->busno); 1021 } 1022 1023 return 0; 1024 } 1025 1026 /* 1027 * Let's configure the PCI bus. 1028 * This consists of basically scanning for all existing devices, 1029 * identifying their needs, and then making another pass over them 1030 * to set: 1031 * 1. I/O addresses 1032 * 2. Memory addresses (Prefetchable and not) 1033 * 3. PCI command register 1034 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 1035 * Header type, Latency timer, Cache line size) register 1036 * 1037 * The command register is set to enable fast back-to-back transactions 1038 * if the host bridge says it can handle it. We also configure 1039 * Master Enable, SERR enable, parity enable, and (if this is not a 1040 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 1041 * will not report some I/O space. 1042 * 1043 * The latency is computed to be a "fair share" of the bus bandwidth. 1044 * The bus bandwidth variable is initialized to the number of PCI cycles 1045 * in one second. The number of cycles taken for one transaction by each 1046 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 1047 * Care is taken to ensure that the latency timer won't be set such that 1048 * it would exceed the critical time for any device. 1049 * 1050 * This is complicated somewhat due to the presence of bridges. PCI-PCI 1051 * bridges are probed and configured recursively. 1052 */ 1053 int 1054 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext, 1055 struct extent *memext, struct extent *pmemext, int firstbus, 1056 int cacheline_size) 1057 { 1058 pciconf_bus_t *pb; 1059 int rv; 1060 1061 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 1062 pb->busno = firstbus; 1063 pb->next_busno = pb->busno + 1; 1064 pb->last_busno = 255; 1065 pb->cacheline_size = cacheline_size; 1066 pb->parent_bus = NULL; 1067 pb->swiz = 0; 1068 pb->io_32bit = 1; 1069 pb->pmem_64bit = 0; 1070 pb->ioext = ioext; 1071 pb->memext = memext; 1072 if (pmemext == NULL) { 1073 pb->pmemext = memext; 1074 } else { 1075 pb->pmemext = pmemext; 1076 } 1077 pb->pc = pc; 1078 pb->io_total = pb->mem_total = pb->pmem_total = 0; 1079 1080 rv = probe_bus(pb); 1081 pb->last_busno = pb->next_busno-1; 1082 if (rv == 0) { 1083 rv = configure_bus(pb); 1084 } 1085 1086 /* 1087 * All done! 1088 */ 1089 free(pb, M_DEVBUF); 1090 return rv; 1091 } 1092