1 /* $NetBSD: pciide_common.c,v 1.48 2010/11/17 19:36:54 dholland Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 30 /* 31 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. All advertising materials mentioning features or use of this software 42 * must display the following acknowledgement: 43 * This product includes software developed by Christopher G. Demetriou 44 * for the NetBSD Project. 45 * 4. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 52 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 53 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 57 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 /* 61 * PCI IDE controller driver. 62 * 63 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 64 * sys/dev/pci/ppb.c, revision 1.16). 65 * 66 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 67 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 68 * 5/16/94" from the PCI SIG. 69 * 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.48 2010/11/17 19:36:54 dholland Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/malloc.h> 77 78 #include <dev/pci/pcireg.h> 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcidevs.h> 81 #include <dev/pci/pciidereg.h> 82 #include <dev/pci/pciidevar.h> 83 84 #include <dev/ic/wdcreg.h> 85 86 #ifdef ATADEBUG 87 int atadebug_pciide_mask = 0; 88 #endif 89 90 #if NATA_DMA 91 static const char dmaerrfmt[] = 92 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; 93 #endif 94 95 /* Default product description for devices not known from this controller */ 96 const struct pciide_product_desc default_product_desc = { 97 0, 98 0, 99 "Generic PCI IDE controller", 100 default_chip_map, 101 }; 102 103 const struct pciide_product_desc * 104 pciide_lookup_product(pcireg_t id, const struct pciide_product_desc *pp) 105 { 106 for (; pp->chip_map != NULL; pp++) 107 if (PCI_PRODUCT(id) == pp->ide_product) 108 break; 109 110 if (pp->chip_map == NULL) 111 return NULL; 112 return pp; 113 } 114 115 void 116 pciide_common_attach(struct pciide_softc *sc, struct pci_attach_args *pa, const struct pciide_product_desc *pp) 117 { 118 pci_chipset_tag_t pc = pa->pa_pc; 119 pcitag_t tag = pa->pa_tag; 120 #if NATA_DMA 121 pcireg_t csr; 122 #endif 123 char devinfo[256]; 124 const char *displaydev; 125 126 aprint_naive(": disk controller\n"); 127 128 sc->sc_pci_id = pa->pa_id; 129 if (pp == NULL) { 130 /* should only happen for generic pciide devices */ 131 sc->sc_pp = &default_product_desc; 132 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 133 displaydev = devinfo; 134 } else { 135 sc->sc_pp = pp; 136 displaydev = sc->sc_pp->ide_name; 137 } 138 139 /* if displaydev == NULL, printf is done in chip-specific map */ 140 if (displaydev) 141 aprint_normal(": %s (rev. 0x%02x)\n", displaydev, 142 PCI_REVISION(pa->pa_class)); 143 else 144 aprint_normal("\n"); 145 146 sc->sc_pc = pa->pa_pc; 147 sc->sc_tag = pa->pa_tag; 148 149 #if NATA_DMA 150 /* Set up DMA defaults; these might be adjusted by chip_map. */ 151 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 152 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 153 #endif 154 155 #ifdef ATADEBUG 156 if (atadebug_pciide_mask & DEBUG_PROBE) 157 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 158 #endif 159 sc->sc_pp->chip_map(sc, pa); 160 161 #if NATA_DMA 162 if (sc->sc_dma_ok) { 163 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 164 csr |= PCI_COMMAND_MASTER_ENABLE; 165 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 166 } 167 #endif 168 ATADEBUG_PRINT(("pciide: command/status register=%x\n", 169 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 170 } 171 172 int 173 pciide_common_detach(struct pciide_softc *sc, int flags) 174 { 175 struct pciide_channel *cp; 176 struct ata_channel *wdc_cp; 177 struct wdc_regs *wdr; 178 int channel, drive; 179 int rv; 180 181 rv = wdcdetach(sc->sc_wdcdev.sc_atac.atac_dev, flags); 182 if (rv) 183 return rv; 184 185 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 186 channel++) { 187 cp = &sc->pciide_channels[channel]; 188 wdc_cp = &cp->ata_channel; 189 wdr = CHAN_TO_WDC_REGS(wdc_cp); 190 191 if (wdc_cp->ch_flags & ATACH_DISABLED) 192 continue; 193 194 if (wdr->cmd_ios != 0) 195 bus_space_unmap(wdr->cmd_iot, 196 wdr->cmd_baseioh, wdr->cmd_ios); 197 if (cp->compat != 0) { 198 if (wdr->ctl_ios != 0) 199 bus_space_unmap(wdr->ctl_iot, 200 wdr->ctl_ioh, wdr->ctl_ios); 201 } else { 202 if (cp->ctl_ios != 0) 203 bus_space_unmap(wdr->ctl_iot, 204 cp->ctl_baseioh, cp->ctl_ios); 205 } 206 207 for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) { 208 #if NATA_DMA 209 pciide_dma_table_teardown(sc, channel, drive); 210 #endif 211 } 212 213 free(cp->ata_channel.ch_queue, M_DEVBUF); 214 cp->ata_channel.atabus = NULL; 215 } 216 217 #if NATA_DMA 218 if (sc->sc_dma_ios != 0) 219 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, sc->sc_dma_ios); 220 if (sc->sc_ba5_ss != 0) 221 bus_space_unmap(sc->sc_ba5_st, sc->sc_ba5_sh, sc->sc_ba5_ss); 222 #endif 223 224 return 0; 225 } 226 227 int 228 pciide_detach(device_t self, int flags) 229 { 230 struct pciide_softc *sc = device_private(self); 231 struct pciide_channel *cp; 232 int channel; 233 #ifndef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH 234 bool has_compat_chan; 235 236 has_compat_chan = false; 237 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 238 channel++) { 239 cp = &sc->pciide_channels[channel]; 240 if (cp->compat != 0) { 241 has_compat_chan = true; 242 } 243 } 244 245 if (has_compat_chan != false) 246 return EBUSY; 247 #endif 248 249 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 250 channel++) { 251 cp = &sc->pciide_channels[channel]; 252 if (cp->compat != 0) 253 if (cp->ih != NULL) 254 pciide_unmap_compat_intr(sc->sc_pc, cp, channel); 255 } 256 257 if (sc->sc_pci_ih != NULL) 258 pci_intr_disestablish(sc->sc_pc, sc->sc_pci_ih); 259 260 return pciide_common_detach(sc, flags); 261 } 262 263 /* tell whether the chip is enabled or not */ 264 int 265 pciide_chipen(struct pciide_softc *sc, struct pci_attach_args *pa) 266 { 267 pcireg_t csr; 268 269 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 270 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 271 PCI_COMMAND_STATUS_REG); 272 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 273 "device disabled (at %s)\n", 274 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 275 "device" : "bridge"); 276 return 0; 277 } 278 return 1; 279 } 280 281 void 282 pciide_mapregs_compat(struct pci_attach_args *pa, struct pciide_channel *cp, int compatchan) 283 { 284 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 285 struct ata_channel *wdc_cp = &cp->ata_channel; 286 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 287 int i; 288 289 cp->compat = 1; 290 291 wdr->cmd_iot = pa->pa_iot; 292 if (bus_space_map(wdr->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 293 PCIIDE_COMPAT_CMD_SIZE, 0, &wdr->cmd_baseioh) != 0) { 294 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 295 "couldn't map %s channel cmd regs\n", cp->name); 296 goto bad; 297 } 298 wdr->cmd_ios = PCIIDE_COMPAT_CMD_SIZE; 299 300 wdr->ctl_iot = pa->pa_iot; 301 if (bus_space_map(wdr->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 302 PCIIDE_COMPAT_CTL_SIZE, 0, &wdr->ctl_ioh) != 0) { 303 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 304 "couldn't map %s channel ctl regs\n", cp->name); 305 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios); 306 goto bad; 307 } 308 wdr->ctl_ios = PCIIDE_COMPAT_CTL_SIZE; 309 310 for (i = 0; i < WDC_NREG; i++) { 311 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 312 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 313 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 314 "couldn't subregion %s channel cmd regs\n", 315 cp->name); 316 goto bad; 317 } 318 } 319 wdc_init_shadow_regs(wdc_cp); 320 wdr->data32iot = wdr->cmd_iot; 321 wdr->data32ioh = wdr->cmd_iohs[0]; 322 return; 323 324 bad: 325 cp->ata_channel.ch_flags |= ATACH_DISABLED; 326 return; 327 } 328 329 void 330 pciide_mapregs_native(struct pci_attach_args *pa, 331 struct pciide_channel *cp, int (*pci_intr)(void *)) 332 { 333 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 334 struct ata_channel *wdc_cp = &cp->ata_channel; 335 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 336 const char *intrstr; 337 pci_intr_handle_t intrhandle; 338 int i; 339 340 cp->compat = 0; 341 342 if (sc->sc_pci_ih == NULL) { 343 if (pci_intr_map(pa, &intrhandle) != 0) { 344 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 345 "couldn't map native-PCI interrupt\n"); 346 goto bad; 347 } 348 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 349 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 350 intrhandle, IPL_BIO, pci_intr, sc); 351 if (sc->sc_pci_ih != NULL) { 352 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 353 "using %s for native-PCI interrupt\n", 354 intrstr ? intrstr : "unknown interrupt"); 355 } else { 356 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 357 "couldn't establish native-PCI interrupt"); 358 if (intrstr != NULL) 359 aprint_error(" at %s", intrstr); 360 aprint_error("\n"); 361 goto bad; 362 } 363 } 364 cp->ih = sc->sc_pci_ih; 365 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->ch_channel), 366 PCI_MAPREG_TYPE_IO, 0, 367 &wdr->cmd_iot, &wdr->cmd_baseioh, NULL, &wdr->cmd_ios) != 0) { 368 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 369 "couldn't map %s channel cmd regs\n", cp->name); 370 goto bad; 371 } 372 373 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->ch_channel), 374 PCI_MAPREG_TYPE_IO, 0, 375 &wdr->ctl_iot, &cp->ctl_baseioh, NULL, &cp->ctl_ios) != 0) { 376 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 377 "couldn't map %s channel ctl regs\n", cp->name); 378 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios); 379 goto bad; 380 } 381 /* 382 * In native mode, 4 bytes of I/O space are mapped for the control 383 * register, the control register is at offset 2. Pass the generic 384 * code a handle for only one byte at the right offset. 385 */ 386 if (bus_space_subregion(wdr->ctl_iot, cp->ctl_baseioh, 2, 1, 387 &wdr->ctl_ioh) != 0) { 388 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 389 "unable to subregion %s channel ctl regs\n", cp->name); 390 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios); 391 bus_space_unmap(wdr->cmd_iot, cp->ctl_baseioh, cp->ctl_ios); 392 goto bad; 393 } 394 395 for (i = 0; i < WDC_NREG; i++) { 396 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 397 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 398 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 399 "couldn't subregion %s channel cmd regs\n", 400 cp->name); 401 goto bad; 402 } 403 } 404 wdc_init_shadow_regs(wdc_cp); 405 wdr->data32iot = wdr->cmd_iot; 406 wdr->data32ioh = wdr->cmd_iohs[0]; 407 return; 408 409 bad: 410 cp->ata_channel.ch_flags |= ATACH_DISABLED; 411 return; 412 } 413 414 #if NATA_DMA 415 void 416 pciide_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 417 { 418 pcireg_t maptype; 419 bus_addr_t addr; 420 struct pciide_channel *pc; 421 int reg, chan; 422 bus_size_t size; 423 424 /* 425 * Map DMA registers 426 * 427 * Note that sc_dma_ok is the right variable to test to see if 428 * DMA can be done. If the interface doesn't support DMA, 429 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 430 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 431 * non-zero if the interface supports DMA and the registers 432 * could be mapped. 433 * 434 * XXX Note that despite the fact that the Bus Master IDE specs 435 * XXX say that "The bus master IDE function uses 16 bytes of IO 436 * XXX space," some controllers (at least the United 437 * XXX Microelectronics UM8886BF) place it in memory space. 438 */ 439 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 440 PCIIDE_REG_BUS_MASTER_DMA); 441 442 switch (maptype) { 443 case PCI_MAPREG_TYPE_IO: 444 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 445 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 446 &addr, NULL, NULL) == 0); 447 if (sc->sc_dma_ok == 0) { 448 aprint_verbose( 449 ", but unused (couldn't query registers)"); 450 break; 451 } 452 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 453 && addr >= 0x10000) { 454 sc->sc_dma_ok = 0; 455 aprint_verbose( 456 ", but unused (registers at unsafe address " 457 "%#lx)", (unsigned long)addr); 458 break; 459 } 460 /* FALLTHROUGH */ 461 462 case PCI_MAPREG_MEM_TYPE_32BIT: 463 sc->sc_dma_ok = (pci_mapreg_map(pa, 464 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 465 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, &sc->sc_dma_ios) 466 == 0); 467 sc->sc_dmat = pa->pa_dmat; 468 if (sc->sc_dma_ok == 0) { 469 aprint_verbose(", but unused (couldn't map registers)"); 470 } else { 471 sc->sc_wdcdev.dma_arg = sc; 472 sc->sc_wdcdev.dma_init = pciide_dma_init; 473 sc->sc_wdcdev.dma_start = pciide_dma_start; 474 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 475 } 476 477 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 478 PCIIDE_OPTIONS_NODMA) { 479 aprint_verbose( 480 ", but unused (forced off by config file)"); 481 sc->sc_dma_ok = 0; 482 } 483 break; 484 485 default: 486 sc->sc_dma_ok = 0; 487 aprint_verbose( 488 ", but unsupported register maptype (0x%x)", maptype); 489 } 490 491 if (sc->sc_dma_ok == 0) 492 return; 493 494 /* 495 * Set up the default handles for the DMA registers. 496 * Just reserve 32 bits for each handle, unless space 497 * doesn't permit it. 498 */ 499 for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) { 500 pc = &sc->pciide_channels[chan]; 501 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 502 size = 4; 503 if (size > (IDEDMA_SCH_OFFSET - reg)) 504 size = IDEDMA_SCH_OFFSET - reg; 505 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 506 IDEDMA_SCH_OFFSET * chan + reg, size, 507 &pc->dma_iohs[reg]) != 0) { 508 sc->sc_dma_ok = 0; 509 aprint_verbose(", but can't subregion offset %d " 510 "size %lu", reg, (u_long)size); 511 return; 512 } 513 } 514 } 515 } 516 #endif /* NATA_DMA */ 517 518 int 519 pciide_compat_intr(void *arg) 520 { 521 struct pciide_channel *cp = arg; 522 523 #ifdef DIAGNOSTIC 524 /* should only be called for a compat channel */ 525 if (cp->compat == 0) 526 panic("pciide compat intr called for non-compat chan %p", cp); 527 #endif 528 return (wdcintr(&cp->ata_channel)); 529 } 530 531 int 532 pciide_pci_intr(void *arg) 533 { 534 struct pciide_softc *sc = arg; 535 struct pciide_channel *cp; 536 struct ata_channel *wdc_cp; 537 int i, rv, crv; 538 539 rv = 0; 540 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 541 cp = &sc->pciide_channels[i]; 542 wdc_cp = &cp->ata_channel; 543 544 /* If a compat channel skip. */ 545 if (cp->compat) 546 continue; 547 /* if this channel not waiting for intr, skip */ 548 if ((wdc_cp->ch_flags & ATACH_IRQ_WAIT) == 0) 549 continue; 550 551 crv = wdcintr(wdc_cp); 552 if (crv == 0) 553 ; /* leave rv alone */ 554 else if (crv == 1) 555 rv = 1; /* claim the intr */ 556 else if (rv == 0) /* crv should be -1 in this case */ 557 rv = crv; /* if we've done no better, take it */ 558 } 559 return (rv); 560 } 561 562 #if NATA_DMA 563 void 564 pciide_channel_dma_setup(struct pciide_channel *cp) 565 { 566 int drive, s; 567 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 568 struct ata_drive_datas *drvp; 569 570 KASSERT(cp->ata_channel.ch_ndrive != 0); 571 572 for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) { 573 drvp = &cp->ata_channel.ch_drive[drive]; 574 /* If no drive, skip */ 575 if ((drvp->drive_flags & DRIVE) == 0) 576 continue; 577 /* setup DMA if needed */ 578 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 579 (drvp->drive_flags & DRIVE_UDMA) == 0) || 580 sc->sc_dma_ok == 0) { 581 s = splbio(); 582 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 583 splx(s); 584 continue; 585 } 586 if (pciide_dma_table_setup(sc, cp->ata_channel.ch_channel, 587 drive) != 0) { 588 /* Abort DMA setup */ 589 s = splbio(); 590 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 591 splx(s); 592 continue; 593 } 594 } 595 } 596 597 #define NIDEDMA_TABLES(sc) \ 598 (MAXPHYS/(min((sc)->sc_dma_maxsegsz, PAGE_SIZE)) + 1) 599 600 int 601 pciide_dma_table_setup(struct pciide_softc *sc, int channel, int drive) 602 { 603 int error; 604 const bus_size_t dma_table_size = 605 sizeof(struct idedma_table) * NIDEDMA_TABLES(sc); 606 struct pciide_dma_maps *dma_maps = 607 &sc->pciide_channels[channel].dma_maps[drive]; 608 609 /* If table was already allocated, just return */ 610 if (dma_maps->dma_table) 611 return 0; 612 613 /* Allocate memory for the DMA tables and map it */ 614 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 615 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &dma_maps->dmamap_table_seg, 616 1, &dma_maps->dmamap_table_nseg, BUS_DMA_NOWAIT)) != 0) { 617 aprint_error(dmaerrfmt, 618 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 619 "allocate", drive, error); 620 return error; 621 } 622 if ((error = bus_dmamem_map(sc->sc_dmat, &dma_maps->dmamap_table_seg, 623 dma_maps->dmamap_table_nseg, dma_table_size, 624 (void **)&dma_maps->dma_table, 625 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 626 aprint_error(dmaerrfmt, 627 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 628 "map", drive, error); 629 return error; 630 } 631 ATADEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 632 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 633 (unsigned long)dma_maps->dmamap_table_seg.ds_addr), DEBUG_PROBE); 634 /* Create and load table DMA map for this disk */ 635 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 636 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 637 &dma_maps->dmamap_table)) != 0) { 638 aprint_error(dmaerrfmt, 639 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 640 "create", drive, error); 641 return error; 642 } 643 if ((error = bus_dmamap_load(sc->sc_dmat, 644 dma_maps->dmamap_table, 645 dma_maps->dma_table, 646 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 647 aprint_error(dmaerrfmt, 648 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 649 "load", drive, error); 650 return error; 651 } 652 ATADEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 653 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 654 DEBUG_PROBE); 655 /* Create a xfer DMA map for this drive */ 656 if ((error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 657 NIDEDMA_TABLES(sc), sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 658 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 659 &dma_maps->dmamap_xfer)) != 0) { 660 aprint_error(dmaerrfmt, 661 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 662 "create xfer", drive, error); 663 return error; 664 } 665 return 0; 666 } 667 668 void 669 pciide_dma_table_teardown(struct pciide_softc *sc, int channel, int drive) 670 { 671 struct pciide_channel *cp; 672 struct pciide_dma_maps *dma_maps; 673 674 cp = &sc->pciide_channels[channel]; 675 dma_maps = &cp->dma_maps[drive]; 676 677 if (dma_maps->dma_table == NULL) 678 return; 679 680 bus_dmamap_destroy(sc->sc_dmat, dma_maps->dmamap_xfer); 681 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_table); 682 bus_dmamap_destroy(sc->sc_dmat, dma_maps->dmamap_table); 683 bus_dmamem_unmap(sc->sc_dmat, dma_maps->dma_table, 684 sizeof(struct idedma_table) * NIDEDMA_TABLES(sc)); 685 bus_dmamem_free(sc->sc_dmat, &dma_maps->dmamap_table_seg, 686 dma_maps->dmamap_table_nseg); 687 688 dma_maps->dma_table = NULL; 689 690 return; 691 } 692 693 int 694 pciide_dma_dmamap_setup(struct pciide_softc *sc, int channel, int drive, void *databuf, size_t datalen, int flags) 695 { 696 int error, seg; 697 struct pciide_channel *cp = &sc->pciide_channels[channel]; 698 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 699 700 error = bus_dmamap_load(sc->sc_dmat, 701 dma_maps->dmamap_xfer, 702 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 703 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 704 if (error) { 705 aprint_error(dmaerrfmt, 706 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 707 "load xfer", drive, error); 708 return error; 709 } 710 711 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 712 dma_maps->dmamap_xfer->dm_mapsize, 713 (flags & WDC_DMA_READ) ? 714 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 715 716 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 717 #ifdef DIAGNOSTIC 718 /* A segment must not cross a 64k boundary */ 719 { 720 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 721 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 722 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 723 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 724 printf("pciide_dma: segment %d physical addr 0x%lx" 725 " len 0x%lx not properly aligned\n", 726 seg, phys, len); 727 panic("pciide_dma: buf align"); 728 } 729 } 730 #endif 731 dma_maps->dma_table[seg].base_addr = 732 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 733 dma_maps->dma_table[seg].byte_count = 734 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 735 IDEDMA_BYTE_COUNT_MASK); 736 ATADEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 737 seg, le32toh(dma_maps->dma_table[seg].byte_count), 738 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 739 740 } 741 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 742 htole32(IDEDMA_BYTE_COUNT_EOT); 743 744 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 745 dma_maps->dmamap_table->dm_mapsize, 746 BUS_DMASYNC_PREWRITE); 747 748 #ifdef DIAGNOSTIC 749 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 750 printf("pciide_dma_dmamap_setup: addr 0x%lx " 751 "not properly aligned\n", 752 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 753 panic("pciide_dma_init: table align"); 754 } 755 #endif 756 /* remember flags */ 757 dma_maps->dma_flags = flags; 758 759 return 0; 760 } 761 762 int 763 pciide_dma_init(void *v, int channel, int drive, void *databuf, size_t datalen, int flags) 764 { 765 struct pciide_softc *sc = v; 766 int error; 767 struct pciide_channel *cp = &sc->pciide_channels[channel]; 768 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 769 770 if ((error = pciide_dma_dmamap_setup(sc, channel, drive, 771 databuf, datalen, flags)) != 0) 772 return error; 773 /* Maps are ready. Start DMA function */ 774 /* Clear status bits */ 775 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 776 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 777 /* Write table addr */ 778 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 779 dma_maps->dmamap_table->dm_segs[0].ds_addr); 780 /* set read/write */ 781 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 782 ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd); 783 return 0; 784 } 785 786 void 787 pciide_dma_start(void *v, int channel, int drive) 788 { 789 struct pciide_softc *sc = v; 790 struct pciide_channel *cp = &sc->pciide_channels[channel]; 791 792 ATADEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 793 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 794 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 795 | IDEDMA_CMD_START); 796 } 797 798 int 799 pciide_dma_finish(void *v, int channel, int drive, int force) 800 { 801 struct pciide_softc *sc = v; 802 u_int8_t status; 803 int error = 0; 804 struct pciide_channel *cp = &sc->pciide_channels[channel]; 805 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 806 807 status = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0); 808 ATADEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 809 DEBUG_XFERS); 810 811 if (force == WDC_DMAEND_END && (status & IDEDMA_CTL_INTR) == 0) 812 return WDC_DMAST_NOIRQ; 813 814 /* stop DMA channel */ 815 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 816 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 817 & ~IDEDMA_CMD_START); 818 819 /* Unload the map of the data buffer */ 820 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 821 dma_maps->dmamap_xfer->dm_mapsize, 822 (dma_maps->dma_flags & WDC_DMA_READ) ? 823 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 824 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 825 826 if ((status & IDEDMA_CTL_ERR) != 0 && force != WDC_DMAEND_ABRT_QUIET) { 827 aprint_error("%s:%d:%d: bus-master DMA error: status=0x%x\n", 828 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 829 drive, status); 830 error |= WDC_DMAST_ERR; 831 } 832 833 if ((status & IDEDMA_CTL_INTR) == 0 && force != WDC_DMAEND_ABRT_QUIET) { 834 aprint_error("%s:%d:%d: bus-master DMA error: missing " 835 "interrupt, status=0x%x\n", 836 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 837 channel, drive, status); 838 error |= WDC_DMAST_NOIRQ; 839 } 840 841 if ((status & IDEDMA_CTL_ACT) != 0 && force != WDC_DMAEND_ABRT_QUIET) { 842 /* data underrun, may be a valid condition for ATAPI */ 843 error |= WDC_DMAST_UNDER; 844 } 845 return error; 846 } 847 848 void 849 pciide_irqack(struct ata_channel *chp) 850 { 851 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 852 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 853 854 /* clear status bits in IDE DMA registers */ 855 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 856 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 857 } 858 #endif /* NATA_DMA */ 859 860 /* some common code used by several chip_map */ 861 int 862 pciide_chansetup(struct pciide_softc *sc, int channel, pcireg_t interface) 863 { 864 struct pciide_channel *cp = &sc->pciide_channels[channel]; 865 sc->wdc_chanarray[channel] = &cp->ata_channel; 866 cp->name = PCIIDE_CHANNEL_NAME(channel); 867 cp->ata_channel.ch_channel = channel; 868 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 869 cp->ata_channel.ch_queue = 870 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 871 if (cp->ata_channel.ch_queue == NULL) { 872 aprint_error("%s %s channel: " 873 "can't allocate memory for command queue", 874 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 875 return 0; 876 } 877 cp->ata_channel.ch_ndrive = 2; 878 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 879 "%s channel %s to %s mode\n", cp->name, 880 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 881 "configured" : "wired", 882 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 883 "native-PCI" : "compatibility"); 884 return 1; 885 } 886 887 /* some common code used by several chip channel_map */ 888 void 889 pciide_mapchan(struct pci_attach_args *pa, 890 struct pciide_channel *cp, 891 pcireg_t interface, int (*pci_intr)(void *)) 892 { 893 struct ata_channel *wdc_cp = &cp->ata_channel; 894 895 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) 896 pciide_mapregs_native(pa, cp, pci_intr); 897 else { 898 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel); 899 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 900 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 901 } 902 wdcattach(wdc_cp); 903 } 904 905 /* 906 * generic code to map the compat intr. 907 */ 908 void 909 pciide_map_compat_intr(struct pci_attach_args *pa, struct pciide_channel *cp, int compatchan) 910 { 911 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 912 913 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 914 cp->ih = 915 pciide_machdep_compat_intr_establish(sc->sc_wdcdev.sc_atac.atac_dev, 916 pa, compatchan, pciide_compat_intr, cp); 917 if (cp->ih == NULL) { 918 #endif 919 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 920 "no compatibility interrupt for use by %s " 921 "channel\n", cp->name); 922 cp->ata_channel.ch_flags |= ATACH_DISABLED; 923 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 924 } 925 #endif 926 } 927 928 void 929 pciide_unmap_compat_intr(pci_chipset_tag_t pc, struct pciide_channel *cp, int compatchan) 930 { 931 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH 932 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 933 934 pciide_machdep_compat_intr_disestablish(sc->sc_wdcdev.sc_atac.atac_dev, 935 sc->sc_pc, compatchan, cp->ih); 936 #endif 937 } 938 939 void 940 default_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 941 { 942 struct pciide_channel *cp; 943 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 944 pcireg_t csr; 945 int channel; 946 #if NATA_DMA 947 int drive; 948 u_int8_t idedma_ctl; 949 #endif 950 const char *failreason; 951 struct wdc_regs *wdr; 952 953 if (pciide_chipen(sc, pa) == 0) 954 return; 955 956 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 957 #if NATA_DMA 958 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 959 "bus-master DMA support present"); 960 if (sc->sc_pp == &default_product_desc && 961 (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 962 PCIIDE_OPTIONS_DMA) == 0) { 963 aprint_verbose(", but unused (no driver support)"); 964 sc->sc_dma_ok = 0; 965 } else { 966 pciide_mapreg_dma(sc, pa); 967 if (sc->sc_dma_ok != 0) 968 aprint_verbose(", used without full driver " 969 "support"); 970 } 971 #else 972 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 973 "bus-master DMA support present, but unused (no driver " 974 "support)"); 975 #endif /* NATA_DMA */ 976 } else { 977 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 978 "hardware does not support DMA"); 979 #if NATA_DMA 980 sc->sc_dma_ok = 0; 981 #endif 982 } 983 aprint_verbose("\n"); 984 #if NATA_DMA 985 if (sc->sc_dma_ok) { 986 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 987 sc->sc_wdcdev.irqack = pciide_irqack; 988 } 989 #endif 990 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0; 991 #if NATA_DMA 992 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 993 #endif 994 995 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 996 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 997 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 998 999 wdc_allocate_regs(&sc->sc_wdcdev); 1000 1001 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1002 channel++) { 1003 cp = &sc->pciide_channels[channel]; 1004 if (pciide_chansetup(sc, channel, interface) == 0) 1005 continue; 1006 wdr = CHAN_TO_WDC_REGS(&cp->ata_channel); 1007 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1008 pciide_mapregs_native(pa, cp, pciide_pci_intr); 1009 else 1010 pciide_mapregs_compat(pa, cp, 1011 cp->ata_channel.ch_channel); 1012 if (cp->ata_channel.ch_flags & ATACH_DISABLED) 1013 continue; 1014 /* 1015 * Check to see if something appears to be there. 1016 */ 1017 failreason = NULL; 1018 /* 1019 * In native mode, always enable the controller. It's 1020 * not possible to have an ISA board using the same address 1021 * anyway. 1022 */ 1023 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1024 wdcattach(&cp->ata_channel); 1025 continue; 1026 } 1027 if (!wdcprobe(&cp->ata_channel)) { 1028 failreason = "not responding; disabled or no drives?"; 1029 goto next; 1030 } 1031 /* 1032 * Now, make sure it's actually attributable to this PCI IDE 1033 * channel by trying to access the channel again while the 1034 * PCI IDE controller's I/O space is disabled. (If the 1035 * channel no longer appears to be there, it belongs to 1036 * this controller.) YUCK! 1037 */ 1038 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1039 PCI_COMMAND_STATUS_REG); 1040 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1041 csr & ~PCI_COMMAND_IO_ENABLE); 1042 if (wdcprobe(&cp->ata_channel)) 1043 failreason = "other hardware responding at addresses"; 1044 pci_conf_write(sc->sc_pc, sc->sc_tag, 1045 PCI_COMMAND_STATUS_REG, csr); 1046 next: 1047 if (failreason) { 1048 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1049 "%s channel ignored (%s)\n", cp->name, failreason); 1050 cp->ata_channel.ch_flags |= ATACH_DISABLED; 1051 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 1052 wdr->cmd_ios); 1053 bus_space_unmap(wdr->ctl_iot, wdr->ctl_ioh, 1054 wdr->ctl_ios); 1055 } else { 1056 pciide_map_compat_intr(pa, cp, 1057 cp->ata_channel.ch_channel); 1058 wdcattach(&cp->ata_channel); 1059 } 1060 } 1061 1062 #if NATA_DMA 1063 if (sc->sc_dma_ok == 0) 1064 return; 1065 1066 /* Allocate DMA maps */ 1067 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1068 channel++) { 1069 idedma_ctl = 0; 1070 cp = &sc->pciide_channels[channel]; 1071 for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) { 1072 /* 1073 * we have not probed the drives yet, allocate 1074 * ressources for all of them. 1075 */ 1076 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1077 /* Abort DMA setup */ 1078 aprint_error( 1079 "%s:%d:%d: can't allocate DMA maps, " 1080 "using PIO transfers\n", 1081 device_xname( 1082 sc->sc_wdcdev.sc_atac.atac_dev), 1083 channel, drive); 1084 sc->sc_dma_ok = 0; 1085 sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA; 1086 sc->sc_wdcdev.irqack = NULL; 1087 break; 1088 } 1089 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1090 } 1091 if (idedma_ctl != 0) { 1092 /* Add software bits in status register */ 1093 bus_space_write_1(sc->sc_dma_iot, 1094 cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl); 1095 } 1096 } 1097 #endif /* NATA_DMA */ 1098 } 1099 1100 void 1101 sata_setup_channel(struct ata_channel *chp) 1102 { 1103 #if NATA_DMA 1104 struct ata_drive_datas *drvp; 1105 int drive; 1106 #if NATA_UDMA 1107 int s; 1108 #endif 1109 u_int32_t idedma_ctl; 1110 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 1111 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 1112 1113 /* setup DMA if needed */ 1114 pciide_channel_dma_setup(cp); 1115 1116 idedma_ctl = 0; 1117 1118 for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) { 1119 drvp = &chp->ch_drive[drive]; 1120 /* If no drive, skip */ 1121 if ((drvp->drive_flags & DRIVE) == 0) 1122 continue; 1123 #if NATA_UDMA 1124 if (drvp->drive_flags & DRIVE_UDMA) { 1125 /* use Ultra/DMA */ 1126 s = splbio(); 1127 drvp->drive_flags &= ~DRIVE_DMA; 1128 splx(s); 1129 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1130 } else 1131 #endif /* NATA_UDMA */ 1132 if (drvp->drive_flags & DRIVE_DMA) { 1133 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1134 } 1135 } 1136 1137 /* 1138 * Nothing to do to setup modes; it is meaningless in S-ATA 1139 * (but many S-ATA drives still want to get the SET_FEATURE 1140 * command). 1141 */ 1142 if (idedma_ctl != 0) { 1143 /* Add software bits in status register */ 1144 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 1145 idedma_ctl); 1146 } 1147 #endif /* NATA_DMA */ 1148 } 1149