xref: /netbsd/sys/dev/pci/pciide_hpt_reg.h (revision c4a72b64)
1 /*      $NetBSD: pciide_hpt_reg.h,v 1.9 2002/08/23 16:24:55 bouyer Exp $       */
2 
3 /*
4  * Copyright (c) 2000 Manuel Bouyer.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *      This product includes software developed by Manuel Bouyer.
17  * 4. Neither the name of the University nor the names of its contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30  *
31  */
32 
33 
34 /*
35  * Register definitions for the Highpoint HPT366 UDMA/66 * and HPT370 UDMA/100
36  * PCI IDE controller.
37  *
38  * The HPT366 has 2 PCI IDE functions, each of them has only one channel.
39  * The HPT370 has the 2 channels on the same PCI IDE function.
40  */
41 
42 /*
43  * The HPT366 and HPT370 have the save vendor/device ID but not the
44  * same revision
45  */
46 #define HPT366_REV 0x01
47 #define HPT370_REV 0x03
48 #define HPT370A_REV 0x04
49 #define HPT372_REV 0x05
50 #define HPT374_REV 0x07
51 
52 #define HPT_IDETIM(chan, drive) (0x40 + ((drive) * 4) + ((chan) * 8))
53 #define HPT_IDETIM_BUFEN		0x80000000
54 #define HPT_IDETIM_MSTEN		0x40000000
55 #define HPT_IDETIM_DMAEN		0x20000000
56 #define HPT_IDETIM_UDMAEN		0x10000000
57 
58 #define HPT366_CTRL1		0x50
59 #define HPT366_CTRL1_BLKDIS(chan)	(0x40 << (chan))
60 #define HPT366_CTRL1_CHANEN(chan)	(0x10 << (chan))
61 #define HPT366_CTRL1_CLRBUF(chan)	(0x04 << (chan))
62 #define HPT366_CTRL1_LEG(chan)		(0x01 << (chan))
63 
64 #define HPT366_CTRL2		0x51
65 #define HPT366_CTRL2_FASTIRQ		0x80
66 #define HPT366_CTRL2_HOLDIRQ(chan)	(0x20 << (chan))
67 #define HPT366_CTRL2_SGEN		0x10
68 #define HPT366_CTRL2_CLEARFIFO(chan)	(0x04 << (chan))
69 #define HPT366_CTRL2_CLEARBMSM		0x02
70 #define HPT366_CTRL2_CLEARSG		0x01
71 
72 #define HPT366_CTRL3(chan)	(0x52 + ((chan) * 4))
73 #define HPT366_CTRL3_PDMA		0x8000
74 #define HPT366_CTRL3_BP			0x4000
75 #define HPT366_CTRL3_FASTIRQ_OFFSET	9
76 #define HPT366_CTRL3_FASTIRQ_MASK	0x3
77 
78 #define HPT370_CTRL1(chan)	(0x50 + ((chan) * 4))
79 #define HPT370_CTRL1_CLRSG		0x80
80 #define HPT370_CTRL1_READF		0x40
81 #define HPT370_CTRL1_CLRST		0x20
82 #define HPT370_CTRL1_CLRSGC		0x10
83 #define HPT370_CTRL1_BLKDIS		0x08
84 #define HPT370_CTRL1_EN			0x04
85 #define HPT370_CTRL1_CLRDBUF		0x02
86 #define HPT370_CTRL1_LEGEN		0x01
87 
88 #define HPT370_CTRL2(chan)	(0x51 + ((chan) * 4))
89 #define HPT370_CTRL2_FASTIRQ		0x02
90 #define HPT370_CTRL2_HIRQ		0x01
91 
92 #define HPT370_CTRL3(chan)	(0x52 + ((chan) * 4))
93 #define HPT370_CTRL3_HIZ		0x8000
94 #define HPT370_CTRL3_BP			0x4000
95 #define HPT370_CTRL3_FASTIRQ_OFFSET	9
96 #define HPT370_CTRL3_FASTIRQ_MASK	0x3
97 
98 #define HPT_STAT1		0x58
99 #define HPT_STAT1_IRQPOLL(chan)		(0x40 << (chan)) /* 366 only */
100 #define HPT_STAT1_DMARQ(chan) 		(0x04 << ((chan) * 3))
101 #define HPT_STAT1_DMACK(chan) 		(0x02 << ((chan) * 3))
102 #define HPT_STAT1_IORDY(chan) 		(0x01 << ((chan) * 3))
103 
104 #define HPT_STAT2		0x59
105 #define HPT_STAT2_FLT_RST		0x40 /* 366 only */
106 #define HPT_STAT2_RST(chan)		(0x40 << (chan))  /* 370 only */
107 #define HPT_STAT2_POLLEN(chan)		(0x04 << ((chan) * 3))
108 #define HPT_STAT2_IRQD1(chan)		(0x02 << ((chan) * 3))
109 #define HPT_STAT2_IRQD0_CH1		0x08
110 #define HPT_STAT2_POLLST		0x01
111 
112 #define HPT_CSEL		0x5a
113 #define HPT_CSEL_IRQDIS			0x10 /* 370 only */
114 #define HPT_CSEL_PCIDIS			0x08 /* 370 only */
115 #define HPT_CSEL_PCIWR			0x04 /* 370 only */
116 #define HPT_CSEL_CBLID(chan)		 (0x01 << (1 - (chan)))
117 
118 #define HPT_SC2			0x5b
119 #define HPT_SC2_OSC_OK		0x80
120 #define HPT_SC2_OSC_EN		0x20
121 #define HPT_SC2_ECLK		0x10
122 #define HPT_SC2_BPIO		0x08
123 #define HPT_SC2_DMARQW		0x04
124 #define HPT_SC2_SCLK		0x02
125 #define HPT_SC2_MAEN		0x01
126 
127 static const u_int32_t hpt366_pio[] __attribute__((__unused__)) =
128 	{0x00d0a7aa, 0x00c8a753, 0x00c8a742, 0x00c8a731};
129 static const u_int32_t hpt366_dma[] __attribute__((__unused__)) =
130 	{0x20c8a797, 0x20c8a742, 0x20c8a731};
131 static const u_int32_t hpt366_udma[] __attribute__((__unused__)) =
132 	{0x10c8a731, 0x10cba731, 0x10caa731, 0x10cfa731, 0x10c9a731};
133 
134 static const u_int32_t hpt370_pio[] __attribute__((__unused__)) =
135 	{0x06914e8a, 0x06914e65, 0x06514e33, 0x06514e22, 0x06514e21};
136 static const u_int32_t hpt370_dma[] __attribute__((__unused__)) =
137 	{0x26514e97, 0x26514e33, 0x26514e21};
138 static const u_int32_t hpt370_udma[] __attribute__((__unused__)) =
139 	{0x16514e31, 0x164d4e31, 0x16494e31, 0x166d4e31, 0x16454e31,
140 	 0x1a85f442};
141 
142 static const u_int32_t hpt372_pio[] __attribute__((__unused__)) =
143 	{0x0d029d5e, 0x0d029d26, 0x0c829ca6, 0x0c829c84, 0x0c829c62};
144 static const u_int32_t hpt372_dma[] __attribute__((__unused__)) =
145 	{0x2c829d2e, 0x2c829c66, 0x2829c62};
146 static const u_int32_t hpt372_udma[] __attribute__((__unused__)) =
147 	{0x1c829c62, 0x1c9a9c62, 0x1c929c62, 0x1c8e9c62, 0x1c8a9c62,
148 	 0x1cae9c62, 0x1c869c62};
149 
150 static u_int32_t hpt374_pio[] __attribute__((__unused__)) =
151 	{0x0ac1f48a, 0x0ac1f465, 0x0a81f454, 0x0a81f443, 0x0a81f442};
152 static u_int32_t hpt374_dma[] __attribute__((__unused__)) =
153 	{0x228082ea, 0x22808254, 0x22808242};
154 static u_int32_t hpt374_udma[] __attribute__((__unused__)) =
155 	{0x121882ea, 0x12148254, 0x120c8242, 0x128c8242, 0x12ac8242,
156 	    0x12848242, 0x12808242};
157