1 /* $NetBSD: pciide_natsemi_reg.h,v 1.1 2010/11/10 22:34:24 skrll Exp $ */ 2 3 /* $OpenBSD: pciide_natsemi_reg.h,v 1.7 2007/06/24 12:41:19 kettenis Exp $ */ 4 5 /* 6 * Copyright (c) 2001 Jason L. Wright (jason@thought.net) 7 * Copyright (c) 2004 Alexander Yurchenko <grange@openbsd.org> 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _DEV_PCI_PCIIDE_NATSEMI_REG_H_ 33 #define _DEV_PCI_PCIIDE_NATSEMI_REG_H_ 34 35 /* 36 * Register definitions for National Semiconductor PC87415. Definitions 37 * based on "PC87415: PCI-IDE DMA Master Mode Interface Controller" 38 * (March 1996) datasheet from their website. 39 */ 40 41 #define NATSEMI_CTRL1 0x40 /* Control register1 */ 42 #define NATSEMI_CTRL1_SWRST 0x04 /* sw rst to ch1/ch2 on */ 43 #define NATSEMI_CTRL1_IDEPWR 0x08 44 #define NATSEMI_CTRL1_CH1INTMAP 0x10 45 #define NATSEMI_CTRL1_CH2INTMAP 0x20 46 #define NATSEMI_CTRL1_INTAMASK 0x40 47 #define NATSEMI_CTRL1_IDWR 0x80 /* write to did/vid enable */ 48 49 #define NATSEMI_CTRL2 0x41 /* Control register2 */ 50 #define NATSEMI_CTRL2_CH1MASK 0x01 /* channel 1 intr masked */ 51 #define NATSEMI_CTRL2_CH2MASK 0x02 /* channel 2 intr masked */ 52 #define NATSEMI_CTRL2_BARDIS 0x04 /* PCI BAR 2/3 disable */ 53 #define NATSEMI_CTRL2_WATCHDOG 0x08 /* enable watchdog timer */ 54 #define NATSEMI_CTRL2_BUF1BYP 0x10 /* bypass buffer 1 */ 55 #define NATSEMI_CTRL2_BUF2BYP 0x20 /* bypass buffer 2 */ 56 #define NATSEMI_CTRL2_IDE1MAP 0x40 /* IDE at bar 1 */ 57 #define NATSEMI_CTRL2_IDE2MAP 0x80 /* IDE at bar 2 */ 58 59 #define NATSEMI_CHMASK(chn) (NATSEMI_CTRL2_CH1MASK << (chn)) 60 61 #define NATSEMI_CTRL3 0x42 /* Control register3 */ 62 #define NATSEMI_CTRL3_CH1PREDIS 0x01 /* channel 1 prefetch disable */ 63 #define NATSEMI_CTRL3_CH2PREDIS 0x02 /* channel 2 prefetch disable */ 64 #define NATSEMI_CTRL3_RSTIDLE 0x04 /* reset idle state */ 65 #define NATSEMI_CTRL3_C1D1DMARQ 0x10 /* c1d1 dmarq handshaking */ 66 #define NATSEMI_CTRL3_C1D2DMARQ 0x20 /* c1d2 dmarq handshaking */ 67 #define NATSEMI_CTRL3_C2D1DMARQ 0x40 /* c2d1 dmarq handshaking */ 68 #define NATSEMI_CTRL3_C2D2DMARQ 0x80 /* c2d2 dmarq handshaking */ 69 70 #define NATSEMI_WBS 0x43 /* Write buffer status */ 71 #define NATSEMI_WBS_WB1NMPTY 0x01 /* chan 1 write buf not empty */ 72 #define NATSEMI_WBS_WB2NMPTY 0x02 /* chan 2 write buf not empty */ 73 74 #define NATSEMI_C1D1DRT 0x44 /* Channel 1/device 1 data read timing */ 75 #define NATSEMI_C1D1DWT 0x45 /* Channel 1/device 1 data write timing */ 76 #define NATSEMI_C1D2DRT 0x48 /* Channel 1/device 2 data read timing */ 77 #define NATSEMI_C1D2DWT 0x49 /* Channel 1/device 2 data write timing */ 78 #define NATSEMI_C2D1DRT 0x4c /* Channel 2/device 1 data read timing */ 79 #define NATSEMI_C2D1DWT 0x4d /* Channel 2/device 1 data write timing */ 80 #define NATSEMI_C2D2DRT 0x50 /* Channel 2/device 2 data read timing */ 81 #define NATSEMI_C2D2DWT 0x51 /* Channel 2/device 2 data write timing */ 82 83 #define NATSEMI_CCBT 0x54 /* Command and control block timing */ 84 85 #define NATSEMI_SECT 0x55 /* Sector size */ 86 #define NATSEMI_SECT_C1UNUSED 0x0f /* not used */ 87 #define NATSEMI_SECT_C1_512 0x0e /* 512 bytes */ 88 #define NATSEMI_SECT_C1_1024 0x0c /* 1024 bytes */ 89 #define NATSEMI_SECT_C1_2048 0x08 /* 2048 bytes */ 90 #define NATSEMI_SECT_C1_4096 0x00 /* 4096 bytes */ 91 #define NATSEMI_SECT_C2UNUSED 0xf0 /* not used */ 92 #define NATSEMI_SECT_C2_512 0xe0 /* 512 bytes */ 93 #define NATSEMI_SECT_C2_1024 0xc0 /* 1024 bytes */ 94 #define NATSEMI_SECT_C2_2048 0x80 /* 2048 bytes */ 95 #define NATSEMI_SECT_C2_4096 0x00 /* 4096 bytes */ 96 97 #define NATSEMI_RTREG(c,d) (0x44 + (c * 8) + (d * 4) + 0) 98 #define NATSEMI_WTREG(c,d) (0x44 + (c * 8) + (d * 4) + 1) 99 100 /* 17 - N = number of clocks */ 101 static u_int8_t natsemi_pio_pulse[] = { 7, 12, 13, 14, 14 }; 102 static u_int8_t natsemi_dma_pulse[] = { 7, 10, 10 }; 103 /* 16 - N = number of clocks */ 104 static u_int8_t natsemi_pio_recover[] = { 6, 8, 11, 13, 15 }; 105 static u_int8_t natsemi_dma_recover[] = { 6, 8, 9 }; 106 107 #endif /* !_DEV_PCI_PCIIDE_NATSEMI_REG_H_ */ 108