1 /* $NetBSD: pciide_piix_reg.h,v 1.7 2002/04/23 20:41:18 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * Registers definitions for Intel's PIIX serie PCI IDE controllers. 36 * See Intel's 37 * "82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE XCELERATOR" 38 * "82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)" and 39 * "Intel 82801AA (ICH) and Intel 82801AB (ICH0) I/O Controller Hub" 40 * available from http://developers.intel.com/ 41 */ 42 43 /* 44 * Bus master interface base address register 45 */ 46 #define PIIX_BMIBA 0x20 47 #define PIIX_BMIBA_ADDR(x) (x & 0x0000FFFF0) 48 #define PIIX_BMIBA_RTE(x) (x & 0x000000001) 49 #define PIIX_BMIBA_RTE_IO 0x000000001 /* base addr maps to I/O space */ 50 51 /* 52 * IDE timing register 53 * 0x40/0x41 is for primary, 0x42/0x43 for secondary channel 54 */ 55 #define PIIX_IDETIM 0x40 56 #define PIIX_IDETIM_READ(x, channel) (((x) >> (16 * (channel))) & 0x0000FFFF) 57 #define PIIX_IDETIM_SET(x, bytes, channel) \ 58 ((x) | ((bytes) << (16 * (channel)))) 59 #define PIIX_IDETIM_CLEAR(x, bytes, channel) \ 60 ((x) & ~((bytes) << (16 * (channel)))) 61 62 #define PIIX_IDETIM_IDE 0x8000 /* PIIX decode IDE registers */ 63 #define PIIX_IDETIM_SITRE 0x4000 /* slaves IDE timing registers 64 enabled (PIIX3/4 only) */ 65 #define PIIX_IDETIM_ISP_MASK 0x3000 /* IOrdy sample point */ 66 #define PIIX_IDETIM_ISP_SHIFT 12 67 #define PIIX_IDETIM_ISP_SET(x) ((x) << PIIX_IDETIM_ISP_SHIFT) 68 #define PIIX_IDETIM_RTC_MASK 0x0300 /* recovery time */ 69 #define PIIX_IDETIM_RTC_SHIFT 8 70 #define PIIX_IDETIM_RTC_SET(x) ((x) << PIIX_IDETIM_RTC_SHIFT) 71 #define PIIX_IDETIM_DTE(d) (0x0008 << (4 * (d))) /* DMA timing only */ 72 #define PIIX_IDETIM_PPE(d) (0x0004 << (4 * (d))) /* prefetch/posting */ 73 #define PIIX_IDETIM_IE(d) (0x0002 << (4 * (d))) /* IORDY enable */ 74 #define PIIX_IDETIM_TIME(d) (0x0001 << (4 * (d))) /* Fast timing enable */ 75 /* 76 * Slave IDE timing register (PIIX3/4 only) 77 * This register must be enabled via the PIIX_IDETIM_SITRE bit 78 */ 79 #define PIIX_SIDETIM 0x44 80 #define PIIX_SIDETIM_ISP_MASK(channel) (0x0c << ((channel) * 4)) 81 #define PIIX_SIDETIM_ISP_SHIFT 2 82 #define PIIX_SIDETIM_ISP_SET(x, channel) \ 83 (x << (PIIX_SIDETIM_ISP_SHIFT + ((channel) * 4))) 84 #define PIIX_SIDETIM_RTC_MASK(channel) (0x03 << ((channel) * 4)) 85 #define PIIX_SIDETIM_RTC_SHIFT 0 86 #define PIIX_SIDETIM_RTC_SET(x, channel) \ 87 (x << (PIIX_SIDETIM_RTC_SHIFT + ((channel) * 4))) 88 89 /* 90 * Ultra DMA/33 register (PIIX4 only) 91 */ 92 #define PIIX_UDMAREG 0x48 93 /* Control register */ 94 #define PIIX_UDMACTL_DRV_EN(channel, drive) (0x01 << ((channel) * 2 + (drive))) 95 /* Ultra DMA/33 timing register (PIIX4 only) */ 96 #define PIIX_UDMATIM_SHIFT 16 97 #define PIIX_UDMATIM_SET(x, channel, drive) \ 98 (((x) << ((channel * 8) + (drive * 4))) << PIIX_UDMATIM_SHIFT) 99 100 /* 101 * IDE config register (ICH/ICH0/ICH2 only) 102 */ 103 #define PIIX_CONFIG 0x54 104 #define PIIX_CONFIG_PINGPONG 0x0400 105 /* The following are only for the 82801AA (ICH) and 82801BA (ICH2) */ 106 #define PIIX_CONFIG_CR(channel, drive) (0x0010 << ((channel) * 2 + (drive))) 107 #define PIIX_CONFIG_UDMA66(channel, drive) (0x0001 << ((channel) * 2 + (drive))) 108 /* The following are only for the 82801BA (ICH2) */ 109 #define PIIX_CONFIG_UDMA100(channel, drive) (0x1000 << ((channel) * 2 + (drive))) 110 111 /* 112 * these tables define the differents values to upload to the 113 * ISP and RTC registers for the various PIO and DMA mode 114 * (from the PIIX4 doc). 115 */ 116 static const int8_t piix_isp_pio[] __attribute__((__unused__)) = 117 {0x00, 0x00, 0x01, 0x02, 0x02}; 118 static const int8_t piix_rtc_pio[] __attribute__((__unused__)) = 119 {0x00, 0x00, 0x00, 0x01, 0x03}; 120 static const int8_t piix_isp_dma[] __attribute__((__unused__)) = 121 {0x00, 0x02, 0x02}; 122 static const int8_t piix_rtc_dma[] __attribute__((__unused__)) = 123 {0x00, 0x02, 0x03}; 124 static const int8_t piix4_sct_udma[] __attribute__((__unused__)) = 125 {0x00, 0x01, 0x02, 0x01, 0x02, 0x01}; 126