1 /* $NetBSD: pcireg.h,v 1.37 2002/03/22 20:03:20 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1999, 2000 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _DEV_PCI_PCIREG_H_ 35 #define _DEV_PCI_PCIREG_H_ 36 37 /* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43 /* 44 * Device identification register; contains a vendor ID and a device ID. 45 */ 46 #define PCI_ID_REG 0x00 47 48 typedef u_int16_t pci_vendor_id_t; 49 typedef u_int16_t pci_product_id_t; 50 51 #define PCI_VENDOR_SHIFT 0 52 #define PCI_VENDOR_MASK 0xffff 53 #define PCI_VENDOR(id) \ 54 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 55 56 #define PCI_PRODUCT_SHIFT 16 57 #define PCI_PRODUCT_MASK 0xffff 58 #define PCI_PRODUCT(id) \ 59 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 60 61 #define PCI_ID_CODE(vid,pid) \ 62 ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ 63 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) \ 64 65 /* 66 * Command and status register. 67 */ 68 #define PCI_COMMAND_STATUS_REG 0x04 69 #define PCI_COMMAND_SHIFT 0 70 #define PCI_COMMAND_MASK 0xffff 71 #define PCI_STATUS_SHIFT 16 72 #define PCI_STATUS_MASK 0xffff 73 74 #define PCI_COMMAND_STATUS_CODE(cmd,stat) \ 75 ((((cmd) & PCI_COMMAND_MASK) >> PCI_COMMAND_SHIFT) | \ 76 (((stat) & PCI_STATUS_MASK) >> PCI_STATUS_SHIFT)) \ 77 78 #define PCI_COMMAND_IO_ENABLE 0x00000001 79 #define PCI_COMMAND_MEM_ENABLE 0x00000002 80 #define PCI_COMMAND_MASTER_ENABLE 0x00000004 81 #define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 82 #define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 83 #define PCI_COMMAND_PALETTE_ENABLE 0x00000020 84 #define PCI_COMMAND_PARITY_ENABLE 0x00000040 85 #define PCI_COMMAND_STEPPING_ENABLE 0x00000080 86 #define PCI_COMMAND_SERR_ENABLE 0x00000100 87 #define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 88 89 #define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 90 #define PCI_STATUS_66MHZ_SUPPORT 0x00200000 91 #define PCI_STATUS_UDF_SUPPORT 0x00400000 92 #define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 93 #define PCI_STATUS_PARITY_ERROR 0x01000000 94 #define PCI_STATUS_DEVSEL_FAST 0x00000000 95 #define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 96 #define PCI_STATUS_DEVSEL_SLOW 0x04000000 97 #define PCI_STATUS_DEVSEL_MASK 0x06000000 98 #define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 99 #define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 100 #define PCI_STATUS_MASTER_ABORT 0x20000000 101 #define PCI_STATUS_SPECIAL_ERROR 0x40000000 102 #define PCI_STATUS_PARITY_DETECT 0x80000000 103 104 /* 105 * PCI Class and Revision Register; defines type and revision of device. 106 */ 107 #define PCI_CLASS_REG 0x08 108 109 typedef u_int8_t pci_class_t; 110 typedef u_int8_t pci_subclass_t; 111 typedef u_int8_t pci_interface_t; 112 typedef u_int8_t pci_revision_t; 113 114 #define PCI_CLASS_SHIFT 24 115 #define PCI_CLASS_MASK 0xff 116 #define PCI_CLASS(cr) \ 117 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 118 119 #define PCI_SUBCLASS_SHIFT 16 120 #define PCI_SUBCLASS_MASK 0xff 121 #define PCI_SUBCLASS(cr) \ 122 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 123 124 #define PCI_INTERFACE_SHIFT 8 125 #define PCI_INTERFACE_MASK 0xff 126 #define PCI_INTERFACE(cr) \ 127 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 128 129 #define PCI_REVISION_SHIFT 0 130 #define PCI_REVISION_MASK 0xff 131 #define PCI_REVISION(cr) \ 132 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 133 134 #define PCI_CLASS_CODE(mainclass, subclass, interface) \ 135 ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \ 136 (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \ 137 (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT)) 138 139 /* base classes */ 140 #define PCI_CLASS_PREHISTORIC 0x00 141 #define PCI_CLASS_MASS_STORAGE 0x01 142 #define PCI_CLASS_NETWORK 0x02 143 #define PCI_CLASS_DISPLAY 0x03 144 #define PCI_CLASS_MULTIMEDIA 0x04 145 #define PCI_CLASS_MEMORY 0x05 146 #define PCI_CLASS_BRIDGE 0x06 147 #define PCI_CLASS_COMMUNICATIONS 0x07 148 #define PCI_CLASS_SYSTEM 0x08 149 #define PCI_CLASS_INPUT 0x09 150 #define PCI_CLASS_DOCK 0x0a 151 #define PCI_CLASS_PROCESSOR 0x0b 152 #define PCI_CLASS_SERIALBUS 0x0c 153 #define PCI_CLASS_WIRELESS 0x0d 154 #define PCI_CLASS_I2O 0x0e 155 #define PCI_CLASS_SATCOM 0x0f 156 #define PCI_CLASS_CRYPTO 0x10 157 #define PCI_CLASS_DASP 0x11 158 #define PCI_CLASS_UNDEFINED 0xff 159 160 /* 0x00 prehistoric subclasses */ 161 #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 162 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 163 164 /* 0x01 mass storage subclasses */ 165 #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 166 #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 167 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 168 #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 169 #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 170 #define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 171 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 172 173 /* 0x02 network subclasses */ 174 #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 175 #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 176 #define PCI_SUBCLASS_NETWORK_FDDI 0x02 177 #define PCI_SUBCLASS_NETWORK_ATM 0x03 178 #define PCI_SUBCLASS_NETWORK_ISDN 0x04 179 #define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 180 #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 181 #define PCI_SUBCLASS_NETWORK_MISC 0x80 182 183 /* 0x03 display subclasses */ 184 #define PCI_SUBCLASS_DISPLAY_VGA 0x00 185 #define PCI_SUBCLASS_DISPLAY_XGA 0x01 186 #define PCI_SUBCLASS_DISPLAY_3D 0x02 187 #define PCI_SUBCLASS_DISPLAY_MISC 0x80 188 189 /* 0x04 multimedia subclasses */ 190 #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 191 #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 192 #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 193 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 194 195 /* 0x05 memory subclasses */ 196 #define PCI_SUBCLASS_MEMORY_RAM 0x00 197 #define PCI_SUBCLASS_MEMORY_FLASH 0x01 198 #define PCI_SUBCLASS_MEMORY_MISC 0x80 199 200 /* 0x06 bridge subclasses */ 201 #define PCI_SUBCLASS_BRIDGE_HOST 0x00 202 #define PCI_SUBCLASS_BRIDGE_ISA 0x01 203 #define PCI_SUBCLASS_BRIDGE_EISA 0x02 204 #define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA? */ 205 #define PCI_SUBCLASS_BRIDGE_PCI 0x04 206 #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 207 #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 208 #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 209 #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 210 #define PCI_SUBCLASS_BRIDGE_STPCI 0x09 211 #define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 212 #define PCI_SUBCLASS_BRIDGE_MISC 0x80 213 214 /* 0x07 communications subclasses */ 215 #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 216 #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 217 #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 218 #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 219 #define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 220 #define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 221 #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 222 223 /* 0x08 system subclasses */ 224 #define PCI_SUBCLASS_SYSTEM_PIC 0x00 225 #define PCI_SUBCLASS_SYSTEM_DMA 0x01 226 #define PCI_SUBCLASS_SYSTEM_TIMER 0x02 227 #define PCI_SUBCLASS_SYSTEM_RTC 0x03 228 #define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 229 #define PCI_SUBCLASS_SYSTEM_MISC 0x80 230 231 /* 0x09 input subclasses */ 232 #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 233 #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 234 #define PCI_SUBCLASS_INPUT_MOUSE 0x02 235 #define PCI_SUBCLASS_INPUT_SCANNER 0x03 236 #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 237 #define PCI_SUBCLASS_INPUT_MISC 0x80 238 239 /* 0x0a dock subclasses */ 240 #define PCI_SUBCLASS_DOCK_GENERIC 0x00 241 #define PCI_SUBCLASS_DOCK_MISC 0x80 242 243 /* 0x0b processor subclasses */ 244 #define PCI_SUBCLASS_PROCESSOR_386 0x00 245 #define PCI_SUBCLASS_PROCESSOR_486 0x01 246 #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 247 #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 248 #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 249 #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 250 #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 251 252 /* 0x0c serial bus subclasses */ 253 #define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 254 #define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 255 #define PCI_SUBCLASS_SERIALBUS_SSA 0x02 256 #define PCI_SUBCLASS_SERIALBUS_USB 0x03 257 #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */ 258 #define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 259 #define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 260 #define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 261 #define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 262 #define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 263 264 /* 0x0d wireless subclasses */ 265 #define PCI_SUBCLASS_WIRELESS_IRDA 0x00 266 #define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 267 #define PCI_SUBCLASS_WIRELESS_RF 0x10 268 #define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 269 #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 270 #define PCI_SUBCLASS_WIRELESS_MISC 0x80 271 272 /* 0x0e I2O (Intelligent I/O) subclasses */ 273 #define PCI_SUBCLASS_I2O_STANDARD 0x00 274 275 /* 0x0f satellite communication subclasses */ 276 /* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ 277 #define PCI_SUBCLASS_SATCOM_TV 0x01 278 #define PCI_SUBCLASS_SATCOM_AUDIO 0x02 279 #define PCI_SUBCLASS_SATCOM_VOICE 0x03 280 #define PCI_SUBCLASS_SATCOM_DATA 0x04 281 282 /* 0x10 encryption/decryption subclasses */ 283 #define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 284 #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 285 #define PCI_SUBCLASS_CRYPTO_MISC 0x80 286 287 /* 0x11 data acquisition and signal processing subclasses */ 288 #define PCI_SUBCLASS_DASP_DPIO 0x00 289 #define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 290 #define PCI_SUBCLASS_DASP_SYNC 0x10 291 #define PCI_SUBCLASS_DASP_MGMT 0x20 292 #define PCI_SUBCLASS_DASP_MISC 0x80 293 294 /* 295 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 296 */ 297 #define PCI_BHLC_REG 0x0c 298 299 #define PCI_BIST_SHIFT 24 300 #define PCI_BIST_MASK 0xff 301 #define PCI_BIST(bhlcr) \ 302 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 303 304 #define PCI_HDRTYPE_SHIFT 16 305 #define PCI_HDRTYPE_MASK 0xff 306 #define PCI_HDRTYPE(bhlcr) \ 307 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 308 309 #define PCI_HDRTYPE_TYPE(bhlcr) \ 310 (PCI_HDRTYPE(bhlcr) & 0x7f) 311 #define PCI_HDRTYPE_MULTIFN(bhlcr) \ 312 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 313 314 #define PCI_LATTIMER_SHIFT 8 315 #define PCI_LATTIMER_MASK 0xff 316 #define PCI_LATTIMER(bhlcr) \ 317 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 318 319 #define PCI_CACHELINE_SHIFT 0 320 #define PCI_CACHELINE_MASK 0xff 321 #define PCI_CACHELINE(bhlcr) \ 322 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 323 324 #define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \ 325 ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \ 326 (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \ 327 (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \ 328 (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \ 329 (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT)) 330 331 /* 332 * Mapping registers 333 */ 334 #define PCI_MAPREG_START 0x10 335 #define PCI_MAPREG_END 0x28 336 #define PCI_MAPREG_ROM 0x30 337 #define PCI_MAPREG_PPB_END 0x18 338 #define PCI_MAPREG_PCB_END 0x14 339 340 #define PCI_MAPREG_TYPE(mr) \ 341 ((mr) & PCI_MAPREG_TYPE_MASK) 342 #define PCI_MAPREG_TYPE_MASK 0x00000001 343 344 #define PCI_MAPREG_TYPE_MEM 0x00000000 345 #define PCI_MAPREG_TYPE_IO 0x00000001 346 #define PCI_MAPREG_ROM_ENABLE 0x00000001 347 348 #define PCI_MAPREG_MEM_TYPE(mr) \ 349 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 350 #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 351 352 #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 353 #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 354 #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 355 356 #define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ 357 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) 358 #define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 359 360 #define PCI_MAPREG_MEM_ADDR(mr) \ 361 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 362 #define PCI_MAPREG_MEM_SIZE(mr) \ 363 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 364 #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 365 366 #define PCI_MAPREG_MEM64_ADDR(mr) \ 367 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 368 #define PCI_MAPREG_MEM64_SIZE(mr) \ 369 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 370 #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL 371 372 #define PCI_MAPREG_IO_ADDR(mr) \ 373 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 374 #define PCI_MAPREG_IO_SIZE(mr) \ 375 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 376 #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc 377 378 #define PCI_MAPREG_SIZE_TO_MASK(size) \ 379 (-(size)) 380 381 #define PCI_MAPREG_NUM(offset) \ 382 (((unsigned)(offset)-PCI_MAPREG_START)/4) 383 384 385 /* 386 * Cardbus CIS pointer (PCI rev. 2.1) 387 */ 388 #define PCI_CARDBUS_CIS_REG 0x28 389 390 /* 391 * Subsystem identification register; contains a vendor ID and a device ID. 392 * Types/macros for PCI_ID_REG apply. 393 * (PCI rev. 2.1) 394 */ 395 #define PCI_SUBSYS_ID_REG 0x2c 396 397 /* 398 * capabilities link list (PCI rev. 2.2) 399 */ 400 #define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ 401 #define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ 402 #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 403 #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 404 #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 405 406 #define PCI_CAP_RESERVED0 0x00 407 #define PCI_CAP_PWRMGMT 0x01 408 #define PCI_CAP_AGP 0x02 409 #define PCI_CAP_VPD 0x03 410 #define PCI_CAP_SLOTID 0x04 411 #define PCI_CAP_MBI 0x05 412 #define PCI_CAP_CPCI_HOTSWAP 0x06 413 #define PCI_CAP_PCIX 0x07 414 #define PCI_CAP_LDT 0x08 415 #define PCI_CAP_VENDSPEC 0x09 416 #define PCI_CAP_DEBUGPORT 0x0a 417 #define PCI_CAP_CPCI_RSRCCTL 0x0b 418 #define PCI_CAP_HOTPLUG 0x0c 419 420 /* 421 * Power Management Control Status Register; access via capability pointer. 422 */ 423 424 #define PCI_PMCSR_STATE_MASK 0x03 425 #define PCI_PMCSR_STATE_D0 0x00 426 #define PCI_PMCSR_STATE_D1 0x01 427 #define PCI_PMCSR_STATE_D2 0x02 428 #define PCI_PMCSR_STATE_D3 0x03 429 430 /* 431 * Interrupt Configuration Register; contains interrupt pin and line. 432 */ 433 #define PCI_INTERRUPT_REG 0x3c 434 435 typedef u_int8_t pci_intr_latency_t; 436 typedef u_int8_t pci_intr_grant_t; 437 typedef u_int8_t pci_intr_pin_t; 438 typedef u_int8_t pci_intr_line_t; 439 440 #define PCI_MAX_LAT_SHIFT 24 441 #define PCI_MAX_LAT_MASK 0xff 442 #define PCI_MAX_LAT(icr) \ 443 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) 444 445 #define PCI_MIN_GNT_SHIFT 16 446 #define PCI_MIN_GNT_MASK 0xff 447 #define PCI_MIN_GNT(icr) \ 448 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) 449 450 #define PCI_INTERRUPT_GRANT_SHIFT 24 451 #define PCI_INTERRUPT_GRANT_MASK 0xff 452 #define PCI_INTERRUPT_GRANT(icr) \ 453 (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK) 454 455 #define PCI_INTERRUPT_LATENCY_SHIFT 16 456 #define PCI_INTERRUPT_LATENCY_MASK 0xff 457 #define PCI_INTERRUPT_LATENCY(icr) \ 458 (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK) 459 460 #define PCI_INTERRUPT_PIN_SHIFT 8 461 #define PCI_INTERRUPT_PIN_MASK 0xff 462 #define PCI_INTERRUPT_PIN(icr) \ 463 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 464 465 #define PCI_INTERRUPT_LINE_SHIFT 0 466 #define PCI_INTERRUPT_LINE_MASK 0xff 467 #define PCI_INTERRUPT_LINE(icr) \ 468 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 469 470 #define PCI_INTERRUPT_CODE(lat,gnt,pin,line) \ 471 ((((lat)&PCI_INTERRUPT_LATENCY_MASK)<<PCI_INTERRUPT_LATENCY_SHIFT)| \ 472 (((gnt)&PCI_INTERRUPT_GRANT_MASK) <<PCI_INTERRUPT_GRANT_SHIFT) | \ 473 (((pin)&PCI_INTERRUPT_PIN_MASK) <<PCI_INTERRUPT_PIN_SHIFT) | \ 474 (((line)&PCI_INTERRUPT_LINE_MASK) <<PCI_INTERRUPT_LINE_SHIFT)) 475 476 #define PCI_INTERRUPT_PIN_NONE 0x00 477 #define PCI_INTERRUPT_PIN_A 0x01 478 #define PCI_INTERRUPT_PIN_B 0x02 479 #define PCI_INTERRUPT_PIN_C 0x03 480 #define PCI_INTERRUPT_PIN_D 0x04 481 #define PCI_INTERRUPT_PIN_MAX 0x04 482 483 /* Header Type 1 (Bridge) configuration registers */ 484 #define PCI_BRIDGE_BUS_REG 0x18 485 #define PCI_BRIDGE_BUS_PRIMARY_SHIFT 0 486 #define PCI_BRIDGE_BUS_SECONDARY_SHIFT 8 487 #define PCI_BRIDGE_BUS_SUBORDINATE_SHIFT 16 488 489 #define PCI_BRIDGE_STATIO_REG 0x1C 490 #define PCI_BRIDGE_STATIO_IOBASE_SHIFT 0 491 #define PCI_BRIDGE_STATIO_IOLIMIT_SHIFT 8 492 #define PCI_BRIDGE_STATIO_STATUS_SHIFT 16 493 #define PCI_BRIDGE_STATIO_IOBASE_MASK 0xf0 494 #define PCI_BRIDGE_STATIO_IOLIMIT_MASK 0xf0 495 #define PCI_BRIDGE_STATIO_STATUS_MASK 0xffff 496 #define PCI_BRIDGE_IO_32BITS(reg) (((reg) & 0xf) == 1) 497 498 #define PCI_BRIDGE_MEMORY_REG 0x20 499 #define PCI_BRIDGE_MEMORY_BASE_SHIFT 4 500 #define PCI_BRIDGE_MEMORY_LIMIT_SHIFT 20 501 #define PCI_BRIDGE_MEMORY_BASE_MASK 0xffff 502 #define PCI_BRIDGE_MEMORY_LIMIT_MASK 0xffff 503 504 #define PCI_BRIDGE_PREFETCHMEM_REG 0x24 505 #define PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT 4 506 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT 20 507 #define PCI_BRIDGE_PREFETCHMEM_BASE_MASK 0xffff 508 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK 0xffff 509 #define PCI_BRIDGE_PREFETCHMEM_64BITS(reg) ((reg) & 0xf) 510 511 #define PCI_BRIDGE_PREFETCHBASE32_REG 0x28 512 #define PCI_BRIDGE_PREFETCHLIMIT32_REG 0x2C 513 514 #define PCI_BRIDGE_IOHIGH_REG 0x30 515 #define PCI_BRIDGE_IOHIGH_BASE_SHIFT 0 516 #define PCI_BRIDGE_IOHIGH_LIMIT_SHIFT 16 517 #define PCI_BRIDGE_IOHIGH_BASE_MASK 0xffff 518 #define PCI_BRIDGE_IOHIGH_LIMIT_MASK 0xffff 519 520 #define PCI_BRIDGE_CONTROL_REG 0x3C 521 #define PCI_BRIDGE_CONTROL_SHIFT 16 522 #define PCI_BRIDGE_CONTROL_MASK 0xffff 523 #define PCI_BRIDGE_CONTROL_PERE (1 << 0) 524 #define PCI_BRIDGE_CONTROL_SERR (1 << 1) 525 #define PCI_BRIDGE_CONTROL_ISA (1 << 2) 526 #define PCI_BRIDGE_CONTROL_VGA (1 << 3) 527 /* Reserved (1 << 4) */ 528 #define PCI_BRIDGE_CONTROL_MABRT (1 << 5) 529 #define PCI_BRIDGE_CONTROL_SECBR (1 << 6) 530 #define PCI_BRIDGE_CONTROL_SECFASTB2B (1 << 7) 531 #define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER (1 << 8) 532 #define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER (1 << 9) 533 #define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT (1 << 10) 534 #define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR (1 << 11) 535 /* Reserved (1 << 12) - (1 << 15) */ 536 537 /* 538 * Vital Product Data resource tags. 539 */ 540 struct pci_vpd_smallres { 541 uint8_t vpdres_byte0; /* length of data + tag */ 542 /* Actual data. */ 543 } __attribute__((__packed__)); 544 545 struct pci_vpd_largeres { 546 uint8_t vpdres_byte0; 547 uint8_t vpdres_len_lsb; /* length of data only */ 548 uint8_t vpdres_len_msb; 549 /* Actual data. */ 550 } __attribute__((__packed__)); 551 552 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 553 554 #define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) 555 #define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) 556 557 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 558 559 #define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ 560 #define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ 561 #define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ 562 563 #define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ 564 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 565 566 struct pci_vpd { 567 uint8_t vpd_key0; 568 uint8_t vpd_key1; 569 uint8_t vpd_len; /* length of data only */ 570 /* Actual data. */ 571 } __attribute__((__packed__)); 572 573 /* 574 * Recommended VPD fields: 575 * 576 * PN Part number of assembly 577 * FN FRU part number 578 * EC EC level of assembly 579 * MN Manufacture ID 580 * SN Serial Number 581 * 582 * Conditionally recommended VPD fields: 583 * 584 * LI Load ID 585 * RL ROM Level 586 * RM Alterable ROM Level 587 * NA Network Address 588 * DD Device Driver Level 589 * DG Diagnostic Level 590 * LL Loadable Microcode Level 591 * VI Vendor ID/Device ID 592 * FU Function Number 593 * SI Subsystem Vendor ID/Subsystem ID 594 * 595 * Additional VPD fields: 596 * 597 * Z0-ZZ User/Product Specific 598 */ 599 600 #endif /* _DEV_PCI_PCIREG_H_ */ 601