1 /* $NetBSD: pcscp.c,v 1.45 2010/11/13 13:52:08 uebayasi Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center; Izumi Tsutsui. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 35 * written by Izumi Tsutsui <tsutsui@NetBSD.org> 36 * 37 * Technical manual available at 38 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/19113.pdf 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: pcscp.c,v 1.45 2010/11/13 13:52:08 uebayasi Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/buf.h> 48 49 #include <sys/bus.h> 50 #include <sys/intr.h> 51 52 #include <dev/scsipi/scsipi_all.h> 53 #include <dev/scsipi/scsi_all.h> 54 #include <dev/scsipi/scsiconf.h> 55 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pcidevs.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 #include <dev/pci/pcscpreg.h> 64 65 #define IO_MAP_REG 0x10 66 67 struct pcscp_softc { 68 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 69 70 bus_space_tag_t sc_st; /* bus space tag */ 71 bus_space_handle_t sc_sh; /* bus space handle */ 72 void *sc_ih; /* interrupt cookie */ 73 74 bus_dma_tag_t sc_dmat; /* DMA tag */ 75 76 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 77 78 uint32_t *sc_mdladdr; /* MDL array */ 79 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 80 81 int sc_active; /* DMA state */ 82 int sc_datain; /* DMA Data Direction */ 83 size_t sc_dmasize; /* DMA size */ 84 uint8_t **sc_dmaaddr; /* DMA address */ 85 size_t *sc_dmalen; /* DMA length */ 86 }; 87 88 #define READ_DMAREG(sc, reg) \ 89 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 90 #define WRITE_DMAREG(sc, reg, var) \ 91 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 92 93 #define PCSCP_READ_REG(sc, reg) \ 94 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2) 95 #define PCSCP_WRITE_REG(sc, reg, val) \ 96 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2, (val)) 97 98 99 static int pcscp_match(device_t, cfdata_t, void *); 100 static void pcscp_attach(device_t, device_t, void *); 101 102 CFATTACH_DECL_NEW(pcscp, sizeof(struct pcscp_softc), 103 pcscp_match, pcscp_attach, NULL, NULL); 104 105 /* 106 * Functions and the switch for the MI code. 107 */ 108 109 static uint8_t pcscp_read_reg(struct ncr53c9x_softc *, int); 110 static void pcscp_write_reg(struct ncr53c9x_softc *, int, uint8_t); 111 static int pcscp_dma_isintr(struct ncr53c9x_softc *); 112 static void pcscp_dma_reset(struct ncr53c9x_softc *); 113 static int pcscp_dma_intr(struct ncr53c9x_softc *); 114 static int pcscp_dma_setup(struct ncr53c9x_softc *, uint8_t **, size_t *, 115 int, size_t *); 116 static void pcscp_dma_go(struct ncr53c9x_softc *); 117 static void pcscp_dma_stop(struct ncr53c9x_softc *); 118 static int pcscp_dma_isactive(struct ncr53c9x_softc *); 119 120 static struct ncr53c9x_glue pcscp_glue = { 121 pcscp_read_reg, 122 pcscp_write_reg, 123 pcscp_dma_isintr, 124 pcscp_dma_reset, 125 pcscp_dma_intr, 126 pcscp_dma_setup, 127 pcscp_dma_go, 128 pcscp_dma_stop, 129 pcscp_dma_isactive, 130 NULL, /* gl_clear_latched_intr */ 131 }; 132 133 static int 134 pcscp_match(device_t parent, cfdata_t cf, void *aux) 135 { 136 struct pci_attach_args *pa = aux; 137 138 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 139 return 0; 140 141 switch (PCI_PRODUCT(pa->pa_id)) { 142 case PCI_PRODUCT_AMD_PCSCSI_PCI: 143 return 1; 144 } 145 return 0; 146 } 147 148 /* 149 * Attach this instance, and then all the sub-devices 150 */ 151 static void 152 pcscp_attach(device_t parent, device_t self, void *aux) 153 { 154 struct pcscp_softc *esc = device_private(self); 155 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 156 struct pci_attach_args *pa = aux; 157 bus_space_tag_t iot; 158 bus_space_handle_t ioh; 159 pci_intr_handle_t ih; 160 const char *intrstr; 161 pcireg_t csr; 162 bus_dma_segment_t seg; 163 int error, rseg; 164 char devinfo[256]; 165 166 sc->sc_dev = self; 167 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 168 aprint_normal(": %s\n", devinfo); 169 aprint_normal("%s", device_xname(sc->sc_dev)); 170 171 if (pci_mapreg_map(pa, IO_MAP_REG, PCI_MAPREG_TYPE_IO, 0, 172 &iot, &ioh, NULL, NULL)) { 173 aprint_error(": unable to map registers\n"); 174 return; 175 } 176 177 sc->sc_glue = &pcscp_glue; 178 179 esc->sc_st = iot; 180 esc->sc_sh = ioh; 181 esc->sc_dmat = pa->pa_dmat; 182 183 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 184 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 185 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 186 187 /* 188 * XXX More of this should be in ncr53c9x_attach(), but 189 * XXX should we really poke around the chip that much in 190 * XXX the MI code? Think about this more... 191 */ 192 193 /* 194 * Set up static configuration info. 195 */ 196 197 /* 198 * XXX should read configuration from EEPROM? 199 * 200 * MI ncr53c9x driver does not support configuration 201 * per each target device, though... 202 */ 203 sc->sc_id = 7; 204 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 205 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 206 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 207 sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE; 208 sc->sc_rev = NCR_VARIANT_AM53C974; 209 sc->sc_features = NCR_F_FASTSCSI; 210 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 211 sc->sc_freq = 40; /* MHz */ 212 213 /* 214 * XXX minsync and maxxfer _should_ be set up in MI code, 215 * XXX but it appears to have some dependency on what sort 216 * XXX of DMA we're hooked up to, etc. 217 */ 218 219 /* 220 * This is the value used to start sync negotiations 221 * Note that the NCR register "SYNCTP" is programmed 222 * in "clocks per byte", and has a minimum value of 4. 223 * The SCSI period used in negotiation is one-fourth 224 * of the time (in nanoseconds) needed to transfer one byte. 225 * Since the chip's clock is given in MHz, we have the following 226 * formula: 4 * period = (1000 / freq) * 4 227 */ 228 229 sc->sc_minsync = 1000 / sc->sc_freq; 230 231 /* Really no limit, but since we want to fit into the TCR... */ 232 sc->sc_maxxfer = 16 * 1024 * 1024; 233 234 /* 235 * Create the DMA maps for the data transfers. 236 */ 237 238 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 239 #define MDL_SEG_OFFSET 0x0FFF 240 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 241 242 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MDL_SEG_SIZE, 243 MDL_SEG_SIZE, BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 244 aprint_error(": can't create DMA maps\n"); 245 return; 246 } 247 248 /* 249 * Allocate and map memory for the MDL. 250 */ 251 252 if ((error = bus_dmamem_alloc(esc->sc_dmat, 253 sizeof(uint32_t) * MDL_SIZE, PAGE_SIZE, 0, &seg, 1, &rseg, 254 BUS_DMA_NOWAIT)) != 0) { 255 aprint_error(": unable to allocate memory for the MDL," 256 " error = %d\n", error); 257 goto fail_0; 258 } 259 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 260 sizeof(uint32_t) * MDL_SIZE , (void **)&esc->sc_mdladdr, 261 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 262 aprint_error(": unable to map the MDL memory, error = %d\n", 263 error); 264 goto fail_1; 265 } 266 if ((error = bus_dmamap_create(esc->sc_dmat, 267 sizeof(uint32_t) * MDL_SIZE, 1, sizeof(uint32_t) * MDL_SIZE, 268 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 269 aprint_error(": unable to map_create for the MDL, error = %d\n", 270 error); 271 goto fail_2; 272 } 273 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 274 esc->sc_mdladdr, sizeof(uint32_t) * MDL_SIZE, 275 NULL, BUS_DMA_NOWAIT)) != 0) { 276 aprint_error(": unable to load for the MDL, error = %d\n", 277 error); 278 goto fail_3; 279 } 280 281 /* map and establish interrupt */ 282 if (pci_intr_map(pa, &ih)) { 283 aprint_error(": couldn't map interrupt\n"); 284 goto fail_4; 285 } 286 287 intrstr = pci_intr_string(pa->pa_pc, ih); 288 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 289 ncr53c9x_intr, esc); 290 if (esc->sc_ih == NULL) { 291 aprint_error(": couldn't establish interrupt"); 292 if (intrstr != NULL) 293 aprint_error(" at %s", intrstr); 294 aprint_error("\n"); 295 goto fail_4; 296 } 297 if (intrstr != NULL) { 298 aprint_normal(": interrupting at %s\n", intrstr); 299 aprint_normal("%s", device_xname(sc->sc_dev)); 300 } 301 302 /* Do the common parts of attachment. */ 303 sc->sc_adapter.adapt_minphys = minphys; 304 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 305 ncr53c9x_attach(sc); 306 307 /* Turn on target selection using the `DMA' method */ 308 sc->sc_features |= NCR_F_DMASELECT; 309 310 return; 311 312 fail_4: 313 bus_dmamap_unload(esc->sc_dmat, esc->sc_mdldmap); 314 fail_3: 315 bus_dmamap_destroy(esc->sc_dmat, esc->sc_mdldmap); 316 fail_2: 317 bus_dmamem_unmap(esc->sc_dmat, (void *)esc->sc_mdldmap, 318 sizeof(uint32_t) * MDL_SIZE); 319 fail_1: 320 bus_dmamem_free(esc->sc_dmat, &seg, rseg); 321 fail_0: 322 bus_dmamap_destroy(esc->sc_dmat, esc->sc_xfermap); 323 } 324 325 /* 326 * Glue functions. 327 */ 328 329 static uint8_t 330 pcscp_read_reg(struct ncr53c9x_softc *sc, int reg) 331 { 332 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 333 334 return PCSCP_READ_REG(esc, reg); 335 } 336 337 static void 338 pcscp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t v) 339 { 340 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 341 342 PCSCP_WRITE_REG(esc, reg, v); 343 } 344 345 static int 346 pcscp_dma_isintr(struct ncr53c9x_softc *sc) 347 { 348 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 349 350 return (PCSCP_READ_REG(esc, NCR_STAT) & NCRSTAT_INT) != 0; 351 } 352 353 static void 354 pcscp_dma_reset(struct ncr53c9x_softc *sc) 355 { 356 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 357 358 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 359 360 esc->sc_active = 0; 361 } 362 363 static int 364 pcscp_dma_intr(struct ncr53c9x_softc *sc) 365 { 366 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 367 int trans, resid, i; 368 bus_dmamap_t dmap = esc->sc_xfermap; 369 int datain = esc->sc_datain; 370 uint32_t dmastat; 371 uint8_t *p = NULL; 372 373 dmastat = READ_DMAREG(esc, DMA_STAT); 374 375 if (dmastat & DMASTAT_ERR) { 376 /* XXX not tested... */ 377 WRITE_DMAREG(esc, DMA_CMD, 378 DMACMD_ABORT | (datain ? DMACMD_DIR : 0)); 379 380 printf("%s: error: DMA error detected; Aborting.\n", 381 device_xname(sc->sc_dev)); 382 bus_dmamap_unload(esc->sc_dmat, dmap); 383 return -1; 384 } 385 386 if (dmastat & DMASTAT_ABT) { 387 /* XXX What should be done? */ 388 printf("%s: %s: DMA aborted.\n", 389 device_xname(sc->sc_dev), __func__); 390 WRITE_DMAREG(esc, DMA_CMD, 391 DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 392 esc->sc_active = 0; 393 return 0; 394 } 395 396 #ifdef DIAGNOSTIC 397 /* This is an "assertion" :) */ 398 if (esc->sc_active == 0) 399 panic("%s: %s: DMA wasn't active", 400 device_xname(sc->sc_dev), __func__); 401 #endif 402 403 /* DMA has stopped */ 404 405 esc->sc_active = 0; 406 407 if (esc->sc_dmasize == 0) { 408 /* A "Transfer Pad" operation completed */ 409 NCR_DMA(("%s: discarded %d bytes (tcl=%d, tcm=%d)\n", 410 __func__, 411 PCSCP_READ_REG(esc, NCR_TCL) | 412 (PCSCP_READ_REG(esc, NCR_TCM) << 8), 413 PCSCP_READ_REG(esc, NCR_TCL), 414 PCSCP_READ_REG(esc, NCR_TCM))); 415 return 0; 416 } 417 418 resid = 0; 419 /* 420 * If a transfer onto the SCSI bus gets interrupted by the device 421 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 422 * as residual since the ESP counter registers get decremented as 423 * bytes are clocked into the FIFO. 424 */ 425 if (!datain && 426 (resid = (PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 427 NCR_DMA(("%s: empty esp FIFO of %d ", __func__, resid)); 428 } 429 430 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 431 /* 432 * `Terminal count' is off, so read the residue 433 * out of the ESP counter registers. 434 */ 435 if (datain) { 436 resid = PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 437 while (resid > 1) 438 resid = 439 PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 440 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 441 (datain ? DMACMD_DIR : 0)); 442 443 for (i = 0; i < 1000; i++) { /* XXX */ 444 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 445 break; 446 DELAY(1); 447 } 448 449 /* See the below comments... */ 450 if (resid) 451 p = *esc->sc_dmaaddr; 452 } 453 454 resid += PCSCP_READ_REG(esc, NCR_TCL) | 455 (PCSCP_READ_REG(esc, NCR_TCM) << 8) | 456 (PCSCP_READ_REG(esc, NCR_TCH) << 16); 457 } else { 458 while ((dmastat & DMASTAT_DONE) == 0) 459 dmastat = READ_DMAREG(esc, DMA_STAT); 460 } 461 462 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 463 464 /* sync MDL */ 465 bus_dmamap_sync(esc->sc_dmat, esc->sc_mdldmap, 466 0, sizeof(uint32_t) * dmap->dm_nsegs, BUS_DMASYNC_POSTWRITE); 467 /* sync transfer buffer */ 468 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 469 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 470 bus_dmamap_unload(esc->sc_dmat, dmap); 471 472 trans = esc->sc_dmasize - resid; 473 474 /* 475 * From the technical manual notes: 476 * 477 * `In some odd byte conditions, one residual byte will be left 478 * in the SCSI FIFO, and the FIFO flags will never count to 0. 479 * When this happens, the residual byte should be retrieved 480 * via PIO following completion of the BLAST operation.' 481 */ 482 483 if (p) { 484 p += trans; 485 *p = PCSCP_READ_REG(esc, NCR_FIFO); 486 trans++; 487 } 488 489 if (trans < 0) { /* transferred < 0 ? */ 490 #if 0 491 /* 492 * This situation can happen in perfectly normal operation 493 * if the ESP is reselected while using DMA to select 494 * another target. As such, don't print the warning. 495 */ 496 printf("%s: xfer (%d) > req (%d)\n", 497 device_xname(sc->sc_dev), trans, esc->sc_dmasize); 498 #endif 499 trans = esc->sc_dmasize; 500 } 501 502 NCR_DMA(("%s: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 503 __func__, 504 PCSCP_READ_REG(esc, NCR_TCL), 505 PCSCP_READ_REG(esc, NCR_TCM), 506 PCSCP_READ_REG(esc, NCR_TCH), 507 trans, resid)); 508 509 *esc->sc_dmalen -= trans; 510 *esc->sc_dmaaddr += trans; 511 512 return 0; 513 } 514 515 static int 516 pcscp_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 517 int datain, size_t *dmasize) 518 { 519 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 520 bus_dmamap_t dmap = esc->sc_xfermap; 521 uint32_t *mdl; 522 int error, nseg, seg; 523 bus_addr_t s_offset, s_addr; 524 525 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 526 527 esc->sc_dmaaddr = addr; 528 esc->sc_dmalen = len; 529 esc->sc_dmasize = *dmasize; 530 esc->sc_datain = datain; 531 532 #ifdef DIAGNOSTIC 533 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 534 panic("%s: transfer size too large", device_xname(sc->sc_dev)); 535 #endif 536 537 /* 538 * No need to set up DMA in `Transfer Pad' operation. 539 * (case of *dmasize == 0) 540 */ 541 if (*dmasize == 0) 542 return 0; 543 544 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 545 *esc->sc_dmalen, NULL, 546 ((sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP) ? 547 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 548 ((sc->sc_nexus->xs->xs_control & XS_CTL_DATA_IN) ? 549 BUS_DMA_READ : BUS_DMA_WRITE)); 550 if (error) { 551 printf("%s: unable to load dmamap, error = %d\n", 552 device_xname(sc->sc_dev), error); 553 return error; 554 } 555 556 /* set transfer length */ 557 WRITE_DMAREG(esc, DMA_STC, *dmasize); 558 559 /* set up MDL */ 560 mdl = esc->sc_mdladdr; 561 nseg = dmap->dm_nsegs; 562 563 /* the first segment is possibly not aligned with 4k MDL boundary */ 564 s_addr = dmap->dm_segs[0].ds_addr; 565 s_offset = s_addr & MDL_SEG_OFFSET; 566 s_addr -= s_offset; 567 568 /* set the first MDL and offset */ 569 WRITE_DMAREG(esc, DMA_SPA, s_offset); 570 *mdl++ = htole32(s_addr); 571 572 /* the rest dmamap segments are aligned with 4k boundary */ 573 for (seg = 1; seg < nseg; seg++) 574 *mdl++ = htole32(dmap->dm_segs[seg].ds_addr); 575 576 return 0; 577 } 578 579 static void 580 pcscp_dma_go(struct ncr53c9x_softc *sc) 581 { 582 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 583 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 584 int datain = esc->sc_datain; 585 586 /* No DMA transfer in Transfer Pad operation */ 587 if (esc->sc_dmasize == 0) 588 return; 589 590 /* sync transfer buffer */ 591 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 592 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 593 594 /* sync MDL */ 595 bus_dmamap_sync(esc->sc_dmat, mdldmap, 596 0, sizeof(uint32_t) * dmap->dm_nsegs, BUS_DMASYNC_PREWRITE); 597 598 /* set Starting MDL Address */ 599 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 600 601 /* set DMA command register bits */ 602 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 603 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 604 /* DMACMD_INTE | */ 605 (datain ? DMACMD_DIR : 0)); 606 607 /* issue DMA start command */ 608 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 609 /* DMACMD_INTE | */ 610 (datain ? DMACMD_DIR : 0)); 611 612 esc->sc_active = 1; 613 } 614 615 static void 616 pcscp_dma_stop(struct ncr53c9x_softc *sc) 617 { 618 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 619 620 /* DMA stop */ 621 /* XXX What should we do here ? */ 622 WRITE_DMAREG(esc, DMA_CMD, 623 DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0)); 624 bus_dmamap_unload(esc->sc_dmat, esc->sc_xfermap); 625 626 esc->sc_active = 0; 627 } 628 629 static int 630 pcscp_dma_isactive(struct ncr53c9x_softc *sc) 631 { 632 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 633 634 /* XXX should check esc->sc_active? */ 635 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 636 return 1; 637 return 0; 638 } 639