1 /* $NetBSD: pcscp.c,v 1.22 2002/11/25 13:41:35 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center; Izumi Tsutsui. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 42 * written by Izumi Tsutsui <tsutsui@ceres.dti.ne.jp> 43 * 44 * Technical manual available at 45 * http://www.amd.com/products/npd/techdocs/techdocs.html 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: pcscp.c,v 1.22 2002/11/25 13:41:35 tsutsui Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 56 #include <machine/bus.h> 57 #include <machine/intr.h> 58 #include <machine/endian.h> 59 60 #include <uvm/uvm_extern.h> 61 62 #include <dev/scsipi/scsipi_all.h> 63 #include <dev/scsipi/scsi_all.h> 64 #include <dev/scsipi/scsiconf.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 70 #include <dev/ic/ncr53c9xreg.h> 71 #include <dev/ic/ncr53c9xvar.h> 72 73 #include <dev/pci/pcscpreg.h> 74 75 #define IO_MAP_REG 0x10 76 77 struct pcscp_softc { 78 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 79 80 bus_space_tag_t sc_st; /* bus space tag */ 81 bus_space_handle_t sc_sh; /* bus space handle */ 82 void *sc_ih; /* interrupt cookie */ 83 84 bus_dma_tag_t sc_dmat; /* DMA tag */ 85 86 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 87 88 u_int32_t *sc_mdladdr; /* MDL array */ 89 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 90 91 int sc_active; /* DMA state */ 92 int sc_datain; /* DMA Data Direction */ 93 size_t sc_dmasize; /* DMA size */ 94 char **sc_dmaaddr; /* DMA address */ 95 size_t *sc_dmalen; /* DMA length */ 96 }; 97 98 #define READ_DMAREG(sc, reg) \ 99 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 100 #define WRITE_DMAREG(sc, reg, var) \ 101 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 102 103 /* don't have to use MI defines in MD code... */ 104 #undef NCR_READ_REG 105 #define NCR_READ_REG(sc, reg) pcscp_read_reg((sc), (reg)) 106 #undef NCR_WRITE_REG 107 #define NCR_WRITE_REG(sc, reg, val) pcscp_write_reg((sc), (reg), (val)) 108 109 int pcscp_match __P((struct device *, struct cfdata *, void *)); 110 void pcscp_attach __P((struct device *, struct device *, void *)); 111 112 CFATTACH_DECL(pcscp, sizeof(struct pcscp_softc), 113 pcscp_match, pcscp_attach, NULL, NULL); 114 115 /* 116 * Functions and the switch for the MI code. 117 */ 118 119 u_char pcscp_read_reg __P((struct ncr53c9x_softc *, int)); 120 void pcscp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 121 int pcscp_dma_isintr __P((struct ncr53c9x_softc *)); 122 void pcscp_dma_reset __P((struct ncr53c9x_softc *)); 123 int pcscp_dma_intr __P((struct ncr53c9x_softc *)); 124 int pcscp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 125 size_t *, int, size_t *)); 126 void pcscp_dma_go __P((struct ncr53c9x_softc *)); 127 void pcscp_dma_stop __P((struct ncr53c9x_softc *)); 128 int pcscp_dma_isactive __P((struct ncr53c9x_softc *)); 129 130 struct ncr53c9x_glue pcscp_glue = { 131 pcscp_read_reg, 132 pcscp_write_reg, 133 pcscp_dma_isintr, 134 pcscp_dma_reset, 135 pcscp_dma_intr, 136 pcscp_dma_setup, 137 pcscp_dma_go, 138 pcscp_dma_stop, 139 pcscp_dma_isactive, 140 NULL, /* gl_clear_latched_intr */ 141 }; 142 143 int 144 pcscp_match(parent, match, aux) 145 struct device *parent; 146 struct cfdata *match; 147 void *aux; 148 { 149 struct pci_attach_args *pa = aux; 150 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 151 return 0; 152 153 switch (PCI_PRODUCT(pa->pa_id)) { 154 case PCI_PRODUCT_AMD_PCSCSI_PCI: 155 return 1; 156 } 157 return 0; 158 } 159 160 /* 161 * Attach this instance, and then all the sub-devices 162 */ 163 void 164 pcscp_attach(parent, self, aux) 165 struct device *parent, *self; 166 void *aux; 167 { 168 struct pci_attach_args *pa = aux; 169 struct pcscp_softc *esc = (void *)self; 170 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 171 bus_space_tag_t iot; 172 bus_space_handle_t ioh; 173 pci_intr_handle_t ih; 174 const char *intrstr; 175 pcireg_t csr; 176 bus_dma_segment_t seg; 177 int error, rseg; 178 char devinfo[256]; 179 180 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 181 printf(": %s\n", devinfo); 182 183 if (pci_mapreg_map(pa, IO_MAP_REG, PCI_MAPREG_TYPE_IO, 0, 184 &iot, &ioh, NULL, NULL)) { 185 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 186 return; 187 } 188 189 sc->sc_glue = &pcscp_glue; 190 191 esc->sc_st = iot; 192 esc->sc_sh = ioh; 193 esc->sc_dmat = pa->pa_dmat; 194 195 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 196 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 197 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 198 199 /* 200 * XXX More of this should be in ncr53c9x_attach(), but 201 * XXX should we really poke around the chip that much in 202 * XXX the MI code? Think about this more... 203 */ 204 205 /* 206 * Set up static configuration info. 207 */ 208 209 /* 210 * XXX should read configuration from EEPROM? 211 * 212 * MI ncr53c9x driver does not support configuration 213 * per each target device, though... 214 */ 215 sc->sc_id = 7; 216 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 217 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 218 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 219 sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE; 220 sc->sc_rev = NCR_VARIANT_AM53C974; 221 sc->sc_features = NCR_F_FASTSCSI; 222 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 223 sc->sc_freq = 40; /* MHz */ 224 225 /* 226 * XXX minsync and maxxfer _should_ be set up in MI code, 227 * XXX but it appears to have some dependency on what sort 228 * XXX of DMA we're hooked up to, etc. 229 */ 230 231 /* 232 * This is the value used to start sync negotiations 233 * Note that the NCR register "SYNCTP" is programmed 234 * in "clocks per byte", and has a minimum value of 4. 235 * The SCSI period used in negotiation is one-fourth 236 * of the time (in nanoseconds) needed to transfer one byte. 237 * Since the chip's clock is given in MHz, we have the following 238 * formula: 4 * period = (1000 / freq) * 4 239 */ 240 241 sc->sc_minsync = 1000 / sc->sc_freq; 242 243 /* Really no limit, but since we want to fit into the TCR... */ 244 sc->sc_maxxfer = 16 * 1024 * 1024; 245 246 /* map and establish interrupt */ 247 if (pci_intr_map(pa, &ih)) { 248 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 249 return; 250 } 251 252 intrstr = pci_intr_string(pa->pa_pc, ih); 253 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 254 ncr53c9x_intr, esc); 255 if (esc->sc_ih == NULL) { 256 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 257 if (intrstr != NULL) 258 printf(" at %s", intrstr); 259 printf("\n"); 260 return; 261 } 262 if (intrstr != NULL) 263 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 264 intrstr); 265 266 /* 267 * Create the DMA maps for the data transfers. 268 */ 269 270 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 271 #define MDL_SEG_OFFSET 0x0FFF 272 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 273 274 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MAXPHYS, 0, 275 BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 276 printf("%s: can't create dma maps\n", sc->sc_dev.dv_xname); 277 return; 278 } 279 280 /* 281 * Allocate and map memory for the MDL. 282 */ 283 284 if ((error = bus_dmamem_alloc(esc->sc_dmat, 285 sizeof(u_int32_t) * MDL_SIZE, PAGE_SIZE, 0, &seg, 1, &rseg, 286 BUS_DMA_NOWAIT)) != 0) { 287 printf("%s: unable to allocate memory for the MDL, " 288 "error = %d\n", sc->sc_dev.dv_xname, error); 289 return; 290 } 291 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 292 sizeof(u_int32_t) * MDL_SIZE , (caddr_t *)&esc->sc_mdladdr, 293 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 294 printf("%s: unable to map the MDL memory, error = %d\n", 295 sc->sc_dev.dv_xname, error); 296 return; 297 } 298 if ((error = bus_dmamap_create(esc->sc_dmat, 299 sizeof(u_int32_t) * MDL_SIZE, 1, sizeof(u_int32_t) * MDL_SIZE, 300 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 301 printf("%s: unable to map_create for the MDL, error = %d\n", 302 sc->sc_dev.dv_xname, error); 303 return; 304 } 305 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 306 esc->sc_mdladdr, sizeof(u_int32_t) * MDL_SIZE, 307 NULL, BUS_DMA_NOWAIT)) != 0) { 308 printf("%s: unable to load for the MDL, error = %d\n", 309 sc->sc_dev.dv_xname, error); 310 return; 311 } 312 313 /* Do the common parts of attachment. */ 314 printf("%s", sc->sc_dev.dv_xname); 315 316 sc->sc_adapter.adapt_minphys = minphys; 317 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 318 ncr53c9x_attach(sc); 319 320 /* Turn on target selection using the `dma' method */ 321 sc->sc_features |= NCR_F_DMASELECT; 322 } 323 324 /* 325 * Glue functions. 326 */ 327 328 u_char 329 pcscp_read_reg(sc, reg) 330 struct ncr53c9x_softc *sc; 331 int reg; 332 { 333 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 334 335 return bus_space_read_1(esc->sc_st, esc->sc_sh, reg << 2); 336 } 337 338 void 339 pcscp_write_reg(sc, reg, v) 340 struct ncr53c9x_softc *sc; 341 int reg; 342 u_char v; 343 { 344 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 345 346 bus_space_write_1(esc->sc_st, esc->sc_sh, reg << 2, v); 347 } 348 349 int 350 pcscp_dma_isintr(sc) 351 struct ncr53c9x_softc *sc; 352 { 353 354 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 355 } 356 357 void 358 pcscp_dma_reset(sc) 359 struct ncr53c9x_softc *sc; 360 { 361 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 362 363 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 364 365 esc->sc_active = 0; 366 } 367 368 int 369 pcscp_dma_intr(sc) 370 struct ncr53c9x_softc *sc; 371 { 372 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 373 int trans, resid, i; 374 bus_dmamap_t dmap = esc->sc_xfermap; 375 int datain = esc->sc_datain; 376 u_int32_t dmastat; 377 char *p = NULL; 378 379 dmastat = READ_DMAREG(esc, DMA_STAT); 380 381 if (dmastat & DMASTAT_ERR) { 382 /* XXX not tested... */ 383 WRITE_DMAREG(esc, DMA_CMD, 384 DMACMD_ABORT | (datain ? DMACMD_DIR : 0)); 385 386 printf("%s: error: DMA error detected; Aborting.\n", 387 sc->sc_dev.dv_xname); 388 bus_dmamap_unload(esc->sc_dmat, dmap); 389 return -1; 390 } 391 392 if (dmastat & DMASTAT_ABT) { 393 /* XXX What should be done? */ 394 printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname); 395 WRITE_DMAREG(esc, DMA_CMD, 396 DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 397 esc->sc_active = 0; 398 return 0; 399 } 400 401 /* This is an "assertion" :) */ 402 if (esc->sc_active == 0) 403 panic("pcscp dmaintr: DMA wasn't active"); 404 405 /* DMA has stopped */ 406 407 esc->sc_active = 0; 408 409 if (esc->sc_dmasize == 0) { 410 /* A "Transfer Pad" operation completed */ 411 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 412 NCR_READ_REG(sc, NCR_TCL) | 413 (NCR_READ_REG(sc, NCR_TCM) << 8), 414 NCR_READ_REG(sc, NCR_TCL), 415 NCR_READ_REG(sc, NCR_TCM))); 416 return 0; 417 } 418 419 resid = 0; 420 /* 421 * If a transfer onto the SCSI bus gets interrupted by the device 422 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 423 * as residual since the ESP counter registers get decremented as 424 * bytes are clocked into the FIFO. 425 */ 426 if (!datain && 427 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 428 NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid)); 429 } 430 431 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 432 /* 433 * `Terminal count' is off, so read the residue 434 * out of the ESP counter registers. 435 */ 436 if (datain) { 437 resid = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 438 while (resid > 1) 439 resid = 440 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 441 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 442 (datain ? DMACMD_DIR : 0)); 443 444 for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */ 445 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 446 break; 447 448 /* See the below comments... */ 449 if (resid) 450 p = *esc->sc_dmaaddr; 451 } 452 453 resid += (NCR_READ_REG(sc, NCR_TCL) | 454 (NCR_READ_REG(sc, NCR_TCM) << 8) | 455 ((sc->sc_cfg2 & NCRCFG2_FE) 456 ? (NCR_READ_REG(sc, NCR_TCH) << 16) : 0)); 457 458 if (resid == 0 && esc->sc_dmasize == 65536 && 459 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 460 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 461 resid = 65536; 462 } else { 463 while((dmastat & DMASTAT_DONE) == 0) 464 dmastat = READ_DMAREG(esc, DMA_STAT); 465 } 466 467 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 468 469 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 470 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 471 bus_dmamap_unload(esc->sc_dmat, dmap); 472 473 trans = esc->sc_dmasize - resid; 474 475 /* 476 * From the technical manual notes: 477 * 478 * `In some odd byte conditions, one residual byte will be left 479 * in the SCSI FIFO, and the FIFO flags will never count to 0. 480 * When this happens, the residual byte should be retrieved 481 * via PIO following completion of the BLAST operation.' 482 */ 483 484 if (p) { 485 p += trans; 486 *p = NCR_READ_REG(sc, NCR_FIFO); 487 trans++; 488 } 489 490 if (trans < 0) { /* transferred < 0 ? */ 491 #if 0 492 /* 493 * This situation can happen in perfectly normal operation 494 * if the ESP is reselected while using DMA to select 495 * another target. As such, don't print the warning. 496 */ 497 printf("%s: xfer (%d) > req (%d)\n", 498 sc->sc_dev.dv_xname, trans, esc->sc_dmasize); 499 #endif 500 trans = esc->sc_dmasize; 501 } 502 503 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 504 NCR_READ_REG(sc, NCR_TCL), 505 NCR_READ_REG(sc, NCR_TCM), 506 (sc->sc_cfg2 & NCRCFG2_FE) ? NCR_READ_REG(sc, NCR_TCH) : 0, 507 trans, resid)); 508 509 *esc->sc_dmalen -= trans; 510 *esc->sc_dmaaddr += trans; 511 512 return 0; 513 } 514 515 int 516 pcscp_dma_setup(sc, addr, len, datain, dmasize) 517 struct ncr53c9x_softc *sc; 518 caddr_t *addr; 519 size_t *len; 520 int datain; 521 size_t *dmasize; 522 { 523 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 524 bus_dmamap_t dmap = esc->sc_xfermap; 525 u_int32_t *mdl; 526 int error, nseg, seg; 527 bus_addr_t s_offset, s_addr; 528 long rest, count; 529 530 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 531 532 esc->sc_dmaaddr = addr; 533 esc->sc_dmalen = len; 534 esc->sc_dmasize = *dmasize; 535 esc->sc_datain = datain; 536 537 #ifdef DIAGNOSTIC 538 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 539 panic("pcscp: transfer size too large"); 540 #endif 541 542 /* 543 * No need to set up DMA in `Transfer Pad' operation. 544 * (case of *dmasize == 0) 545 */ 546 if (*dmasize == 0) 547 return 0; 548 549 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 550 *esc->sc_dmalen, NULL, 551 ((sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP) ? 552 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 553 ((sc->sc_nexus->xs->xs_control & XS_CTL_DATA_IN) ? 554 BUS_DMA_READ : BUS_DMA_WRITE)); 555 if (error) { 556 printf("%s: unable to load dmamap, error = %d\n", 557 sc->sc_dev.dv_xname, error); 558 return error; 559 } 560 561 /* set transfer length */ 562 WRITE_DMAREG(esc, DMA_STC, *dmasize); 563 564 /* set up MDL */ 565 mdl = esc->sc_mdladdr; 566 nseg = dmap->dm_nsegs; 567 568 /* the first segment is possibly not aligned with 4k MDL boundary */ 569 count = dmap->dm_segs[0].ds_len; 570 s_addr = dmap->dm_segs[0].ds_addr; 571 s_offset = s_addr & MDL_SEG_OFFSET; 572 s_addr -= s_offset; 573 rest = MDL_SEG_SIZE - s_offset; 574 575 /* set the first MDL and offset */ 576 WRITE_DMAREG(esc, DMA_SPA, s_offset); 577 *mdl++ = htole32(s_addr); 578 count -= rest; 579 580 /* rests of the first dmamap segment */ 581 while (count > 0) { 582 s_addr += MDL_SEG_SIZE; 583 *mdl++ = htole32(s_addr); 584 count -= MDL_SEG_SIZE; 585 } 586 587 /* the rest dmamap segments are aligned with 4k boundary */ 588 for (seg = 1; seg < nseg; seg++) { 589 count = dmap->dm_segs[seg].ds_len; 590 s_addr = dmap->dm_segs[seg].ds_addr; 591 592 /* first 4kbyte of each dmamap segment */ 593 *mdl++ = htole32(s_addr); 594 count -= MDL_SEG_SIZE; 595 596 /* trailing contiguous 4k frames of each dmamap segments */ 597 while (count > 0) { 598 s_addr += MDL_SEG_SIZE; 599 *mdl++ = htole32(s_addr); 600 count -= MDL_SEG_SIZE; 601 } 602 } 603 604 return 0; 605 } 606 607 void 608 pcscp_dma_go(sc) 609 struct ncr53c9x_softc *sc; 610 { 611 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 612 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 613 int datain = esc->sc_datain; 614 615 /* No DMA transfer in Transfer Pad operation */ 616 if (esc->sc_dmasize == 0) 617 return; 618 619 /* sync transfer buffer */ 620 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 621 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 622 623 /* sync MDL */ 624 bus_dmamap_sync(esc->sc_dmat, mdldmap, 0, mdldmap->dm_mapsize, 625 BUS_DMASYNC_PREWRITE); 626 627 /* set Starting MDL Address */ 628 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 629 630 /* set DMA command register bits */ 631 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 632 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 633 /* DMACMD_INTE | */ 634 (datain ? DMACMD_DIR : 0)); 635 636 /* issue DMA start command */ 637 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 638 /* DMACMD_INTE | */ 639 (datain ? DMACMD_DIR : 0)); 640 641 esc->sc_active = 1; 642 } 643 644 void 645 pcscp_dma_stop(sc) 646 struct ncr53c9x_softc *sc; 647 { 648 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 649 650 /* dma stop */ 651 /* XXX What should we do here ? */ 652 WRITE_DMAREG(esc, DMA_CMD, 653 DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0)); 654 655 esc->sc_active = 0; 656 } 657 658 int 659 pcscp_dma_isactive(sc) 660 struct ncr53c9x_softc *sc; 661 { 662 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 663 664 /* XXX should check esc->sc_active? */ 665 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 666 return 1; 667 return 0; 668 } 669