1 /* $NetBSD: twe.c,v 1.24 2002/05/24 18:10:07 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: twe.c,v 1.1 2000/05/24 23:35:23 msmith Exp 66 */ 67 68 /* 69 * Driver for the 3ware Escalade family of RAID controllers. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: twe.c,v 1.24 2002/05/24 18:10:07 christos Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/device.h> 79 #include <sys/queue.h> 80 #include <sys/proc.h> 81 #include <sys/buf.h> 82 #include <sys/endian.h> 83 #include <sys/malloc.h> 84 #include <sys/disk.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <machine/bswap.h> 89 #include <machine/bus.h> 90 91 #include <dev/pci/pcireg.h> 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/pcidevs.h> 94 #include <dev/pci/twereg.h> 95 #include <dev/pci/twevar.h> 96 97 #define PCI_CBIO 0x10 98 99 static void twe_aen_handler(struct twe_ccb *, int); 100 static void twe_attach(struct device *, struct device *, void *); 101 static int twe_init_connection(struct twe_softc *); 102 static int twe_intr(void *); 103 static int twe_match(struct device *, struct cfdata *, void *); 104 static int twe_param_get(struct twe_softc *, int, int, size_t, 105 void (*)(struct twe_ccb *, int), void **); 106 static void twe_poll(struct twe_softc *); 107 static int twe_print(void *, const char *); 108 static int twe_reset(struct twe_softc *); 109 static int twe_submatch(struct device *, struct cfdata *, void *); 110 static int twe_status_check(struct twe_softc *, u_int); 111 static int twe_status_wait(struct twe_softc *, u_int, int); 112 113 static inline u_int32_t twe_inl(struct twe_softc *, int); 114 static inline void twe_outl(struct twe_softc *, int, u_int32_t); 115 116 struct cfattach twe_ca = { 117 sizeof(struct twe_softc), twe_match, twe_attach 118 }; 119 120 struct { 121 const u_int aen; /* High byte non-zero if w/unit */ 122 const char *desc; 123 } static const twe_aen_names[] = { 124 { 0x0000, "queue empty" }, 125 { 0x0001, "soft reset" }, 126 { 0x0102, "degraded mirror" }, 127 { 0x0003, "controller error" }, 128 { 0x0104, "rebuild fail" }, 129 { 0x0105, "rebuild done" }, 130 { 0x0106, "incompatible unit" }, 131 { 0x0107, "init done" }, 132 { 0x0108, "unclean shutdown" }, 133 { 0x0109, "aport timeout" }, 134 { 0x010a, "drive error" }, 135 { 0x010b, "rebuild started" }, 136 { 0x010c, "init started" }, 137 { 0x0015, "table undefined" }, 138 { 0x00ff, "aen queue full" }, 139 }; 140 141 static inline u_int32_t 142 twe_inl(struct twe_softc *sc, int off) 143 { 144 145 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 146 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 147 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, off)); 148 } 149 150 static inline void 151 twe_outl(struct twe_softc *sc, int off, u_int32_t val) 152 { 153 154 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 155 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 156 BUS_SPACE_BARRIER_WRITE); 157 } 158 159 /* 160 * Match a supported board. 161 */ 162 static int 163 twe_match(struct device *parent, struct cfdata *cfdata, void *aux) 164 { 165 struct pci_attach_args *pa; 166 167 pa = aux; 168 169 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3WARE && 170 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE || 171 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE_ASIC)); 172 } 173 174 /* 175 * Attach a supported board. 176 * 177 * XXX This doesn't fail gracefully. 178 */ 179 static void 180 twe_attach(struct device *parent, struct device *self, void *aux) 181 { 182 struct pci_attach_args *pa; 183 struct twe_softc *sc; 184 pci_chipset_tag_t pc; 185 pci_intr_handle_t ih; 186 pcireg_t csr; 187 const char *intrstr; 188 int size, i, rv, rseg; 189 size_t max_segs, max_xfer; 190 struct twe_param *dtp, *ctp; 191 bus_dma_segment_t seg; 192 struct twe_cmd *tc; 193 struct twe_attach_args twea; 194 struct twe_ccb *ccb; 195 196 sc = (struct twe_softc *)self; 197 pa = aux; 198 pc = pa->pa_pc; 199 sc->sc_dmat = pa->pa_dmat; 200 SIMPLEQ_INIT(&sc->sc_ccb_queue); 201 SLIST_INIT(&sc->sc_ccb_freelist); 202 203 printf(": 3ware Escalade\n"); 204 205 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 206 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 207 printf("%s: can't map i/o space\n", sc->sc_dv.dv_xname); 208 return; 209 } 210 211 /* Enable the device. */ 212 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 213 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 214 csr | PCI_COMMAND_MASTER_ENABLE); 215 216 /* Map and establish the interrupt. */ 217 if (pci_intr_map(pa, &ih)) { 218 printf("%s: can't map interrupt\n", sc->sc_dv.dv_xname); 219 return; 220 } 221 intrstr = pci_intr_string(pc, ih); 222 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, twe_intr, sc); 223 if (sc->sc_ih == NULL) { 224 printf("%s: can't establish interrupt", sc->sc_dv.dv_xname); 225 if (intrstr != NULL) 226 printf(" at %s", intrstr); 227 printf("\n"); 228 return; 229 } 230 if (intrstr != NULL) 231 printf("%s: interrupting at %s\n", sc->sc_dv.dv_xname, intrstr); 232 233 /* 234 * Allocate and initialise the command blocks and CCBs. 235 */ 236 size = sizeof(struct twe_cmd) * TWE_MAX_QUEUECNT; 237 238 if ((rv = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &seg, 1, 239 &rseg, BUS_DMA_NOWAIT)) != 0) { 240 printf("%s: unable to allocate commands, rv = %d\n", 241 sc->sc_dv.dv_xname, rv); 242 return; 243 } 244 245 if ((rv = bus_dmamem_map(sc->sc_dmat, &seg, rseg, size, 246 (caddr_t *)&sc->sc_cmds, 247 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 248 printf("%s: unable to map commands, rv = %d\n", 249 sc->sc_dv.dv_xname, rv); 250 return; 251 } 252 253 if ((rv = bus_dmamap_create(sc->sc_dmat, size, size, 1, 0, 254 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 255 printf("%s: unable to create command DMA map, rv = %d\n", 256 sc->sc_dv.dv_xname, rv); 257 return; 258 } 259 260 if ((rv = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_cmds, 261 size, NULL, BUS_DMA_NOWAIT)) != 0) { 262 printf("%s: unable to load command DMA map, rv = %d\n", 263 sc->sc_dv.dv_xname, rv); 264 return; 265 } 266 267 sc->sc_cmds_paddr = sc->sc_dmamap->dm_segs[0].ds_addr; 268 memset(sc->sc_cmds, 0, size); 269 270 ccb = malloc(sizeof(*ccb) * TWE_MAX_QUEUECNT, M_DEVBUF, M_NOWAIT); 271 sc->sc_ccbs = ccb; 272 tc = (struct twe_cmd *)sc->sc_cmds; 273 max_segs = twe_get_maxsegs(); 274 max_xfer = twe_get_maxxfer(max_segs); 275 276 for (i = 0; i < TWE_MAX_QUEUECNT; i++, tc++, ccb++) { 277 ccb->ccb_cmd = tc; 278 ccb->ccb_cmdid = i; 279 ccb->ccb_flags = 0; 280 rv = bus_dmamap_create(sc->sc_dmat, max_xfer, 281 max_segs, PAGE_SIZE, 0, 282 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 283 &ccb->ccb_dmamap_xfer); 284 if (rv != 0) { 285 printf("%s: can't create dmamap, rv = %d\n", 286 sc->sc_dv.dv_xname, rv); 287 return; 288 } 289 /* Save one CCB for parameter retrieval. */ 290 if (i != 0) 291 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, 292 ccb_chain.slist); 293 } 294 295 /* Wait for the controller to become ready. */ 296 if (twe_status_wait(sc, TWE_STS_MICROCONTROLLER_READY, 6)) { 297 printf("%s: microcontroller not ready\n", sc->sc_dv.dv_xname); 298 return; 299 } 300 301 twe_outl(sc, TWE_REG_CTL, TWE_CTL_DISABLE_INTRS); 302 303 /* Reset the controller. */ 304 if (twe_reset(sc)) { 305 printf("%s: reset failed\n", sc->sc_dv.dv_xname); 306 return; 307 } 308 309 /* Find attached units. */ 310 rv = twe_param_get(sc, TWE_PARAM_UNITSUMMARY, 311 TWE_PARAM_UNITSUMMARY_Status, TWE_MAX_UNITS, NULL, (void **)&dtp); 312 if (rv != 0) { 313 printf("%s: can't detect attached units (%d)\n", 314 sc->sc_dv.dv_xname, rv); 315 return; 316 } 317 318 /* For each detected unit, collect size and store in an array. */ 319 for (i = 0, sc->sc_nunits = 0; i < TWE_MAX_UNITS; i++) { 320 /* Unit present? */ 321 if ((dtp->tp_data[i] & TWE_PARAM_UNITSTATUS_Online) == 0) { 322 sc->sc_dsize[i] = 0; 323 continue; 324 } 325 326 rv = twe_param_get(sc, TWE_PARAM_UNITINFO + i, 327 TWE_PARAM_UNITINFO_Capacity, 4, NULL, (void **)&ctp); 328 if (rv != 0) { 329 printf("%s: error %d fetching capacity for unit %d\n", 330 sc->sc_dv.dv_xname, rv, i); 331 continue; 332 } 333 334 sc->sc_dsize[i] = le32toh(*(u_int32_t *)ctp->tp_data); 335 free(ctp, M_DEVBUF); 336 sc->sc_nunits++; 337 } 338 free(dtp, M_DEVBUF); 339 340 /* Initialise connection with controller and enable interrupts. */ 341 twe_init_connection(sc); 342 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR | 343 TWE_CTL_UNMASK_RESP_INTR | 344 TWE_CTL_ENABLE_INTRS); 345 346 /* Attach sub-devices. */ 347 for (i = 0; i < TWE_MAX_UNITS; i++) { 348 if (sc->sc_dsize[i] == 0) 349 continue; 350 twea.twea_unit = i; 351 config_found_sm(&sc->sc_dv, &twea, twe_print, twe_submatch); 352 } 353 } 354 355 /* 356 * Reset the controller. Currently only useful at attach time; must be 357 * called with interrupts blocked. 358 */ 359 static int 360 twe_reset(struct twe_softc *sc) 361 { 362 struct twe_param *tp; 363 u_int aen, status; 364 volatile u_int32_t junk; 365 int got, rv; 366 367 /* Issue a soft reset. */ 368 twe_outl(sc, TWE_REG_CTL, TWE_CTL_ISSUE_SOFT_RESET | 369 TWE_CTL_CLEAR_HOST_INTR | 370 TWE_CTL_CLEAR_ATTN_INTR | 371 TWE_CTL_MASK_CMD_INTR | 372 TWE_CTL_MASK_RESP_INTR | 373 TWE_CTL_CLEAR_ERROR_STS | 374 TWE_CTL_DISABLE_INTRS); 375 376 if (twe_status_wait(sc, TWE_STS_ATTN_INTR, 15)) { 377 printf("%s: no attention interrupt\n", 378 sc->sc_dv.dv_xname); 379 return (-1); 380 } 381 382 /* Pull AENs out of the controller; look for a soft reset AEN. */ 383 for (got = 0;;) { 384 rv = twe_param_get(sc, TWE_PARAM_AEN, TWE_PARAM_AEN_UnitCode, 385 2, NULL, (void **)&tp); 386 if (rv != 0) 387 printf("%s: error %d while draining response queue\n", 388 sc->sc_dv.dv_xname, rv); 389 aen = TWE_AEN_CODE(le16toh(*(u_int16_t *)tp->tp_data)); 390 free(tp, M_DEVBUF); 391 if (aen == TWE_AEN_QUEUE_EMPTY) 392 break; 393 if (aen == TWE_AEN_SOFT_RESET) 394 got = 1; 395 } 396 if (!got) { 397 printf("%s: reset not reported\n", sc->sc_dv.dv_xname); 398 return (-1); 399 } 400 401 /* Check controller status. */ 402 status = twe_inl(sc, TWE_REG_STS); 403 if (twe_status_check(sc, status)) { 404 printf("%s: controller errors detected\n", 405 sc->sc_dv.dv_xname); 406 return (-1); 407 } 408 409 /* Drain the response queue. */ 410 for (;;) { 411 status = twe_inl(sc, TWE_REG_STS); 412 if (twe_status_check(sc, status) != 0) { 413 printf("%s: can't drain response queue\n", 414 sc->sc_dv.dv_xname); 415 return (-1); 416 } 417 if ((status & TWE_STS_RESP_QUEUE_EMPTY) != 0) 418 break; 419 junk = twe_inl(sc, TWE_REG_RESP_QUEUE); 420 } 421 422 return (0); 423 } 424 425 /* 426 * Print autoconfiguration message for a sub-device. 427 */ 428 static int 429 twe_print(void *aux, const char *pnp) 430 { 431 struct twe_attach_args *twea; 432 433 twea = aux; 434 435 if (pnp != NULL) 436 printf("block device at %s", pnp); 437 printf(" unit %d", twea->twea_unit); 438 return (UNCONF); 439 } 440 441 /* 442 * Match a sub-device. 443 */ 444 static int 445 twe_submatch(struct device *parent, struct cfdata *cf, void *aux) 446 { 447 struct twe_attach_args *twea; 448 449 twea = aux; 450 451 if (cf->tweacf_unit != TWECF_UNIT_DEFAULT && 452 cf->tweacf_unit != twea->twea_unit) 453 return (0); 454 455 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 456 } 457 458 /* 459 * Interrupt service routine. 460 */ 461 static int 462 twe_intr(void *arg) 463 { 464 struct twe_softc *sc; 465 u_int status; 466 int caught, rv; 467 468 sc = arg; 469 caught = 0; 470 status = twe_inl(sc, TWE_REG_STS); 471 twe_status_check(sc, status); 472 473 /* Host interrupts - purpose unknown. */ 474 if ((status & TWE_STS_HOST_INTR) != 0) { 475 #ifdef DIAGNOSTIC 476 printf("%s: host interrupt\n", sc->sc_dv.dv_xname); 477 #endif 478 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_HOST_INTR); 479 caught = 1; 480 } 481 482 /* 483 * Attention interrupts, signalled when a controller or child device 484 * state change has occurred. 485 */ 486 if ((status & TWE_STS_ATTN_INTR) != 0) { 487 if ((sc->sc_flags & TWEF_AEN) == 0) { 488 rv = twe_param_get(sc, TWE_PARAM_AEN, 489 TWE_PARAM_AEN_UnitCode, 2, twe_aen_handler, 490 NULL); 491 if (rv != 0) { 492 printf("%s: unable to retrieve AEN (%d)\n", 493 sc->sc_dv.dv_xname, rv); 494 twe_outl(sc, TWE_REG_CTL, 495 TWE_CTL_CLEAR_ATTN_INTR); 496 } else 497 sc->sc_flags |= TWEF_AEN; 498 } 499 caught = 1; 500 } 501 502 /* 503 * Command interrupts, signalled when the controller can accept more 504 * commands. We don't use this; instead, we try to submit commands 505 * when we receive them, and when other commands have completed. 506 * Mask it so we don't get another one. 507 */ 508 if ((status & TWE_STS_CMD_INTR) != 0) { 509 #ifdef DIAGNOSTIC 510 printf("%s: command interrupt\n", sc->sc_dv.dv_xname); 511 #endif 512 twe_outl(sc, TWE_REG_CTL, TWE_CTL_MASK_CMD_INTR); 513 caught = 1; 514 } 515 516 if ((status & TWE_STS_RESP_INTR) != 0) { 517 twe_poll(sc); 518 caught = 1; 519 } 520 521 return (caught); 522 } 523 524 /* 525 * Handle an AEN returned by the controller. 526 */ 527 static void 528 twe_aen_handler(struct twe_ccb *ccb, int error) 529 { 530 struct twe_softc *sc; 531 struct twe_param *tp; 532 const char *str; 533 u_int aen; 534 int i, hu, rv; 535 536 sc = (struct twe_softc *)ccb->ccb_tx.tx_dv; 537 tp = ccb->ccb_tx.tx_context; 538 twe_ccb_unmap(sc, ccb); 539 540 if (error) { 541 printf("%s: error retrieving AEN\n", sc->sc_dv.dv_xname); 542 aen = TWE_AEN_QUEUE_EMPTY; 543 } else 544 aen = le16toh(*(u_int16_t *)tp->tp_data); 545 free(tp, M_DEVBUF); 546 twe_ccb_free(sc, ccb); 547 548 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) { 549 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 550 sc->sc_flags &= ~TWEF_AEN; 551 return; 552 } 553 554 str = "<unknown>"; 555 i = 0; 556 hu = 0; 557 558 while (i < sizeof(twe_aen_names) / sizeof(twe_aen_names[0])) { 559 if (TWE_AEN_CODE(twe_aen_names[i].aen) == TWE_AEN_CODE(aen)) { 560 str = twe_aen_names[i].desc; 561 hu = (TWE_AEN_UNIT(twe_aen_names[i].aen) != 0); 562 break; 563 } 564 i++; 565 } 566 printf("%s: AEN 0x%04x (%s) received", sc->sc_dv.dv_xname, 567 TWE_AEN_CODE(aen), str); 568 if (hu != 0) 569 printf(" for unit %d", TWE_AEN_UNIT(aen)); 570 printf("\n"); 571 572 /* 573 * Chain another retrieval in case interrupts have been 574 * coalesced. 575 */ 576 rv = twe_param_get(sc, TWE_PARAM_AEN, TWE_PARAM_AEN_UnitCode, 2, 577 twe_aen_handler, NULL); 578 if (rv != 0) 579 printf("%s: unable to retrieve AEN (%d)\n", 580 sc->sc_dv.dv_xname, rv); 581 } 582 583 /* 584 * Execute a TWE_OP_GET_PARAM command. If a callback function is provided, 585 * it will be called with generated context when the command has completed. 586 * If no callback is provided, the command will be executed synchronously 587 * and a pointer to a buffer containing the data returned. 588 * 589 * The caller or callback is responsible for freeing the buffer. 590 */ 591 static int 592 twe_param_get(struct twe_softc *sc, int table_id, int param_id, size_t size, 593 void (*func)(struct twe_ccb *, int), void **pbuf) 594 { 595 struct twe_ccb *ccb; 596 struct twe_cmd *tc; 597 struct twe_param *tp; 598 int rv, s; 599 600 rv = twe_ccb_alloc(sc, &ccb, 601 TWE_CCB_PARAM | TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 602 if (rv != 0) 603 return (rv); 604 605 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 606 if (pbuf != NULL) 607 *pbuf = tp; 608 609 ccb->ccb_data = tp; 610 ccb->ccb_datasize = TWE_SECTOR_SIZE; 611 ccb->ccb_tx.tx_handler = func; 612 ccb->ccb_tx.tx_context = tp; 613 ccb->ccb_tx.tx_dv = &sc->sc_dv; 614 615 tc = ccb->ccb_cmd; 616 tc->tc_size = 2; 617 tc->tc_opcode = TWE_OP_GET_PARAM | (tc->tc_size << 5); 618 tc->tc_unit = 0; 619 tc->tc_count = htole16(1); 620 621 /* Fill in the outbound parameter data. */ 622 tp->tp_table_id = htole16(table_id); 623 tp->tp_param_id = param_id; 624 tp->tp_param_size = size; 625 626 /* Map the transfer. */ 627 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 628 twe_ccb_free(sc, ccb); 629 free(tp, M_DEVBUF); 630 return (rv); 631 } 632 633 /* Submit the command and either wait or let the callback handle it. */ 634 if (func == NULL) { 635 s = splbio(); 636 rv = twe_ccb_poll(sc, ccb, 5); 637 twe_ccb_unmap(sc, ccb); 638 twe_ccb_free(sc, ccb); 639 splx(s); 640 if (rv != 0) 641 free(tp, M_DEVBUF); 642 } else { 643 twe_ccb_enqueue(sc, ccb); 644 rv = 0; 645 } 646 647 return (rv); 648 } 649 650 /* 651 * Execute a TWE_OP_INIT_CONNECTION command. Return non-zero on error. 652 * Must be called with interrupts blocked. 653 */ 654 static int 655 twe_init_connection(struct twe_softc *sc) 656 { 657 struct twe_ccb *ccb; 658 struct twe_cmd *tc; 659 int rv; 660 661 if ((rv = twe_ccb_alloc(sc, &ccb, 0)) != 0) 662 return (rv); 663 664 /* Build the command. */ 665 tc = ccb->ccb_cmd; 666 tc->tc_size = 3; 667 tc->tc_opcode = TWE_OP_INIT_CONNECTION; 668 tc->tc_unit = 0; 669 tc->tc_count = htole16(TWE_MAX_CMDS); 670 tc->tc_args.init_connection.response_queue_pointer = 0; 671 672 /* Submit the command for immediate execution. */ 673 rv = twe_ccb_poll(sc, ccb, 5); 674 twe_ccb_free(sc, ccb); 675 return (rv); 676 } 677 678 /* 679 * Poll the controller for completed commands. Must be called with 680 * interrupts blocked. 681 */ 682 static void 683 twe_poll(struct twe_softc *sc) 684 { 685 struct twe_ccb *ccb; 686 int found; 687 u_int status, cmdid; 688 689 found = 0; 690 691 for (;;) { 692 status = twe_inl(sc, TWE_REG_STS); 693 twe_status_check(sc, status); 694 695 if ((status & TWE_STS_RESP_QUEUE_EMPTY)) 696 break; 697 698 found = 1; 699 cmdid = twe_inl(sc, TWE_REG_RESP_QUEUE); 700 cmdid = (cmdid & TWE_RESP_MASK) >> TWE_RESP_SHIFT; 701 if (cmdid >= TWE_MAX_QUEUECNT) { 702 printf("%s: bad completion\n", sc->sc_dv.dv_xname); 703 continue; 704 } 705 706 ccb = sc->sc_ccbs + cmdid; 707 if ((ccb->ccb_flags & TWE_CCB_ACTIVE) == 0) { 708 printf("%s: bad completion (not active)\n", 709 sc->sc_dv.dv_xname); 710 continue; 711 } 712 ccb->ccb_flags ^= TWE_CCB_COMPLETE | TWE_CCB_ACTIVE; 713 714 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 715 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, 716 sizeof(struct twe_cmd), 717 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 718 719 /* Pass notification to upper layers. */ 720 if (ccb->ccb_tx.tx_handler != NULL) 721 (*ccb->ccb_tx.tx_handler)(ccb, 722 ccb->ccb_cmd->tc_status != 0 ? EIO : 0); 723 } 724 725 /* If any commands have completed, run the software queue. */ 726 if (found) 727 twe_ccb_enqueue(sc, NULL); 728 } 729 730 /* 731 * Wait for `status' to be set in the controller status register. Return 732 * zero if found, non-zero if the operation timed out. 733 */ 734 static int 735 twe_status_wait(struct twe_softc *sc, u_int32_t status, int timo) 736 { 737 738 for (timo *= 10; timo != 0; timo--) { 739 if ((twe_inl(sc, TWE_REG_STS) & status) == status) 740 break; 741 delay(100000); 742 } 743 744 return (timo == 0); 745 } 746 747 /* 748 * Complain if the status bits aren't what we expect. 749 */ 750 static int 751 twe_status_check(struct twe_softc *sc, u_int status) 752 { 753 int rv; 754 755 rv = 0; 756 757 if ((status & TWE_STS_EXPECTED_BITS) != TWE_STS_EXPECTED_BITS) { 758 printf("%s: missing status bits: 0x%08x\n", sc->sc_dv.dv_xname, 759 status & ~TWE_STS_EXPECTED_BITS); 760 rv = -1; 761 } 762 763 if ((status & TWE_STS_UNEXPECTED_BITS) != 0) { 764 printf("%s: unexpected status bits: 0x%08x\n", 765 sc->sc_dv.dv_xname, status & TWE_STS_UNEXPECTED_BITS); 766 rv = -1; 767 } 768 769 return (rv); 770 } 771 772 /* 773 * Allocate and initialise a CCB. 774 */ 775 int 776 twe_ccb_alloc(struct twe_softc *sc, struct twe_ccb **ccbp, int flags) 777 { 778 struct twe_cmd *tc; 779 struct twe_ccb *ccb; 780 int s; 781 782 s = splbio(); 783 if ((flags & TWE_CCB_PARAM) != 0) 784 ccb = sc->sc_ccbs; 785 else { 786 /* Allocate a CCB and command block. */ 787 if (SLIST_FIRST(&sc->sc_ccb_freelist) == NULL) { 788 splx(s); 789 return (EAGAIN); 790 } 791 ccb = SLIST_FIRST(&sc->sc_ccb_freelist); 792 SLIST_REMOVE_HEAD(&sc->sc_ccb_freelist, ccb_chain.slist); 793 } 794 #ifdef DIAGNOSTIC 795 if ((ccb->ccb_flags & TWE_CCB_ALLOCED) != 0) 796 panic("twe_ccb_alloc: CCB already allocated"); 797 flags |= TWE_CCB_ALLOCED; 798 #endif 799 splx(s); 800 801 /* Initialise some fields and return. */ 802 ccb->ccb_tx.tx_handler = NULL; 803 ccb->ccb_flags = flags; 804 tc = ccb->ccb_cmd; 805 tc->tc_status = 0; 806 tc->tc_flags = 0; 807 tc->tc_cmdid = ccb->ccb_cmdid; 808 *ccbp = ccb; 809 810 return (0); 811 } 812 813 /* 814 * Free a CCB. 815 */ 816 void 817 twe_ccb_free(struct twe_softc *sc, struct twe_ccb *ccb) 818 { 819 int s; 820 821 s = splbio(); 822 if ((ccb->ccb_flags & TWE_CCB_PARAM) == 0) 823 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, ccb_chain.slist); 824 ccb->ccb_flags = 0; 825 splx(s); 826 } 827 828 /* 829 * Map the specified CCB's command block and data buffer (if any) into 830 * controller visible space. Perform DMA synchronisation. 831 */ 832 int 833 twe_ccb_map(struct twe_softc *sc, struct twe_ccb *ccb) 834 { 835 struct twe_cmd *tc; 836 int flags, nsegs, i, s, rv; 837 void *data; 838 839 /* 840 * The data as a whole must be 512-byte aligned. 841 */ 842 if (((u_long)ccb->ccb_data & (TWE_ALIGNMENT - 1)) != 0) { 843 s = splvm(); 844 /* XXX */ 845 ccb->ccb_abuf = uvm_km_kmemalloc(kmem_map, NULL, 846 ccb->ccb_datasize, UVM_KMF_NOWAIT); 847 splx(s); 848 data = (void *)ccb->ccb_abuf; 849 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 850 memcpy(data, ccb->ccb_data, ccb->ccb_datasize); 851 } else { 852 ccb->ccb_abuf = (vaddr_t)0; 853 data = ccb->ccb_data; 854 } 855 856 /* 857 * Map the data buffer into bus space and build the S/G list. 858 */ 859 rv = bus_dmamap_load(sc->sc_dmat, ccb->ccb_dmamap_xfer, data, 860 ccb->ccb_datasize, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 861 ((ccb->ccb_flags & TWE_CCB_DATA_IN) ? 862 BUS_DMA_READ : BUS_DMA_WRITE)); 863 if (rv != 0) { 864 if (ccb->ccb_abuf != (vaddr_t)0) { 865 s = splvm(); 866 /* XXX */ 867 uvm_km_free(kmem_map, ccb->ccb_abuf, 868 ccb->ccb_datasize); 869 splx(s); 870 } 871 return (rv); 872 } 873 874 nsegs = ccb->ccb_dmamap_xfer->dm_nsegs; 875 tc = ccb->ccb_cmd; 876 tc->tc_size += 2 * nsegs; 877 878 /* The location of the S/G list is dependant upon command type. */ 879 switch (tc->tc_opcode >> 5) { 880 case 2: 881 for (i = 0; i < nsegs; i++) { 882 tc->tc_args.param.sgl[i].tsg_address = 883 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 884 tc->tc_args.param.sgl[i].tsg_length = 885 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 886 } 887 /* XXX Needed? */ 888 for (; i < TWE_SG_SIZE; i++) { 889 tc->tc_args.param.sgl[i].tsg_address = 0; 890 tc->tc_args.param.sgl[i].tsg_length = 0; 891 } 892 break; 893 case 3: 894 for (i = 0; i < nsegs; i++) { 895 tc->tc_args.io.sgl[i].tsg_address = 896 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 897 tc->tc_args.io.sgl[i].tsg_length = 898 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 899 } 900 /* XXX Needed? */ 901 for (; i < TWE_SG_SIZE; i++) { 902 tc->tc_args.io.sgl[i].tsg_address = 0; 903 tc->tc_args.io.sgl[i].tsg_length = 0; 904 } 905 break; 906 #ifdef DEBUG 907 default: 908 panic("twe_ccb_map: oops"); 909 #endif 910 } 911 912 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 913 flags = BUS_DMASYNC_PREREAD; 914 else 915 flags = 0; 916 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 917 flags |= BUS_DMASYNC_PREWRITE; 918 919 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 920 ccb->ccb_datasize, flags); 921 return (0); 922 } 923 924 /* 925 * Unmap the specified CCB's command block and data buffer (if any) and 926 * perform DMA synchronisation. 927 */ 928 void 929 twe_ccb_unmap(struct twe_softc *sc, struct twe_ccb *ccb) 930 { 931 int flags, s; 932 933 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 934 flags = BUS_DMASYNC_POSTREAD; 935 else 936 flags = 0; 937 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 938 flags |= BUS_DMASYNC_POSTWRITE; 939 940 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 941 ccb->ccb_datasize, flags); 942 bus_dmamap_unload(sc->sc_dmat, ccb->ccb_dmamap_xfer); 943 944 if (ccb->ccb_abuf != (vaddr_t)0) { 945 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 946 memcpy(ccb->ccb_data, (void *)ccb->ccb_abuf, 947 ccb->ccb_datasize); 948 s = splvm(); 949 /* XXX */ 950 uvm_km_free(kmem_map, ccb->ccb_abuf, ccb->ccb_datasize); 951 splx(s); 952 } 953 } 954 955 /* 956 * Submit a command to the controller and poll on completion. Return 957 * non-zero on timeout (but don't check status, as some command types don't 958 * return status). Must be called with interrupts blocked. 959 */ 960 int 961 twe_ccb_poll(struct twe_softc *sc, struct twe_ccb *ccb, int timo) 962 { 963 int rv; 964 965 if ((rv = twe_ccb_submit(sc, ccb)) != 0) 966 return (rv); 967 968 for (timo *= 1000; timo != 0; timo--) { 969 twe_poll(sc); 970 if ((ccb->ccb_flags & TWE_CCB_COMPLETE) != 0) 971 break; 972 DELAY(100); 973 } 974 975 return (timo == 0); 976 } 977 978 /* 979 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 980 * the order that they were enqueued and try to submit their command blocks 981 * to the controller for execution. 982 */ 983 void 984 twe_ccb_enqueue(struct twe_softc *sc, struct twe_ccb *ccb) 985 { 986 int s; 987 988 s = splbio(); 989 990 if (ccb != NULL) 991 SIMPLEQ_INSERT_TAIL(&sc->sc_ccb_queue, ccb, ccb_chain.simpleq); 992 993 while ((ccb = SIMPLEQ_FIRST(&sc->sc_ccb_queue)) != NULL) { 994 if (twe_ccb_submit(sc, ccb)) 995 break; 996 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_queue, ccb, ccb_chain.simpleq); 997 } 998 999 splx(s); 1000 } 1001 1002 /* 1003 * Submit the command block associated with the specified CCB to the 1004 * controller for execution. Must be called with interrupts blocked. 1005 */ 1006 int 1007 twe_ccb_submit(struct twe_softc *sc, struct twe_ccb *ccb) 1008 { 1009 bus_addr_t pa; 1010 int rv; 1011 u_int status; 1012 1013 /* Check to see if we can post a command. */ 1014 status = twe_inl(sc, TWE_REG_STS); 1015 twe_status_check(sc, status); 1016 1017 if ((status & TWE_STS_CMD_QUEUE_FULL) == 0) { 1018 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1019 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, sizeof(struct twe_cmd), 1020 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1021 ccb->ccb_flags |= TWE_CCB_ACTIVE; 1022 pa = sc->sc_cmds_paddr + 1023 ccb->ccb_cmdid * sizeof(struct twe_cmd); 1024 twe_outl(sc, TWE_REG_CMD_QUEUE, (u_int32_t)pa); 1025 rv = 0; 1026 } else 1027 rv = EBUSY; 1028 1029 return (rv); 1030 } 1031