1 /* $NetBSD: ydsreg.h,v 1.2 2002/11/04 14:56:10 kent Exp $ */ 2 3 /* 4 * Copyright (c) 2000, 2001 Kazuki Sakamoto and Minoura Makoto. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * YMF724/740/744/754 registers 30 */ 31 32 #ifndef _DEV_PCI_YDSREG_H_ 33 #define _DEV_PCI_YDSREG_H_ 34 35 /* 36 * PCI Config Registers 37 */ 38 #define YDS_PCI_MBA 0x10 39 #define YDS_PCI_LEGACY 0x40 40 # define YDS_PCI_LEGACY_SBEN 0x0001 41 # define YDS_PCI_LEGACY_FMEN 0x0002 42 # define YDS_PCI_LEGACY_JPEN 0x0004 43 # define YDS_PCI_LEGACY_MEN 0x0008 44 # define YDS_PCI_LEGACY_MIEN 0x0010 45 # define YDS_PCI_LEGACY_IO 0x0020 46 # define YDS_PCI_LEGACY_SDMA0 0x0000 47 # define YDS_PCI_LEGACY_SDMA1 0x0040 48 # define YDS_PCI_LEGACY_SDMA3 0x00c0 49 # define YDS_PCI_LEGACY_SBIRQ5 0x0000 50 # define YDS_PCI_LEGACY_SBIRQ7 0x0100 51 # define YDS_PCI_LEGACY_SBIRQ9 0x0200 52 # define YDS_PCI_LEGACY_SBIRQ10 0x0300 53 # define YDS_PCI_LEGACY_SBIRQ11 0x0400 54 # define YDS_PCI_LEGACY_MPUIRQ5 0x0000 55 # define YDS_PCI_LEGACY_MPUIRQ7 0x0800 56 # define YDS_PCI_LEGACY_MPUIRQ9 0x1000 57 # define YDS_PCI_LEGACY_MPUIRQ10 0x1800 58 # define YDS_PCI_LEGACY_MPUIRQ11 0x2000 59 # define YDS_PCI_LEGACY_SIEN 0x4000 60 # define YDS_PCI_LEGACY_LAD 0x8000 61 62 # define YDS_PCI_EX_LEGACY_FMIO_388 (0x0000 << 16) 63 # define YDS_PCI_EX_LEGACY_FMIO_398 (0x0001 << 16) 64 # define YDS_PCI_EX_LEGACY_FMIO_3A0 (0x0002 << 16) 65 # define YDS_PCI_EX_LEGACY_FMIO_3A8 (0x0003 << 16) 66 # define YDS_PCI_EX_LEGACY_SBIO_220 (0x0000 << 16) 67 # define YDS_PCI_EX_LEGACY_SBIO_240 (0x0004 << 16) 68 # define YDS_PCI_EX_LEGACY_SBIO_260 (0x0008 << 16) 69 # define YDS_PCI_EX_LEGACY_SBIO_280 (0x000c << 16) 70 # define YDS_PCI_EX_LEGACY_MPUIO_330 (0x0000 << 16) 71 # define YDS_PCI_EX_LEGACY_MPUIO_300 (0x0010 << 16) 72 # define YDS_PCI_EX_LEGACY_MPUIO_332 (0x0020 << 16) 73 # define YDS_PCI_EX_LEGACY_MPUIO_334 (0x0030 << 16) 74 # define YDS_PCI_EX_LEGACY_JSIO_201 (0x0000 << 16) 75 # define YDS_PCI_EX_LEGACY_JSIO_202 (0x0040 << 16) 76 # define YDS_PCI_EX_LEGACY_JSIO_204 (0x0080 << 16) 77 # define YDS_PCI_EX_LEGACY_JSIO_205 (0x00c0 << 16) 78 # define YDS_PCI_EX_LEGACY_MAIM (0x0100 << 16) 79 # define YDS_PCI_EX_LEGACY_SBMOD_PCI (0x0000 << 16) 80 # define YDS_PCI_EX_LEGACY_SBMOD_DDMA (0x1000 << 16) 81 # define YDS_PCI_EX_LEGACY_SBVER_3 (0x0000 << 16) 82 # define YDS_PCI_EX_LEGACY_SBVER_2 (0x2000 << 16) 83 # define YDS_PCI_EX_LEGACY_SBVER_1 (0x4000 << 16) 84 # define YDS_PCI_EX_LEGACY_IMOD (0x8000 << 16) 85 86 #define YDS_PCI_DSCTRL 0x48 87 # define YDS_DSCTRL_CRST 0x0001 88 # define YDS_DSCTRL_WRST 0x0004 89 # define YDS_DSCTRL_ACLS 0x0008 90 #define YDS_PCI_DSPOWER1 0x4a 91 # define YDS_DSPOWER1_DMC 0x0001 92 # define YDS_DSPOWER1_DPLL 0x0002 93 # define YDS_DSPOWER1_JSR 0x0040 94 #define YDS_PCI_DISTDMA 0x4c 95 #define YDS_PCI_DSPOWER2 0x4e 96 # define YDS_DSPOWER2_CMCD 0x0001 97 # define YDS_DSPOWER2_PSFM 0x0002 98 # define YDS_DSPOWER2_PSSB 0x0004 99 # define YDS_DSPOWER2_PSMPU 0x0008 100 # define YDS_DSPOWER2_PSJOY 0x0010 101 # define YDS_DSPOWER2_PSPCA 0x0020 102 # define YDS_DSPOWER2_PSSRC 0x0040 103 # define YDS_DSPOWER2_PSZV 0x0080 104 # define YDS_DSPOWER2_PSDIT 0x0100 105 # define YDS_DSPOWER2_PSDIR 0x0200 106 # define YDS_DSPOWER2_PSACL 0x0400 107 # define YDS_DSPOWER2_PSIO 0x0800 108 # define YDS_DSPOWER2_PSHWV 0x1000 109 110 #define YDS_PCI_FM_BA 0x60 111 #define YDS_PCI_SB_BA 0x62 112 #define YDS_PCI_MPU_BA 0x64 113 #define YDS_PCI_JS_BA 0x66 114 115 /* 116 * DS-1 PCI Audio part registers 117 */ 118 #define YDS_INTERRUPT_FLAGS 0x0004 119 #define YDS_INTERRUPT_FLAGS_TI 0x0001 120 #define YDS_ACTIVITY 0x0006 121 # define YDS_ACTIVITY_DOCKA 0x0010 122 #define YDS_GLOBAL_CONTROL 0x0008 123 # define YDS_GLCTRL_HVE 0x0001 124 # define YDS_GLCTRL_HVIE 0x0002 125 126 #define YDS_GPIO_IIF 0x0050 127 # define YDS_GPIO_GIO0 0x0001 128 # define YDS_GPIO_GIO1 0x0002 129 # define YDS_GPIO_GIO2 0x0004 130 #define YDS_GPIO_IIE 0x0052 131 # define YDS_GPIO_GIE0 0x0001 132 # define YDS_GPIO_GIE1 0x0002 133 # define YDS_GPIO_GIE2 0x0004 134 #define YDS_GPIO_ISTAT 0x0054 135 # define YDS_GPIO_GPI0 0x0001 136 # define YDS_GPIO_GPI1 0x0002 137 # define YDS_GPIO_GPI2 0x0004 138 #define YDS_GPIO_OCTRL 0x0056 139 # define YDS_GPIO_GPO0 0x0001 140 # define YDS_GPIO_GPO1 0x0002 141 # define YDS_GPIO_GPO2 0x0004 142 #define YDS_GPIO_FUNCE 0x0058 143 # define YDS_GPIO_GPC0 0x0001 144 # define YDS_GPIO_GPC1 0x0002 145 # define YDS_GPIO_GPC2 0x0004 146 # define YDS_GPIO_GPE0 0x0010 147 # define YDS_GPIO_GPE1 0x0020 148 # define YDS_GPIO_GPE2 0x0040 149 #define YDS_GPIO_ITYPE 0x005a 150 # define YDS_GPIO_GPT0_LEVEL 0x0000 151 # define YDS_GPIO_GPT0_RISE 0x0001 152 # define YDS_GPIO_GPT0_FALL 0x0002 153 # define YDS_GPIO_GPT0_BOTH 0x0003 154 # define YDS_GPIO_GPT0_MASK 0x0003 155 # define YDS_GPIO_GPT1_LEVEL 0x0004 156 # define YDS_GPIO_GPT1_RISE 0x0005 157 # define YDS_GPIO_GPT1_FALL 0x0006 158 # define YDS_GPIO_GPT1_BOTH 0x0007 159 # define YDS_GPIO_GPT1_MASK 0x0007 160 # define YDS_GPIO_GPT2_LEVEL 0x0000 161 # define YDS_GPIO_GPT2_RISE 0x0010 162 # define YDS_GPIO_GPT2_FALL 0x0020 163 # define YDS_GPIO_GPT2_BOTH 0x0030 164 # define YDS_GPIO_GPT2_MASK 0x0030 165 166 #define YDS_GLOBAL_CONTROL 0x0008 167 # define YDS_GLCTRL_HVE 0x0001 168 # define YDS_GLCTRL_HVIE 0x0002 169 170 #define AC97_CMD_DATA 0x0060 171 #define AC97_CMD_ADDR 0x0062 172 # define AC97_ID(id) ((id) << 8) 173 # define AC97_CMD_READ 0x8000 174 # define AC97_CMD_WRITE 0x0000 175 #define AC97_STAT_DATA1 0x0064 176 #define AC97_STAT_ADDR1 0x0066 177 #define AC97_STAT_DATA2 0x0068 178 #define AC97_STAT_ADDR2 0x006a 179 # define AC97_BUSY 0x8000 180 #define AC97_SECONDARY_CONF 0x0070 181 # define AC97_SECONDARY_RSOC 0x0001 182 # define AC97_SECONDARY_PHWV 0x0002 183 # define AC97_SECONDARY_SHWV 0x0004 184 # define AC97_SECONDARY_4CHEN 0x0010 185 # define AC97_SECONDARY_4CHSEL 0x0020 186 187 #define YDS_LEGACY_OUT_VOLUME 0x0080 188 #define YDS_DAC_OUT_VOLUME 0x0084 189 #define YDS_DAC_OUT_VOL_L 0x0084 190 #define YDS_DAC_OUT_VOL_R 0x0086 191 #define YDS_ZV_OUT_VOLUME 0x0088 192 #define YDS_2ND_OUT_VOLUME 0x008C 193 #define YDS_ADC_OUT_VOLUME 0x0090 194 #define YDS_LEGACY_REC_VOLUME 0x0094 195 #define YDS_DAC_REC_VOLUME 0x0098 196 #define YDS_ZV_REC_VOLUME 0x009C 197 #define YDS_2ND_REC_VOLUME 0x00A0 198 #define YDS_ADC_REC_VOLUME 0x00A4 199 #define YDS_ADC_IN_VOLUME 0x00A8 200 #define YDS_REC_IN_VOLUME 0x00AC 201 #define YDS_P44_OUT_VOLUME 0x00B0 202 #define YDS_P44_REC_VOLUME 0x00B4 203 #define YDS_SPDIFIN_OUT_VOLUME 0x00B8 204 #define YDS_SPDIFIN_REC_VOLUME 0x00BC 205 206 #define YDS_ADC_SAMPLE_RATE 0x00c0 207 #define YDS_REC_SAMPLE_RATE 0x00c4 208 #define YDS_ADC_FORMAT 0x00c8 209 #define YDS_REC_FORMAT 0x00cc 210 # define YDS_FORMAT_8BIT 0x01 211 # define YDS_FORMAT_STEREO 0x02 212 213 #define YDS_STATUS 0x0100 214 # define YDS_STAT_ACT 0x00000001 215 # define YDS_STAT_WORK 0x00000002 216 # define YDS_STAT_TINT 0x00008000 217 # define YDS_STAT_INT 0x80000000 218 #define YDS_CONTROL_SELECT 0x0104 219 # define YDS_CSEL 0x00000001 220 #define YDS_MODE 0x0108 221 # define YDS_MODE_ACTV 0x00000001 222 # define YDS_MODE_ACTV2 0x00000002 223 # define YDS_MODE_TOUT 0x00008000 224 # define YDS_MODE_RESET 0x00010000 225 # define YDS_MODE_AC3 0x40000000 226 # define YDS_MODE_MUTE 0x80000000 227 228 #define YDS_CONFIG 0x0114 229 # define YDS_DSP_DISABLE 0 230 # define YDS_DSP_SETUP 0x00000001 231 232 #define YDS_PLAY_CTRLSIZE 0x0140 233 #define YDS_REC_CTRLSIZE 0x0144 234 #define YDS_EFFECT_CTRLSIZE 0x0148 235 #define YDS_WORK_SIZE 0x014c 236 #define YDS_MAPOF_REC 0x0150 237 # define YDS_RECSLOT_VALID 0x00000001 238 # define YDS_ADCSLOT_VALID 0x00000002 239 #define YDS_MAPOF_EFFECT 0x0154 240 # define YDS_DL_VALID 0x00000001 241 # define YDS_DR_VALID 0x00000002 242 # define YDS_EFFECT1_VALID 0x00000004 243 # define YDS_EFFECT2_VALID 0x00000008 244 # define YDS_EFFECT3_VALID 0x00000010 245 246 #define YDS_PLAY_CTRLBASE 0x0158 247 #define YDS_REC_CTRLBASE 0x015c 248 #define YDS_EFFECT_CTRLBASE 0x0160 249 #define YDS_WORK_BASE 0x0164 250 251 #define YDS_DSP_INSTRAM 0x1000 252 #define YDS_CTRL_INSTRAM 0x4000 253 254 typedef enum { 255 YDS_DS_1, 256 YDS_DS_1E 257 } yds_dstype_t; 258 259 #define AC97_TIMEOUT 1000 260 #define YDS_WORK_TIMEOUT 250000 261 262 /* slot control data structures */ 263 #define MAX_PLAY_SLOT_CTRL 64 264 #define N_PLAY_SLOT_CTRL_BANK 2 265 #define N_REC_SLOT_CTRL 2 266 #define N_REC_SLOT_CTRL_BANK 2 267 268 /* 269 * play slot 270 */ 271 union play_slot_table { 272 u_int32_t numofplay; 273 u_int32_t slotbase; 274 }; 275 276 struct play_slot_ctrl_bank { 277 u_int32_t format; 278 #define PSLT_FORMAT_STEREO 0x00010000 279 #define PSLT_FORMAT_8BIT 0x80000000 280 #define PSLT_FORMAT_SRC441 0x10000000 281 #define PSLT_FORMAT_RCH 0x00000001 282 u_int32_t loopdefault; 283 u_int32_t pgbase; 284 u_int32_t pgloop; 285 u_int32_t pgloopend; 286 u_int32_t pgloopfrac; 287 u_int32_t pgdeltaend; 288 u_int32_t lpfkend; 289 u_int32_t eggainend; 290 u_int32_t lchgainend; 291 u_int32_t rchgainend; 292 u_int32_t effect1gainend; 293 u_int32_t effect2gainend; 294 u_int32_t effect3gainend; 295 u_int32_t lpfq; 296 u_int32_t status; 297 #define PSLT_STATUS_DEND 0x00000001 298 u_int32_t numofframes; 299 u_int32_t loopcount; 300 u_int32_t pgstart; 301 u_int32_t pgstartfrac; 302 u_int32_t pgdelta; 303 u_int32_t lpfk; 304 u_int32_t eggain; 305 u_int32_t lchgain; 306 u_int32_t rchgain; 307 u_int32_t effect1gain; 308 u_int32_t effect2gain; 309 u_int32_t effect3gain; 310 u_int32_t lpfd1; 311 u_int32_t lpfd2; 312 }; 313 314 /* 315 * rec slot 316 */ 317 struct rec_slot_ctrl_bank { 318 u_int32_t pgbase; 319 u_int32_t pgloopendadr; 320 u_int32_t pgstartadr; 321 u_int32_t numofloops; 322 }; 323 324 struct rec_slot { 325 struct rec_slot_ctrl { 326 struct rec_slot_ctrl_bank bank[N_REC_SLOT_CTRL_BANK]; 327 } ctrl[N_REC_SLOT_CTRL]; 328 }; 329 330 /* 331 * effect slot 332 */ 333 struct effect_slot_ctrl_bank { 334 u_int32_t pgbase; 335 u_int32_t pgloopend; 336 u_int32_t pgstart; 337 u_int32_t temp; 338 }; 339 340 #endif /* _DEV_PCI_YDSREG_H_ */ 341