1 /* $NetBSD: if_xi.c,v 1.21 2002/05/05 03:19:26 takemura Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * XXX THIS DRIVER IS BROKEN WRT. MULTICAST LISTS AND PROMISC/ALLMULTI 6 * XXX FLAGS! 7 */ 8 9 /* 10 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by Niklas Hallqvist, 24 * Brandon Creighton and Job de Haas. 25 * 4. The name of the author may not be used to endorse or promote products 26 * derived from this software without specific prior written permission 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 30 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 31 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 33 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 37 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 42 */ 43 44 /* 45 * Known Bugs: 46 * 47 * 1) Promiscuous mode doesn't work on at least the CE2. 48 * 2) Slow. ~450KB/s. Memory access would be better. 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.21 2002/05/05 03:19:26 takemura Exp $"); 53 54 #include "opt_inet.h" 55 #include "bpfilter.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/device.h> 60 #include <sys/ioctl.h> 61 #include <sys/mbuf.h> 62 #include <sys/malloc.h> 63 #include <sys/socket.h> 64 65 #include "rnd.h" 66 #if NRND > 0 67 #include <sys/rnd.h> 68 #endif 69 70 #include <net/if.h> 71 #include <net/if_dl.h> 72 #include <net/if_media.h> 73 #include <net/if_types.h> 74 #include <net/if_ether.h> 75 76 #ifdef INET 77 #include <netinet/in.h> 78 #include <netinet/in_systm.h> 79 #include <netinet/in_var.h> 80 #include <netinet/ip.h> 81 #include <netinet/if_inarp.h> 82 #endif 83 84 #ifdef IPX 85 #include <netipx/ipx.h> 86 #include <netipx/ipx_if.h> 87 #endif 88 89 #ifdef NS 90 #include <netns/ns.h> 91 #include <netns/ns_if.h> 92 #endif 93 94 #if NBPFILTER > 0 95 #include <net/bpf.h> 96 #include <net/bpfdesc.h> 97 #endif 98 99 #define ETHER_MIN_LEN 64 100 #define ETHER_CRC_LEN 4 101 102 /* 103 * Maximum number of bytes to read per interrupt. Linux recommends 104 * somewhere between 2000-22000. 105 * XXX This is currently a hard maximum. 106 */ 107 #define MAX_BYTES_INTR 12000 108 109 #include <dev/mii/mii.h> 110 #include <dev/mii/miivar.h> 111 112 #include <dev/pcmcia/pcmciareg.h> 113 #include <dev/pcmcia/pcmciavar.h> 114 #include <dev/pcmcia/pcmciadevs.h> 115 116 #include <dev/pcmcia/if_xireg.h> 117 118 #ifdef __GNUC__ 119 #define INLINE __inline 120 #else 121 #define INLINE 122 #endif /* __GNUC__ */ 123 124 #ifdef XIDEBUG 125 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 126 127 #define XID_CONFIG 0x1 128 #define XID_MII 0x2 129 #define XID_INTR 0x4 130 #define XID_FIFO 0x8 131 132 #ifdef XIDEBUG_VALUE 133 int xidebug = XIDEBUG_VALUE; 134 #else 135 int xidebug = 0; 136 #endif 137 #else 138 #define DPRINTF(cat, x) (void)0 139 #endif 140 141 int xi_pcmcia_match __P((struct device *, struct cfdata *, void *)); 142 void xi_pcmcia_attach __P((struct device *, struct device *, void *)); 143 int xi_pcmcia_detach __P((struct device *, int)); 144 int xi_pcmcia_activate __P((struct device *, enum devact)); 145 146 /* 147 * In case this chipset ever turns up out of pcmcia attachments (very 148 * unlikely) do the driver splitup. 149 */ 150 struct xi_softc { 151 struct device sc_dev; /* Generic device info */ 152 struct ethercom sc_ethercom; /* Ethernet common part */ 153 154 struct mii_data sc_mii; /* MII media information */ 155 156 bus_space_tag_t sc_bst; /* Bus cookie */ 157 bus_space_handle_t sc_bsh; /* Bus I/O handle */ 158 bus_size_t sc_offset; /* Offset of registers */ 159 160 u_int8_t sc_rev; /* Chip revision */ 161 u_int32_t sc_flags; /* Misc. flags */ 162 int sc_all_mcasts; /* Receive all multicasts */ 163 u_int8_t sc_enaddr[ETHER_ADDR_LEN]; 164 #if NRND > 0 165 rndsource_element_t sc_rnd_source; 166 #endif 167 }; 168 169 struct xi_pcmcia_softc { 170 struct xi_softc sc_xi; /* Generic device info */ 171 172 /* PCMCIA-specific goo */ 173 struct pcmcia_function *sc_pf; /* PCMCIA function */ 174 struct pcmcia_io_handle sc_pcioh; /* iospace info */ 175 int sc_io_window; /* io window info */ 176 void *sc_ih; /* Interrupt handler */ 177 void *sc_powerhook; /* power hook descriptor */ 178 int sc_resource; /* resource allocated */ 179 #define XI_RES_PCIC 1 180 #define XI_RES_IO_ALLOC 2 181 #define XI_RES_IO_MAP 4 182 #define XI_RES_MI 8 183 }; 184 185 struct cfattach xi_pcmcia_ca = { 186 sizeof(struct xi_pcmcia_softc), 187 xi_pcmcia_match, 188 xi_pcmcia_attach, 189 xi_pcmcia_detach, 190 xi_pcmcia_activate 191 }; 192 193 static int xi_pcmcia_cis_quirks __P((struct pcmcia_function *)); 194 static void xi_cycle_power __P((struct xi_softc *)); 195 static int xi_ether_ioctl __P((struct ifnet *, u_long cmd, caddr_t)); 196 static void xi_full_reset __P((struct xi_softc *)); 197 static void xi_init __P((struct xi_softc *)); 198 static int xi_intr __P((void *)); 199 static int xi_ioctl __P((struct ifnet *, u_long, caddr_t)); 200 static int xi_mdi_read __P((struct device *, int, int)); 201 static void xi_mdi_write __P((struct device *, int, int, int)); 202 static int xi_mediachange __P((struct ifnet *)); 203 static void xi_mediastatus __P((struct ifnet *, struct ifmediareq *)); 204 static int xi_pcmcia_funce_enaddr __P((struct device *, u_int8_t *)); 205 static int xi_pcmcia_lan_nid_ciscallback __P((struct pcmcia_tuple *, void *)); 206 static int xi_pcmcia_manfid_ciscallback __P((struct pcmcia_tuple *, void *)); 207 static u_int16_t xi_get __P((struct xi_softc *)); 208 static void xi_reset __P((struct xi_softc *)); 209 static void xi_set_address __P((struct xi_softc *)); 210 static void xi_start __P((struct ifnet *)); 211 static void xi_statchg __P((struct device *)); 212 static void xi_stop __P((struct xi_softc *)); 213 static void xi_watchdog __P((struct ifnet *)); 214 const struct xi_pcmcia_product *xi_pcmcia_identify __P((struct device *, 215 struct pcmcia_attach_args *)); 216 static int xi_pcmcia_enable __P((struct xi_pcmcia_softc *)); 217 static void xi_pcmcia_disable __P((struct xi_pcmcia_softc *)); 218 static void xi_pcmcia_power __P((int, void *)); 219 220 /* flags */ 221 #define XIFLAGS_MOHAWK 0x001 /* 100Mb capabilities (has phy) */ 222 #define XIFLAGS_DINGO 0x002 /* realport cards ??? */ 223 #define XIFLAGS_MODEM 0x004 /* modem also present */ 224 225 const struct xi_pcmcia_product { 226 u_int32_t xpp_vendor; /* vendor ID */ 227 u_int32_t xpp_product; /* product ID */ 228 int xpp_expfunc; /* expected function number */ 229 int xpp_flags; /* initial softc flags */ 230 const char *xpp_name; /* device name */ 231 } xi_pcmcia_products[] = { 232 #ifdef NOT_SUPPORTED 233 { PCMCIA_VENDOR_XIRCOM, 0x0141, 234 0, 0, 235 PCMCIA_STR_XIRCOM_CE }, 236 #endif 237 { PCMCIA_VENDOR_XIRCOM, 0x0141, 238 0, 0, 239 PCMCIA_STR_XIRCOM_CE2 }, 240 { PCMCIA_VENDOR_XIRCOM, 0x0142, 241 0, 0, 242 PCMCIA_STR_XIRCOM_CE2 }, 243 { PCMCIA_VENDOR_XIRCOM, 0x0143, 244 0, XIFLAGS_MOHAWK, 245 PCMCIA_STR_XIRCOM_CE3 }, 246 { PCMCIA_VENDOR_COMPAQ2, 0x0143, 247 0, XIFLAGS_MOHAWK, 248 PCMCIA_STR_COMPAQ2_CPQ_10_100 }, 249 { PCMCIA_VENDOR_INTEL, 0x0143, 250 0, XIFLAGS_MOHAWK | XIFLAGS_MODEM, 251 PCMCIA_STR_INTEL_EEPRO100 }, 252 { PCMCIA_VENDOR_XIRCOM, PCMCIA_PRODUCT_XIRCOM_XE2000, 253 0, XIFLAGS_MOHAWK, 254 PCMCIA_STR_XIRCOM_XE2000 }, 255 { PCMCIA_VENDOR_XIRCOM, PCMCIA_PRODUCT_XIRCOM_REM56, 256 0, XIFLAGS_MOHAWK | XIFLAGS_DINGO | XIFLAGS_MODEM, 257 PCMCIA_STR_XIRCOM_REM56 }, 258 #ifdef NOT_SUPPORTED 259 { PCMCIA_VENDOR_XIRCOM, 0x1141, 260 0, XIFLAGS_MODEM, 261 PCMCIA_STR_XIRCOM_CEM }, 262 #endif 263 { PCMCIA_VENDOR_XIRCOM, 0x1142, 264 0, XIFLAGS_MODEM, 265 PCMCIA_STR_XIRCOM_CEM }, 266 { PCMCIA_VENDOR_XIRCOM, 0x1143, 267 0, XIFLAGS_MODEM, 268 PCMCIA_STR_XIRCOM_CEM }, 269 { PCMCIA_VENDOR_XIRCOM, 0x1144, 270 0, XIFLAGS_MODEM, 271 PCMCIA_STR_XIRCOM_CEM33 }, 272 { PCMCIA_VENDOR_XIRCOM, 0x1145, 273 0, XIFLAGS_MOHAWK | XIFLAGS_MODEM, 274 PCMCIA_STR_XIRCOM_CEM56 }, 275 { PCMCIA_VENDOR_XIRCOM, 0x1146, 276 0, XIFLAGS_MOHAWK | XIFLAGS_DINGO | XIFLAGS_MODEM, 277 PCMCIA_STR_XIRCOM_REM56 }, 278 { PCMCIA_VENDOR_XIRCOM, 0x1147, 279 0, XIFLAGS_MOHAWK | XIFLAGS_DINGO | XIFLAGS_MODEM, 280 PCMCIA_STR_XIRCOM_REM56 }, 281 { 0, 0, 282 0, 0, 283 NULL }, 284 }; 285 286 287 const struct xi_pcmcia_product * 288 xi_pcmcia_identify(dev, pa) 289 struct device *dev; 290 struct pcmcia_attach_args *pa; 291 { 292 const struct xi_pcmcia_product *xpp; 293 u_int8_t id; 294 u_int32_t prod; 295 296 /* 297 * The Xircom ethernet cards swap the revision and product fields 298 * inside the CIS, which makes identification just a little 299 * bit different. 300 */ 301 302 pcmcia_scan_cis(dev, xi_pcmcia_manfid_ciscallback, &id); 303 304 prod = (pa->product & ~0xff) | id; 305 306 DPRINTF(XID_CONFIG, ("product=0x%x\n", prod)); 307 308 for (xpp = xi_pcmcia_products; xpp->xpp_name != NULL; xpp++) 309 if (pa->manufacturer == xpp->xpp_vendor && 310 prod == xpp->xpp_product && 311 pa->pf->number == xpp->xpp_expfunc) 312 return (xpp); 313 return (NULL); 314 } 315 316 /* 317 * The quirks are done here instead of the traditional framework because 318 * of the difficulty in identifying the devices. 319 */ 320 static int 321 xi_pcmcia_cis_quirks(pf) 322 struct pcmcia_function *pf; 323 { 324 struct pcmcia_config_entry *cfe; 325 326 /* Tell the pcmcia framework where the CCR is. */ 327 pf->ccr_base = 0x800; 328 pf->ccr_mask = 0x67; 329 330 /* Fake a cfe. */ 331 SIMPLEQ_FIRST(&pf->cfe_head) = cfe = (struct pcmcia_config_entry *) 332 malloc(sizeof(*cfe), M_DEVBUF, M_NOWAIT|M_ZERO); 333 334 if (cfe == NULL) 335 return -1; 336 337 /* 338 * XXX Use preprocessor symbols instead. 339 * Enable ethernet & its interrupts, wiring them to -INT 340 * No I/O base. 341 */ 342 cfe->number = 0x5; 343 cfe->flags = 0; /* XXX Check! */ 344 cfe->iftype = PCMCIA_IFTYPE_IO; 345 cfe->num_iospace = 0; 346 cfe->num_memspace = 0; 347 cfe->irqmask = 0x8eb0; 348 349 return 0; 350 } 351 352 int 353 xi_pcmcia_match(parent, match, aux) 354 struct device *parent; 355 struct cfdata *match; 356 void *aux; 357 { 358 struct pcmcia_attach_args *pa = aux; 359 360 if (pa->manufacturer == PCMCIA_VENDOR_XIRCOM && 361 pa->product == 0x110a) 362 return (2); /* prevent attach to com_pcmcia */ 363 if (pa->pf->function != PCMCIA_FUNCTION_NETWORK) 364 return (0); 365 366 if (pa->manufacturer == PCMCIA_VENDOR_COMPAQ2 && 367 pa->product == PCMCIA_PRODUCT_COMPAQ2_CPQ_10_100) 368 return (1); 369 370 if (pa->manufacturer == PCMCIA_VENDOR_INTEL && 371 pa->product == PCMCIA_PRODUCT_INTEL_EEPRO100) 372 return (1); 373 374 if (pa->manufacturer == PCMCIA_VENDOR_XIRCOM && 375 ((pa->product >> 8) == XIMEDIA_ETHER || 376 (pa->product >> 8) == (XIMEDIA_ETHER | XIMEDIA_MODEM))) 377 return (1); 378 379 return (0); 380 } 381 382 void 383 xi_pcmcia_attach(parent, self, aux) 384 struct device *parent, *self; 385 void *aux; 386 { 387 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)self; 388 struct xi_softc *sc = &psc->sc_xi; 389 struct pcmcia_attach_args *pa = aux; 390 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 391 const struct xi_pcmcia_product *xpp; 392 393 if (xi_pcmcia_cis_quirks(pa->pf) < 0) { 394 printf(": function enable failed\n"); 395 return; 396 } 397 398 /* Enable the card */ 399 psc->sc_pf = pa->pf; 400 pcmcia_function_init(psc->sc_pf, psc->sc_pf->cfe_head.sqh_first); 401 if (pcmcia_function_enable(psc->sc_pf)) { 402 printf(": function enable failed\n"); 403 goto fail; 404 } 405 psc->sc_resource |= XI_RES_PCIC; 406 407 /* allocate/map ISA I/O space */ 408 if (pcmcia_io_alloc(psc->sc_pf, 0, XI_IOSIZE, XI_IOSIZE, 409 &psc->sc_pcioh) != 0) { 410 printf(": I/O allocation failed\n"); 411 goto fail; 412 } 413 psc->sc_resource |= XI_RES_IO_ALLOC; 414 415 sc->sc_bst = psc->sc_pcioh.iot; 416 sc->sc_bsh = psc->sc_pcioh.ioh; 417 sc->sc_offset = 0; 418 419 if (pcmcia_io_map(psc->sc_pf, PCMCIA_WIDTH_AUTO, 0, XI_IOSIZE, 420 &psc->sc_pcioh, &psc->sc_io_window)) { 421 printf(": can't map I/O space\n"); 422 goto fail; 423 } 424 psc->sc_resource |= XI_RES_IO_MAP; 425 426 xpp = xi_pcmcia_identify(parent,pa); 427 if (xpp == NULL) { 428 printf(": unrecognised model\n"); 429 return; 430 } 431 sc->sc_flags = xpp->xpp_flags; 432 433 printf(": %s\n", xpp->xpp_name); 434 435 /* 436 * Configuration as advised by DINGO documentation. 437 * Dingo has some extra configuration registers in the CCR space. 438 */ 439 if (sc->sc_flags & XIFLAGS_DINGO) { 440 struct pcmcia_mem_handle pcmh; 441 int ccr_window; 442 bus_addr_t ccr_offset; 443 444 /* get access to the DINGO CCR space */ 445 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 446 &pcmh)) { 447 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 448 goto fail; 449 } 450 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 451 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 452 &pcmh, &ccr_offset, &ccr_window)) { 453 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 454 pcmcia_mem_free(psc->sc_pf, &pcmh); 455 goto fail; 456 } 457 458 /* enable the second function - usually modem */ 459 bus_space_write_1(pcmh.memt, pcmh.memh, 460 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 461 bus_space_write_1(pcmh.memt, pcmh.memh, 462 ccr_offset + PCMCIA_CCR_DCOR1, 463 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 464 bus_space_write_1(pcmh.memt, pcmh.memh, 465 ccr_offset + PCMCIA_CCR_DCOR2, 0); 466 bus_space_write_1(pcmh.memt, pcmh.memh, 467 ccr_offset + PCMCIA_CCR_DCOR3, 0); 468 bus_space_write_1(pcmh.memt, pcmh.memh, 469 ccr_offset + PCMCIA_CCR_DCOR4, 0); 470 471 /* We don't need them anymore and can free them (I think). */ 472 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 473 pcmcia_mem_free(psc->sc_pf, &pcmh); 474 } 475 476 /* 477 * Get the ethernet address from FUNCE/LAN_NID tuple. 478 */ 479 xi_pcmcia_funce_enaddr(parent, sc->sc_enaddr); 480 if (!sc->sc_enaddr) { 481 printf("%s: unable to get ethernet address\n", 482 sc->sc_dev.dv_xname); 483 goto fail; 484 } 485 486 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 487 ether_sprintf(sc->sc_enaddr)); 488 489 ifp = &sc->sc_ethercom.ec_if; 490 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 491 ifp->if_softc = sc; 492 ifp->if_start = xi_start; 493 ifp->if_ioctl = xi_ioctl; 494 ifp->if_watchdog = xi_watchdog; 495 ifp->if_flags = 496 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 497 IFQ_SET_READY(&ifp->if_snd); 498 499 /* Reset and initialize the card. */ 500 xi_full_reset(sc); 501 502 /* 503 * Initialize our media structures and probe the MII. 504 */ 505 sc->sc_mii.mii_ifp = ifp; 506 sc->sc_mii.mii_readreg = xi_mdi_read; 507 sc->sc_mii.mii_writereg = xi_mdi_write; 508 sc->sc_mii.mii_statchg = xi_statchg; 509 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 510 xi_mediastatus); 511 DPRINTF(XID_MII | XID_CONFIG, 512 ("xi: bmsr %x\n", xi_mdi_read(&sc->sc_dev, 0, 1))); 513 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 514 MII_OFFSET_ANY, 0); 515 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 516 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 517 NULL); 518 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 519 520 /* 802.1q capability */ 521 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 522 /* Attach the interface. */ 523 if_attach(ifp); 524 ether_ifattach(ifp, sc->sc_enaddr); 525 psc->sc_resource |= XI_RES_MI; 526 527 #if NRND > 0 528 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, 529 RND_TYPE_NET, 0); 530 #endif 531 532 /* 533 * Reset and initialize the card again for DINGO (as found in Linux 534 * driver). Without this Dingo will get a watchdog timeout the first 535 * time. The ugly media tickling seems to be necessary for getting 536 * autonegotiation to work too. 537 */ 538 if (sc->sc_flags & XIFLAGS_DINGO) { 539 xi_full_reset(sc); 540 xi_init(sc); 541 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 542 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE); 543 xi_stop(sc); 544 } 545 546 psc->sc_powerhook = powerhook_establish(xi_pcmcia_power, sc); 547 548 pcmcia_function_disable(psc->sc_pf); 549 psc->sc_resource &= ~XI_RES_PCIC; 550 551 return; 552 553 fail: 554 if ((psc->sc_resource & XI_RES_IO_MAP) != 0) { 555 pcmcia_io_unmap(psc->sc_pf, psc->sc_io_window); 556 psc->sc_resource &= ~XI_RES_IO_MAP; 557 } 558 if ((psc->sc_resource & XI_RES_IO_ALLOC) != 0) { 559 pcmcia_io_free(psc->sc_pf, &psc->sc_pcioh); 560 psc->sc_resource &= ~XI_RES_IO_ALLOC; 561 } 562 if (psc->sc_resource & XI_RES_PCIC) { 563 pcmcia_function_disable(pa->pf); 564 psc->sc_resource &= ~XI_RES_PCIC; 565 } 566 free(SIMPLEQ_FIRST(&psc->sc_pf->cfe_head), M_DEVBUF); 567 } 568 569 int 570 xi_pcmcia_detach(self, flags) 571 struct device *self; 572 int flags; 573 { 574 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)self; 575 struct xi_softc *sc = &psc->sc_xi; 576 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 577 578 DPRINTF(XID_CONFIG, ("xi_pcmcia_detach()\n")); 579 580 if (psc->sc_powerhook != NULL) 581 powerhook_disestablish(psc->sc_powerhook); 582 583 #if NRND > 0 584 rnd_detach_source(&sc->sc_rnd_source); 585 #endif 586 587 if ((psc->sc_resource & XI_RES_MI) != 0) { 588 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 589 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 590 ether_ifdetach(ifp); 591 if_detach(ifp); 592 psc->sc_resource &= ~XI_RES_MI; 593 } 594 if (psc->sc_resource & XI_RES_IO_MAP) { 595 pcmcia_io_unmap(psc->sc_pf, psc->sc_io_window); 596 psc->sc_resource &= ~XI_RES_IO_MAP; 597 } 598 if ((psc->sc_resource & XI_RES_IO_ALLOC) != 0) { 599 pcmcia_io_free(psc->sc_pf, &psc->sc_pcioh); 600 psc->sc_resource &= ~XI_RES_IO_ALLOC; 601 } 602 603 xi_pcmcia_disable(psc); 604 605 free(SIMPLEQ_FIRST(&psc->sc_pf->cfe_head), M_DEVBUF); 606 607 return 0; 608 } 609 610 int 611 xi_pcmcia_activate(self, act) 612 struct device *self; 613 enum devact act; 614 { 615 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)self; 616 struct xi_softc *sc = &psc->sc_xi; 617 int s, rv=0; 618 619 DPRINTF(XID_CONFIG, ("xi_pcmcia_activate()\n")); 620 621 s = splnet(); 622 switch (act) { 623 case DVACT_ACTIVATE: 624 rv = EOPNOTSUPP; 625 break; 626 627 case DVACT_DEACTIVATE: 628 if_deactivate(&sc->sc_ethercom.ec_if); 629 break; 630 } 631 splx(s); 632 return (rv); 633 } 634 635 static int 636 xi_pcmcia_enable(psc) 637 struct xi_pcmcia_softc *psc; 638 { 639 struct xi_softc *sc = &psc->sc_xi; 640 641 DPRINTF(XID_CONFIG,("xi_pcmcia_enable()\n")); 642 643 if (pcmcia_function_enable(psc->sc_pf)) 644 return (1); 645 psc->sc_resource |= XI_RES_PCIC; 646 647 /* establish the interrupt. */ 648 psc->sc_ih = pcmcia_intr_establish(psc->sc_pf, IPL_NET, xi_intr, sc); 649 if (psc->sc_ih == NULL) { 650 printf("%s: couldn't establish interrupt\n", 651 sc->sc_dev.dv_xname); 652 pcmcia_function_disable(psc->sc_pf); 653 psc->sc_resource &= ~XI_RES_PCIC; 654 return (1); 655 } 656 657 xi_full_reset(sc); 658 659 return (0); 660 } 661 662 663 static void 664 xi_pcmcia_disable(psc) 665 struct xi_pcmcia_softc *psc; 666 { 667 DPRINTF(XID_CONFIG,("xi_pcmcia_disable()\n")); 668 669 if (psc->sc_resource & XI_RES_PCIC) { 670 pcmcia_intr_disestablish(psc->sc_pf, psc->sc_ih); 671 pcmcia_function_disable(psc->sc_pf); 672 psc->sc_resource &= ~XI_RES_PCIC; 673 } 674 } 675 676 677 static void 678 xi_pcmcia_power(why, arg) 679 int why; 680 void *arg; 681 { 682 struct xi_pcmcia_softc *psc = arg; 683 struct xi_softc *sc = &psc->sc_xi; 684 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 685 int s; 686 687 DPRINTF(XID_CONFIG,("xi_pcmcia_power()\n")); 688 689 s = splnet(); 690 691 switch (why) { 692 case PWR_SUSPEND: 693 case PWR_STANDBY: 694 if (ifp->if_flags & IFF_RUNNING) { 695 xi_stop(sc); 696 } 697 ifp->if_flags &= ~IFF_RUNNING; 698 ifp->if_timer = 0; 699 break; 700 case PWR_RESUME: 701 if ((ifp->if_flags & IFF_RUNNING) == 0) { 702 xi_init(sc); 703 } 704 ifp->if_flags |= IFF_RUNNING; 705 break; 706 case PWR_SOFTSUSPEND: 707 case PWR_SOFTSTANDBY: 708 case PWR_SOFTRESUME: 709 break; 710 } 711 splx(s); 712 } 713 714 /* 715 * XXX These two functions might be OK to factor out into pcmcia.c since 716 * if_sm_pcmcia.c uses similar ones. 717 */ 718 static int 719 xi_pcmcia_funce_enaddr(parent, myla) 720 struct device *parent; 721 u_int8_t *myla; 722 { 723 /* XXX The Linux driver has more ways to do this in case of failure. */ 724 return (pcmcia_scan_cis(parent, xi_pcmcia_lan_nid_ciscallback, myla)); 725 } 726 727 static int 728 xi_pcmcia_lan_nid_ciscallback(tuple, arg) 729 struct pcmcia_tuple *tuple; 730 void *arg; 731 { 732 u_int8_t *myla = arg; 733 int i; 734 735 DPRINTF(XID_CONFIG, ("xi_pcmcia_lan_nid_ciscallback()\n")); 736 737 if (tuple->code == PCMCIA_CISTPL_FUNCE) { 738 if (tuple->length < 2) 739 return (0); 740 741 switch (pcmcia_tuple_read_1(tuple, 0)) { 742 case PCMCIA_TPLFE_TYPE_LAN_NID: 743 if (pcmcia_tuple_read_1(tuple, 1) != ETHER_ADDR_LEN) 744 return (0); 745 break; 746 747 case 0x02: 748 /* 749 * Not sure about this, I don't have a CE2 750 * that puts the ethernet addr here. 751 */ 752 if (pcmcia_tuple_read_1(tuple, 1) != 13) 753 return (0); 754 break; 755 756 default: 757 return (0); 758 } 759 760 for (i = 0; i < ETHER_ADDR_LEN; i++) 761 myla[i] = pcmcia_tuple_read_1(tuple, i + 2); 762 return (1); 763 } 764 765 /* Yet another spot where this might be. */ 766 if (tuple->code == 0x89) { 767 pcmcia_tuple_read_1(tuple, 1); 768 for (i = 0; i < ETHER_ADDR_LEN; i++) 769 myla[i] = pcmcia_tuple_read_1(tuple, i + 2); 770 return (1); 771 } 772 return (0); 773 } 774 775 int 776 xi_pcmcia_manfid_ciscallback(tuple, arg) 777 struct pcmcia_tuple *tuple; 778 void *arg; 779 { 780 u_int8_t *id = arg; 781 782 DPRINTF(XID_CONFIG, ("xi_pcmcia_manfid_callback()\n")); 783 784 if (tuple->code != PCMCIA_CISTPL_MANFID) 785 return (0); 786 787 if (tuple->length < 2) 788 return (0); 789 790 *id = pcmcia_tuple_read_1(tuple, 4); 791 return (1); 792 } 793 794 static int 795 xi_intr(arg) 796 void *arg; 797 { 798 struct xi_softc *sc = arg; 799 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 800 u_int8_t esr, rsr, isr, rx_status, savedpage; 801 u_int16_t tx_status, recvcount = 0, tempint; 802 803 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 804 805 #if 0 806 if (!(ifp->if_flags & IFF_RUNNING)) 807 return (0); 808 #endif 809 810 ifp->if_timer = 0; /* turn watchdog timer off */ 811 812 if (sc->sc_flags & XIFLAGS_MOHAWK) { 813 /* Disable interrupt (Linux does it). */ 814 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 815 0); 816 } 817 818 savedpage = 819 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + PR); 820 821 PAGE(sc, 0); 822 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ESR); 823 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ISR0); 824 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR); 825 826 /* Check to see if card has been ejected. */ 827 if (isr == 0xff) { 828 #ifdef DIAGNOSTIC 829 printf("%s: interrupt for dead card\n", sc->sc_dev.dv_xname); 830 #endif 831 goto end; 832 } 833 834 PAGE(sc, 40); 835 rx_status = 836 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RXST0); 837 tx_status = 838 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + TXST0); 839 840 /* 841 * XXX Linux writes to RXST0 and TXST* here. My CE2 works just fine 842 * without it, and I can't see an obvious reason for it. 843 */ 844 845 PAGE(sc, 0); 846 while (esr & FULL_PKT_RCV) { 847 if (!(rsr & RSR_RX_OK)) 848 break; 849 850 /* Compare bytes read this interrupt to hard maximum. */ 851 if (recvcount > MAX_BYTES_INTR) { 852 DPRINTF(XID_INTR, 853 ("xi: too many bytes this interrupt\n")); 854 ifp->if_iqdrops++; 855 /* Drop packet. */ 856 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 857 sc->sc_offset + DO0, DO_SKIP_RX_PKT); 858 } 859 tempint = xi_get(sc); /* XXX doesn't check the error! */ 860 recvcount += tempint; 861 ifp->if_ibytes += tempint; 862 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 863 sc->sc_offset + ESR); 864 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 865 sc->sc_offset + RSR); 866 } 867 868 /* Packet too long? */ 869 if (rsr & RSR_TOO_LONG) { 870 ifp->if_ierrors++; 871 DPRINTF(XID_INTR, ("xi: packet too long\n")); 872 } 873 874 /* CRC error? */ 875 if (rsr & RSR_CRCERR) { 876 ifp->if_ierrors++; 877 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 878 } 879 880 /* Alignment error? */ 881 if (rsr & RSR_ALIGNERR) { 882 ifp->if_ierrors++; 883 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 884 } 885 886 /* Check for rx overrun. */ 887 if (rx_status & RX_OVERRUN) { 888 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 889 CLR_RX_OVERRUN); 890 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 891 } 892 893 /* Try to start more packets transmitting. */ 894 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 895 xi_start(ifp); 896 897 /* Detected excessive collisions? */ 898 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 899 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 900 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 901 RESTART_TX); 902 ifp->if_oerrors++; 903 } 904 905 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 906 ifp->if_oerrors++; 907 908 end: 909 /* Reenable interrupts. */ 910 PAGE(sc, savedpage); 911 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 912 ENABLE_INT); 913 914 /* have handled the interrupt */ 915 #if NRND > 0 916 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 917 #endif 918 919 return (1); 920 } 921 922 /* 923 * Pull a packet from the card into an mbuf chain. 924 */ 925 static u_int16_t 926 xi_get(sc) 927 struct xi_softc *sc; 928 { 929 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 930 struct mbuf *top, **mp, *m; 931 u_int16_t pktlen, len, recvcount = 0; 932 u_int8_t *data; 933 u_int8_t rsr; 934 935 DPRINTF(XID_CONFIG, ("xi_get()\n")); 936 937 PAGE(sc, 0); 938 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR); 939 940 pktlen = 941 bus_space_read_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RBC0) & 942 RBC_COUNT_MASK; 943 944 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 945 946 if (pktlen == 0) { 947 /* 948 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 949 * when MPE is set. It is not known why. 950 */ 951 return (0); 952 } 953 954 /* XXX should this be incremented now ? */ 955 recvcount += pktlen; 956 957 MGETHDR(m, M_DONTWAIT, MT_DATA); 958 if (m == 0) 959 return (recvcount); 960 m->m_pkthdr.rcvif = ifp; 961 m->m_pkthdr.len = pktlen; 962 m->m_flags |= M_HASFCS; 963 len = MHLEN; 964 top = 0; 965 mp = ⊤ 966 967 while (pktlen > 0) { 968 if (top) { 969 MGET(m, M_DONTWAIT, MT_DATA); 970 if (m == 0) { 971 m_freem(top); 972 return (recvcount); 973 } 974 len = MLEN; 975 } 976 if (pktlen >= MINCLSIZE) { 977 MCLGET(m, M_DONTWAIT); 978 if (!(m->m_flags & M_EXT)) { 979 m_freem(m); 980 m_freem(top); 981 return (recvcount); 982 } 983 len = MCLBYTES; 984 } 985 if (!top) { 986 caddr_t newdata = (caddr_t)ALIGN(m->m_data + 987 sizeof(struct ether_header)) - 988 sizeof(struct ether_header); 989 len -= newdata - m->m_data; 990 m->m_data = newdata; 991 } 992 len = min(pktlen, len); 993 data = mtod(m, u_int8_t *); 994 if (len > 1) { 995 len &= ~1; 996 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, 997 sc->sc_offset + EDP, (u_int16_t *)data, len>>1); 998 } else 999 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 1000 sc->sc_offset + EDP); 1001 m->m_len = len; 1002 pktlen -= len; 1003 *mp = m; 1004 mp = &m->m_next; 1005 } 1006 1007 /* Skip Rx packet. */ 1008 bus_space_write_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + DO0, 1009 DO_SKIP_RX_PKT); 1010 1011 ifp->if_ipackets++; 1012 1013 #if NBPFILTER > 0 1014 if (ifp->if_bpf) 1015 bpf_mtap(ifp->if_bpf, top); 1016 #endif 1017 1018 (*ifp->if_input)(ifp, top); 1019 return (recvcount); 1020 } 1021 1022 /* 1023 * Serial management for the MII. 1024 * The DELAY's below stem from the fact that the maximum frequency 1025 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 1026 * go much faster than that. 1027 */ 1028 1029 /* Let the MII serial management be idle for one period. */ 1030 static INLINE void xi_mdi_idle __P((struct xi_softc *)); 1031 static INLINE void 1032 xi_mdi_idle(sc) 1033 struct xi_softc *sc; 1034 { 1035 bus_space_tag_t bst = sc->sc_bst; 1036 bus_space_handle_t bsh = sc->sc_bsh; 1037 bus_addr_t offset = sc->sc_offset; 1038 1039 /* Drive MDC low... */ 1040 bus_space_write_1(bst, bsh, offset + GP2, MDC_LOW); 1041 DELAY(1); 1042 1043 /* and high again. */ 1044 bus_space_write_1(bst, bsh, offset + GP2, MDC_HIGH); 1045 DELAY(1); 1046 } 1047 1048 /* Pulse out one bit of data. */ 1049 static INLINE void xi_mdi_pulse __P((struct xi_softc *, int)); 1050 static INLINE void 1051 xi_mdi_pulse(sc, data) 1052 struct xi_softc *sc; 1053 int data; 1054 { 1055 bus_space_tag_t bst = sc->sc_bst; 1056 bus_space_handle_t bsh = sc->sc_bsh; 1057 bus_addr_t offset = sc->sc_offset; 1058 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 1059 1060 /* First latch the data bit MDIO with clock bit MDC low...*/ 1061 bus_space_write_1(bst, bsh, offset + GP2, bit | MDC_LOW); 1062 DELAY(1); 1063 1064 /* then raise the clock again, preserving the data bit. */ 1065 bus_space_write_1(bst, bsh, offset + GP2, bit | MDC_HIGH); 1066 DELAY(1); 1067 } 1068 1069 /* Probe one bit of data. */ 1070 static INLINE int xi_mdi_probe __P((struct xi_softc *sc)); 1071 static INLINE int 1072 xi_mdi_probe(sc) 1073 struct xi_softc *sc; 1074 { 1075 bus_space_tag_t bst = sc->sc_bst; 1076 bus_space_handle_t bsh = sc->sc_bsh; 1077 bus_size_t offset = sc->sc_offset; 1078 u_int8_t x; 1079 1080 /* Pull clock bit MDCK low... */ 1081 bus_space_write_1(bst, bsh, offset + GP2, MDC_LOW); 1082 DELAY(1); 1083 1084 /* Read data and drive clock high again. */ 1085 x = bus_space_read_1(bst, bsh, offset + GP2) & MDIO; 1086 bus_space_write_1(bst, bsh, offset + GP2, MDC_HIGH); 1087 DELAY(1); 1088 1089 return (x); 1090 } 1091 1092 /* Pulse out a sequence of data bits. */ 1093 static INLINE void xi_mdi_pulse_bits __P((struct xi_softc *, u_int32_t, int)); 1094 static INLINE void 1095 xi_mdi_pulse_bits(sc, data, len) 1096 struct xi_softc *sc; 1097 u_int32_t data; 1098 int len; 1099 { 1100 u_int32_t mask; 1101 1102 for (mask = 1 << (len - 1); mask; mask >>= 1) 1103 xi_mdi_pulse(sc, data & mask); 1104 } 1105 1106 /* Read a PHY register. */ 1107 static int 1108 xi_mdi_read(self, phy, reg) 1109 struct device *self; 1110 int phy; 1111 int reg; 1112 { 1113 struct xi_softc *sc = (struct xi_softc *)self; 1114 int i; 1115 u_int32_t mask; 1116 u_int32_t data = 0; 1117 1118 PAGE(sc, 2); 1119 for (i = 0; i < 32; i++) /* Synchronize. */ 1120 xi_mdi_pulse(sc, 1); 1121 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 1122 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 1123 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 1124 xi_mdi_idle(sc); /* Turn around. */ 1125 xi_mdi_probe(sc); /* Drop initial zero bit. */ 1126 1127 for (mask = 1 << 15; mask; mask >>= 1) { 1128 if (xi_mdi_probe(sc)) 1129 data |= mask; 1130 } 1131 xi_mdi_idle(sc); 1132 1133 DPRINTF(XID_MII, 1134 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 1135 1136 return (data); 1137 } 1138 1139 /* Write a PHY register. */ 1140 static void 1141 xi_mdi_write(self, phy, reg, value) 1142 struct device *self; 1143 int phy; 1144 int reg; 1145 int value; 1146 { 1147 struct xi_softc *sc = (struct xi_softc *)self; 1148 int i; 1149 1150 PAGE(sc, 2); 1151 for (i = 0; i < 32; i++) /* Synchronize. */ 1152 xi_mdi_pulse(sc, 1); 1153 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 1154 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 1155 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 1156 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 1157 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */ 1158 xi_mdi_idle(sc); /* Idle away. */ 1159 1160 DPRINTF(XID_MII, 1161 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 1162 } 1163 1164 static void 1165 xi_statchg(self) 1166 struct device *self; 1167 { 1168 /* XXX Update ifp->if_baudrate */ 1169 } 1170 1171 /* 1172 * Change media according to request. 1173 */ 1174 static int 1175 xi_mediachange(ifp) 1176 struct ifnet *ifp; 1177 { 1178 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 1179 1180 if (ifp->if_flags & IFF_UP) 1181 xi_init(ifp->if_softc); 1182 return (0); 1183 } 1184 1185 /* 1186 * Notify the world which media we're using. 1187 */ 1188 static void 1189 xi_mediastatus(ifp, ifmr) 1190 struct ifnet *ifp; 1191 struct ifmediareq *ifmr; 1192 { 1193 struct xi_softc *sc = ifp->if_softc; 1194 1195 DPRINTF(XID_CONFIG, ("xi_mediastatus()\n")); 1196 1197 mii_pollstat(&sc->sc_mii); 1198 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1199 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1200 } 1201 1202 static void 1203 xi_reset(sc) 1204 struct xi_softc *sc; 1205 { 1206 int s; 1207 1208 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 1209 1210 s = splnet(); 1211 xi_stop(sc); 1212 xi_full_reset(sc); 1213 xi_init(sc); 1214 splx(s); 1215 } 1216 1217 static void 1218 xi_watchdog(ifp) 1219 struct ifnet *ifp; 1220 { 1221 struct xi_softc *sc = ifp->if_softc; 1222 1223 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1224 ++ifp->if_oerrors; 1225 1226 xi_reset(sc); 1227 } 1228 1229 static void 1230 xi_stop(sc) 1231 register struct xi_softc *sc; 1232 { 1233 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 1234 1235 /* Disable interrupts. */ 1236 PAGE(sc, 0); 1237 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 0); 1238 1239 PAGE(sc, 1); 1240 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + IMR0, 0); 1241 1242 /* Power down, wait. */ 1243 PAGE(sc, 4); 1244 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + GP1, 0); 1245 DELAY(40000); 1246 1247 /* Cancel watchdog timer. */ 1248 sc->sc_ethercom.ec_if.if_timer = 0; 1249 } 1250 1251 static void 1252 xi_init(sc) 1253 struct xi_softc *sc; 1254 { 1255 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)sc; 1256 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1257 int s; 1258 1259 DPRINTF(XID_CONFIG, ("xi_init()\n")); 1260 1261 if ((psc->sc_resource & XI_RES_PCIC) == 0) 1262 xi_pcmcia_enable(psc); 1263 1264 s = splnet(); 1265 1266 xi_set_address(sc); 1267 1268 /* Set current media. */ 1269 mii_mediachg(&sc->sc_mii); 1270 1271 ifp->if_flags |= IFF_RUNNING; 1272 ifp->if_flags &= ~IFF_OACTIVE; 1273 splx(s); 1274 } 1275 1276 /* 1277 * Start outputting on the interface. 1278 * Always called as splnet(). 1279 */ 1280 static void 1281 xi_start(ifp) 1282 struct ifnet *ifp; 1283 { 1284 struct xi_softc *sc = ifp->if_softc; 1285 bus_space_tag_t bst = sc->sc_bst; 1286 bus_space_handle_t bsh = sc->sc_bsh; 1287 bus_addr_t offset = sc->sc_offset; 1288 unsigned int s, len, pad = 0; 1289 struct mbuf *m0, *m; 1290 u_int16_t space; 1291 1292 DPRINTF(XID_CONFIG, ("xi_start()\n")); 1293 1294 /* Don't transmit if interface is busy or not running. */ 1295 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 1296 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 1297 return; 1298 } 1299 1300 /* Peek at the next packet. */ 1301 IFQ_POLL(&ifp->if_snd, m0); 1302 if (m0 == 0) 1303 return; 1304 1305 /* We need to use m->m_pkthdr.len, so require the header. */ 1306 if (!(m0->m_flags & M_PKTHDR)) 1307 panic("xi_start: no header mbuf"); 1308 1309 len = m0->m_pkthdr.len; 1310 1311 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 1312 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 1313 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 1314 1315 PAGE(sc, 0); 1316 space = bus_space_read_2(bst, bsh, offset + TSO0) & 0x7fff; 1317 if (len + pad + 2 > space) { 1318 DPRINTF(XID_FIFO, 1319 ("xi: not enough space in output FIFO (%d > %d)\n", 1320 len + pad + 2, space)); 1321 return; 1322 } 1323 1324 IFQ_DEQUEUE(&ifp->if_snd, m0); 1325 1326 #if NBPFILTER > 0 1327 if (ifp->if_bpf) 1328 bpf_mtap(ifp->if_bpf, m0); 1329 #endif 1330 1331 /* 1332 * Do the output at splhigh() so that an interrupt from another device 1333 * won't cause a FIFO underrun. 1334 */ 1335 s = splhigh(); 1336 1337 bus_space_write_2(bst, bsh, offset + TSO2, (u_int16_t)len + pad + 2); 1338 bus_space_write_2(bst, bsh, offset + EDP, (u_int16_t)len + pad); 1339 for (m = m0; m; ) { 1340 if (m->m_len > 1) 1341 bus_space_write_multi_2(bst, bsh, offset + EDP, 1342 mtod(m, u_int16_t *), m->m_len>>1); 1343 if (m->m_len & 1) 1344 bus_space_write_1(bst, bsh, offset + EDP, 1345 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1346 MFREE(m, m0); 1347 m = m0; 1348 } 1349 if (sc->sc_flags & XIFLAGS_MOHAWK) 1350 bus_space_write_1(bst, bsh, offset + CR, TX_PKT | ENABLE_INT); 1351 else { 1352 for (; pad > 1; pad -= 2) 1353 bus_space_write_2(bst, bsh, offset + EDP, 0); 1354 if (pad == 1) 1355 bus_space_write_1(bst, bsh, offset + EDP, 0); 1356 } 1357 1358 splx(s); 1359 1360 ifp->if_timer = 5; 1361 ++ifp->if_opackets; 1362 } 1363 1364 static int 1365 xi_ether_ioctl(ifp, cmd, data) 1366 struct ifnet *ifp; 1367 u_long cmd; 1368 caddr_t data; 1369 { 1370 struct ifaddr *ifa = (struct ifaddr *)data; 1371 struct xi_softc *sc = ifp->if_softc; 1372 1373 1374 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 1375 1376 switch (cmd) { 1377 case SIOCSIFADDR: 1378 ifp->if_flags |= IFF_UP; 1379 1380 switch (ifa->ifa_addr->sa_family) { 1381 #ifdef INET 1382 case AF_INET: 1383 xi_init(sc); 1384 arp_ifinit(ifp, ifa); 1385 break; 1386 #endif /* INET */ 1387 1388 #ifdef NS 1389 case AF_NS: 1390 { 1391 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1392 1393 if (ns_nullhost(*ina)) 1394 ina->x_host = *(union ns_host *) 1395 LLADDR(ifp->if_sadl); 1396 else 1397 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 1398 ifp->if_addrlen); 1399 /* Set new address. */ 1400 xi_init(sc); 1401 break; 1402 } 1403 #endif /* NS */ 1404 1405 default: 1406 xi_init(sc); 1407 break; 1408 } 1409 break; 1410 1411 default: 1412 return (EINVAL); 1413 } 1414 1415 return (0); 1416 } 1417 1418 static int 1419 xi_ioctl(ifp, command, data) 1420 struct ifnet *ifp; 1421 u_long command; 1422 caddr_t data; 1423 { 1424 struct xi_pcmcia_softc *psc = ifp->if_softc; 1425 struct xi_softc *sc = &psc->sc_xi; 1426 struct ifreq *ifr = (struct ifreq *)data; 1427 int s, error = 0; 1428 1429 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 1430 1431 s = splnet(); 1432 1433 switch (command) { 1434 case SIOCSIFADDR: 1435 error = xi_ether_ioctl(ifp, command, data); 1436 break; 1437 1438 case SIOCSIFFLAGS: 1439 sc->sc_all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1440 1441 PAGE(sc, 0x42); 1442 if ((ifp->if_flags & IFF_PROMISC) || 1443 (ifp->if_flags & IFF_ALLMULTI)) 1444 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1445 sc->sc_offset + SWC1, 1446 SWC1_PROMISC | SWC1_MCAST_PROM); 1447 else 1448 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1449 sc->sc_offset + SWC1, 0); 1450 1451 /* 1452 * If interface is marked up and not running, then start it. 1453 * If it is marked down and running, stop it. 1454 * XXX If it's up then re-initialize it. This is so flags 1455 * such as IFF_PROMISC are handled. 1456 */ 1457 if (ifp->if_flags & IFF_UP) { 1458 xi_init(sc); 1459 } else { 1460 if (ifp->if_flags & IFF_RUNNING) { 1461 xi_pcmcia_disable(psc); 1462 xi_stop(sc); 1463 ifp->if_flags &= ~IFF_RUNNING; 1464 } 1465 } 1466 break; 1467 1468 case SIOCADDMULTI: 1469 case SIOCDELMULTI: 1470 sc->sc_all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1471 error = (command == SIOCADDMULTI) ? 1472 ether_addmulti(ifr, &sc->sc_ethercom) : 1473 ether_delmulti(ifr, &sc->sc_ethercom); 1474 1475 if (error == ENETRESET) { 1476 /* 1477 * Multicast list has changed; set the hardware 1478 * filter accordingly. 1479 */ 1480 if (!sc->sc_all_mcasts && 1481 !(ifp->if_flags & IFF_PROMISC)) 1482 xi_set_address(sc); 1483 1484 /* 1485 * xi_set_address() can turn on all_mcasts if we run 1486 * out of space, so check it again rather than else {}. 1487 */ 1488 if (sc->sc_all_mcasts) 1489 xi_init(sc); 1490 error = 0; 1491 } 1492 break; 1493 1494 case SIOCSIFMEDIA: 1495 case SIOCGIFMEDIA: 1496 error = 1497 ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1498 break; 1499 1500 default: 1501 error = EINVAL; 1502 } 1503 splx(s); 1504 return (error); 1505 } 1506 1507 static void 1508 xi_set_address(sc) 1509 struct xi_softc *sc; 1510 { 1511 bus_space_tag_t bst = sc->sc_bst; 1512 bus_space_handle_t bsh = sc->sc_bsh; 1513 bus_addr_t offset = sc->sc_offset; 1514 struct ethercom *ether = &sc->sc_ethercom; 1515 #if 0 1516 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1517 #endif 1518 #if WORKING_MULTICAST 1519 struct ether_multistep step; 1520 struct ether_multi *enm; 1521 int page, pos, num; 1522 #endif 1523 int i; 1524 1525 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 1526 1527 PAGE(sc, 0x50); 1528 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1529 bus_space_write_1(bst, bsh, offset + IA + i, 1530 sc->sc_enaddr[(sc->sc_flags & XIFLAGS_MOHAWK) ? 5-i : i]); 1531 } 1532 1533 if (ether->ec_multicnt > 0) { 1534 #ifdef WORKING_MULTICAST 1535 if (ether->ec_multicnt > 9) { 1536 #else 1537 { 1538 #endif 1539 PAGE(sc, 0x42); 1540 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1541 sc->sc_offset + SWC1, 1542 SWC1_PROMISC | SWC1_MCAST_PROM); 1543 return; 1544 } 1545 1546 #ifdef WORKING_MULTICAST 1547 1548 ETHER_FIRST_MULTI(step, ether, enm); 1549 1550 pos = IA + 6; 1551 for (page = 0x50, num = ether->ec_multicnt; num > 0 && enm; 1552 num--) { 1553 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1554 sizeof(enm->enm_addrlo)) != 0) { 1555 /* 1556 * The multicast address is really a range; 1557 * it's easier just to accept all multicasts. 1558 * XXX should we be setting IFF_ALLMULTI here? 1559 */ 1560 #if 0 1561 ifp->if_flags |= IFF_ALLMULTI; 1562 #endif 1563 sc->sc_all_mcasts=1; 1564 break; 1565 } 1566 1567 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1568 printf("%x:", enm->enm_addrlo[i]); 1569 bus_space_write_1(bst, bsh, offset + pos, 1570 enm->enm_addrlo[ 1571 (sc->sc_flags & XIFLAGS_MOHAWK) ? 5-i : i]); 1572 1573 if (++pos > 15) { 1574 pos = IA; 1575 page++; 1576 PAGE(sc, page); 1577 } 1578 } 1579 printf("\n"); 1580 ETHER_NEXT_MULTI(step, enm); 1581 } 1582 #endif 1583 } 1584 } 1585 1586 static void 1587 xi_cycle_power(sc) 1588 struct xi_softc *sc; 1589 { 1590 bus_space_tag_t bst = sc->sc_bst; 1591 bus_space_handle_t bsh = sc->sc_bsh; 1592 bus_addr_t offset = sc->sc_offset; 1593 1594 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1595 1596 PAGE(sc, 4); 1597 DELAY(1); 1598 bus_space_write_1(bst, bsh, offset + GP1, 0); 1599 DELAY(40000); 1600 if (sc->sc_flags & XIFLAGS_MOHAWK) 1601 bus_space_write_1(bst, bsh, offset + GP1, POWER_UP); 1602 else 1603 /* XXX What is bit 2 (aka AIC)? */ 1604 bus_space_write_1(bst, bsh, offset + GP1, POWER_UP | 4); 1605 DELAY(20000); 1606 } 1607 1608 static void 1609 xi_full_reset(sc) 1610 struct xi_softc *sc; 1611 { 1612 bus_space_tag_t bst = sc->sc_bst; 1613 bus_space_handle_t bsh = sc->sc_bsh; 1614 bus_addr_t offset = sc->sc_offset; 1615 1616 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1617 1618 /* Do an as extensive reset as possible on all functions. */ 1619 xi_cycle_power(sc); 1620 bus_space_write_1(bst, bsh, offset + CR, SOFT_RESET); 1621 DELAY(20000); 1622 bus_space_write_1(bst, bsh, offset + CR, 0); 1623 DELAY(20000); 1624 if (sc->sc_flags & XIFLAGS_MOHAWK) { 1625 PAGE(sc, 4); 1626 /* 1627 * Drive GP1 low to power up ML6692 and GP2 high to power up 1628 * the 10Mhz chip. XXX What chip is that? The phy? 1629 */ 1630 bus_space_write_1(bst, bsh, offset + GP0, 1631 GP1_OUT | GP2_OUT | GP2_WR); 1632 } 1633 DELAY(500000); 1634 1635 /* Get revision information. XXX Symbolic constants. */ 1636 sc->sc_rev = bus_space_read_1(bst, bsh, offset + BV) & 1637 ((sc->sc_flags & XIFLAGS_MOHAWK) ? 0x70 : 0x30) >> 4; 1638 1639 /* Media selection. XXX Maybe manual overriding too? */ 1640 if (!(sc->sc_flags & XIFLAGS_MOHAWK)) { 1641 PAGE(sc, 4); 1642 /* 1643 * XXX I have no idea what this really does, it is from the 1644 * Linux driver. 1645 */ 1646 bus_space_write_1(bst, bsh, offset + GP0, GP1_OUT); 1647 } 1648 DELAY(40000); 1649 1650 /* Setup the ethernet interrupt mask. */ 1651 PAGE(sc, 1); 1652 #if 1 1653 bus_space_write_1(bst, bsh, offset + IMR0, 1654 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 1655 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 1656 #else 1657 bus_space_write_1(bst, bsh, offset + IMR0, 0xff); 1658 #endif 1659 if (!(sc->sc_flags & XIFLAGS_DINGO)) { 1660 /* XXX What is this? Not for Dingo at least. */ 1661 /* Unmask TX underrun detection */ 1662 bus_space_write_1(bst, bsh, offset + IMR1, 1); 1663 } 1664 1665 /* 1666 * Disable source insertion. 1667 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1668 */ 1669 if (!(sc->sc_flags & XIFLAGS_DINGO)) { 1670 PAGE(sc, 0x42); 1671 bus_space_write_1(bst, bsh, offset + SWC0, 0x20); 1672 } 1673 1674 /* Set the local memory dividing line. */ 1675 if (sc->sc_rev != 1) { 1676 PAGE(sc, 2); 1677 /* XXX Symbolic constant preferrable. */ 1678 bus_space_write_2(bst, bsh, offset + RBS0, 0x2000); 1679 } 1680 1681 xi_set_address(sc); 1682 1683 /* 1684 * Apparently the receive byte pointer can be bad after a reset, so 1685 * we hardwire it correctly. 1686 */ 1687 PAGE(sc, 0); 1688 bus_space_write_2(bst, bsh, offset + DO0, DO_CHG_OFFSET); 1689 1690 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1691 PAGE(sc, 0x40); 1692 bus_space_write_1(bst, bsh, offset + RX0MSK, 1693 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1694 bus_space_write_1(bst, bsh, offset + TX0MSK, 1695 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1696 SQE | TX_ABORT | TX_OK); 1697 if (!(sc->sc_flags & XIFLAGS_DINGO)) 1698 /* XXX From Linux, dunno what 0xb0 means. */ 1699 bus_space_write_1(bst, bsh, offset + TX1MSK, 0xb0); 1700 bus_space_write_1(bst, bsh, offset + RXST0, 0); 1701 bus_space_write_1(bst, bsh, offset + TXST0, 0); 1702 bus_space_write_1(bst, bsh, offset + TXST1, 0); 1703 1704 /* Enable MII function if available. */ 1705 if (LIST_FIRST(&sc->sc_mii.mii_phys)) { 1706 PAGE(sc, 2); 1707 bus_space_write_1(bst, bsh, offset + MSR, 1708 bus_space_read_1(bst, bsh, offset + MSR) | SELECT_MII); 1709 DELAY(20000); 1710 } else { 1711 PAGE(sc, 0); 1712 1713 /* XXX Do we need to do this? */ 1714 PAGE(sc, 0x42); 1715 bus_space_write_1(bst, bsh, offset + SWC1, SWC1_AUTO_MEDIA); 1716 DELAY(50000); 1717 1718 /* XXX Linux probes the media here. */ 1719 } 1720 1721 /* Configure the LED registers. */ 1722 PAGE(sc, 2); 1723 1724 /* XXX This is not good for 10base2. */ 1725 bus_space_write_1(bst, bsh, offset + LED, 1726 LED_TX_ACT << LED1_SHIFT | LED_10MB_LINK << LED0_SHIFT); 1727 if (sc->sc_flags & XIFLAGS_DINGO) 1728 bus_space_write_1(bst, bsh, offset + LED3, 1729 LED_100MB_LINK << LED3_SHIFT); 1730 1731 /* Enable receiver and go online. */ 1732 PAGE(sc, 0x40); 1733 bus_space_write_1(bst, bsh, offset + CMD0, ENABLE_RX | ONLINE); 1734 1735 #if 0 1736 /* XXX Linux does this here - is it necessary? */ 1737 PAGE(sc, 1); 1738 bus_space_write_1(bst, bsh, offset + IMR0, 0xff); 1739 if (!(sc->sc_flags & XIFLAGS_DINGO)) { 1740 /* XXX What is this? Not for Dingo at least. */ 1741 bus_space_write_1(bst, bsh, offset + IMR1, 1); 1742 } 1743 #endif 1744 1745 /* Enable interrupts. */ 1746 PAGE(sc, 0); 1747 bus_space_write_1(bst, bsh, offset + CR, ENABLE_INT); 1748 1749 /* XXX This is pure magic for me, found in the Linux driver. */ 1750 if ((sc->sc_flags & (XIFLAGS_DINGO | XIFLAGS_MODEM)) == XIFLAGS_MODEM) { 1751 if ((bus_space_read_1(bst, bsh, offset + 0x10) & 0x01) == 0) 1752 /* Unmask the master interrupt bit. */ 1753 bus_space_write_1(bst, bsh, offset + 0x10, 0x11); 1754 } 1755 1756 /* 1757 * The Linux driver says this: 1758 * We should switch back to page 0 to avoid a bug in revision 0 1759 * where regs with offset below 8 can't be read after an access 1760 * to the MAC registers. 1761 */ 1762 PAGE(sc, 0); 1763 } 1764