1 /* $NetBSD: hcsc.c,v 1.9 2002/03/24 14:56:01 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Ben Harris 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Mark Brinicombe of Causality Limited. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Copyright (c) 1996, 1997 Matthias Pfaller. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Matthias Pfaller. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * HCCS 8-bit SCSI driver using the generic NCR5380 driver 71 * 72 * Andy Armstrong gives some details of the HCCS SCSI cards at 73 * <URL:http://www.armlinux.org/~webmail/linux-arm/1997-08/msg00042.html>. 74 */ 75 76 #include <sys/cdefs.h> 77 __KERNEL_RCSID(0, "$NetBSD: hcsc.c,v 1.9 2002/03/24 14:56:01 bjh21 Exp $"); 78 79 #include <sys/param.h> 80 81 #include <sys/systm.h> 82 #include <sys/kernel.h> 83 #include <sys/device.h> 84 #include <sys/buf.h> 85 #include <dev/scsipi/scsi_all.h> 86 #include <dev/scsipi/scsipi_all.h> 87 #include <dev/scsipi/scsiconf.h> 88 89 #include <dev/ic/ncr5380reg.h> 90 #include <dev/ic/ncr5380var.h> 91 92 #include <machine/bootconfig.h> 93 94 #include <dev/podulebus/podulebus.h> 95 #include <dev/podulebus/podules.h> 96 #include <dev/podulebus/powerromreg.h> 97 98 #include <dev/podulebus/hcscreg.h> 99 100 void hcsc_attach (struct device *, struct device *, void *); 101 int hcsc_match (struct device *, struct cfdata *, void *); 102 103 static int hcsc_pdma_in(struct ncr5380_softc *, int, int, u_char *); 104 static int hcsc_pdma_out(struct ncr5380_softc *, int, int, u_char *); 105 106 107 /* 108 * HCCS 8-bit SCSI softc structure. 109 * 110 * Contains the generic ncr5380 device node, podule information and 111 * global information required by the driver. 112 */ 113 114 struct hcsc_softc { 115 struct ncr5380_softc sc_ncr5380; 116 bus_space_tag_t sc_pdmat; 117 bus_space_handle_t sc_pdmah; 118 void *sc_ih; 119 struct evcnt sc_intrcnt; 120 }; 121 122 struct cfattach hcsc_ca = { 123 sizeof(struct hcsc_softc), hcsc_match, hcsc_attach 124 }; 125 126 /* 127 * Card probe function 128 * 129 * Just match the manufacturer and podule ID's 130 */ 131 132 int 133 hcsc_match(struct device *parent, struct cfdata *cf, void *aux) 134 { 135 struct podulebus_attach_args *pa = aux; 136 137 /* Normal ROM */ 138 if (pa->pa_product == PODULE_HCCS_IDESCSI && 139 strncmp(pa->pa_descr, "SCSI", 4) == 0) 140 return 1; 141 /* PowerROM */ 142 if (pa->pa_product == PODULE_ALSYSTEMS_SCSI && 143 podulebus_initloader(pa) == 0 && 144 podloader_callloader(pa, 0, 0) == PRID_HCCS_SCSI1) 145 return 1; 146 return 0; 147 } 148 149 /* 150 * Card attach function 151 * 152 */ 153 154 void 155 hcsc_attach(struct device *parent, struct device *self, void *aux) 156 { 157 struct hcsc_softc *sc = (struct hcsc_softc *)self; 158 struct podulebus_attach_args *pa = aux; 159 #ifndef NCR5380_USE_BUS_SPACE 160 u_char *iobase; 161 #endif 162 char hi_option[sizeof(sc->sc_ncr5380.sc_dev.dv_xname) + 8]; 163 164 sc->sc_ncr5380.sc_min_dma_len = 0; 165 sc->sc_ncr5380.sc_no_disconnect = 0; 166 sc->sc_ncr5380.sc_parity_disable = 0; 167 168 sc->sc_ncr5380.sc_dma_alloc = NULL; 169 sc->sc_ncr5380.sc_dma_free = NULL; 170 sc->sc_ncr5380.sc_dma_poll = NULL; 171 sc->sc_ncr5380.sc_dma_setup = NULL; 172 sc->sc_ncr5380.sc_dma_start = NULL; 173 sc->sc_ncr5380.sc_dma_eop = NULL; 174 sc->sc_ncr5380.sc_dma_stop = NULL; 175 sc->sc_ncr5380.sc_intr_on = NULL; 176 sc->sc_ncr5380.sc_intr_off = NULL; 177 178 #ifdef NCR5380_USE_BUS_SPACE 179 sc->sc_ncr5380.sc_regt = pa->pa_fast_t; 180 bus_space_map(sc->sc_ncr5380.sc_regt, 181 pa->pa_fast_base + HCSC_DP8490_OFFSET, 8, 0, 182 &sc->sc_ncr5380.sc_regh); 183 sc->sc_ncr5380.sci_r0 = 0; 184 sc->sc_ncr5380.sci_r1 = 1; 185 sc->sc_ncr5380.sci_r2 = 2; 186 sc->sc_ncr5380.sci_r3 = 3; 187 sc->sc_ncr5380.sci_r4 = 4; 188 sc->sc_ncr5380.sci_r5 = 5; 189 sc->sc_ncr5380.sci_r6 = 6; 190 sc->sc_ncr5380.sci_r7 = 7; 191 #else 192 iobase = (u_char *)pa->pa_fast_base + HCSC_DP8490_OFFSET; 193 sc->sc_ncr5380.sci_r0 = iobase + 0; 194 sc->sc_ncr5380.sci_r1 = iobase + 4; 195 sc->sc_ncr5380.sci_r2 = iobase + 8; 196 sc->sc_ncr5380.sci_r3 = iobase + 12; 197 sc->sc_ncr5380.sci_r4 = iobase + 16; 198 sc->sc_ncr5380.sci_r5 = iobase + 20; 199 sc->sc_ncr5380.sci_r6 = iobase + 24; 200 sc->sc_ncr5380.sci_r7 = iobase + 28; 201 #endif 202 sc->sc_pdmat = pa->pa_mod_t; 203 bus_space_map(sc->sc_pdmat, pa->pa_mod_base + HCSC_PDMA_OFFSET, 1, 0, 204 &sc->sc_pdmah); 205 206 sc->sc_ncr5380.sc_rev = NCR_VARIANT_DP8490; 207 208 sc->sc_ncr5380.sc_pio_in = hcsc_pdma_in; 209 sc->sc_ncr5380.sc_pio_out = hcsc_pdma_out; 210 211 /* Provide an override for the host id */ 212 sc->sc_ncr5380.sc_channel.chan_id = 7; 213 sprintf(hi_option, "%s.hostid", sc->sc_ncr5380.sc_dev.dv_xname); 214 (void)get_bootconf_option(boot_args, hi_option, 215 BOOTOPT_TYPE_INT, &sc->sc_ncr5380.sc_channel.chan_id); 216 sc->sc_ncr5380.sc_adapter.adapt_minphys = minphys; 217 218 printf(": host ID %d\n", sc->sc_ncr5380.sc_channel.chan_id); 219 220 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 221 self->dv_xname, "intr"); 222 sc->sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO, ncr5380_intr, 223 sc, &sc->sc_intrcnt); 224 225 ncr5380_attach(&sc->sc_ncr5380); 226 } 227 228 #ifndef HCSC_TSIZE_OUT 229 #define HCSC_TSIZE_OUT 512 230 #endif 231 232 #ifndef HCSC_TSIZE_IN 233 #define HCSC_TSIZE_IN 512 234 #endif 235 236 #define TIMEOUT 1000000 237 238 static __inline int 239 hcsc_ready(struct ncr5380_softc *sc) 240 { 241 int i; 242 243 for (i = TIMEOUT; i > 0; i--) { 244 if ((NCR5380_READ(sc,sci_csr) & 245 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) == 246 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) 247 return(1); 248 249 if ((NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 || 250 SCI_BUSY(sc) == 0) 251 return(0); 252 } 253 printf("%s: ready timeout\n", sc->sc_dev.dv_xname); 254 return(0); 255 } 256 257 258 259 /* Return zero on success. */ 260 static __inline void hcsc_wait_not_req(struct ncr5380_softc *sc) 261 { 262 int timo; 263 for (timo = TIMEOUT; timo; timo--) { 264 if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ) == 0 || 265 (NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 || 266 SCI_BUSY(sc) == 0) { 267 return; 268 } 269 } 270 printf("%s: pdma not_req timeout\n", sc->sc_dev.dv_xname); 271 } 272 273 static int 274 hcsc_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen, 275 u_char *data) 276 { 277 struct hcsc_softc *sc = (void *)ncr_sc; 278 bus_space_tag_t pdmat = sc->sc_pdmat; 279 bus_space_handle_t pdmah = sc->sc_pdmah; 280 int s, resid, len; 281 282 s = splbio(); 283 284 NCR5380_WRITE(ncr_sc, sci_mode, 285 NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA); 286 NCR5380_WRITE(ncr_sc, sci_irecv, 0); 287 288 resid = datalen; 289 while (resid > 0) { 290 len = min(resid, HCSC_TSIZE_IN); 291 if (hcsc_ready(ncr_sc) == 0) 292 goto interrupt; 293 bus_space_read_multi_1(pdmat, pdmah, 0, data, len); 294 data += len; 295 resid -= len; 296 } 297 298 hcsc_wait_not_req(ncr_sc); 299 300 interrupt: 301 SCI_CLR_INTR(ncr_sc); 302 NCR5380_WRITE(ncr_sc, sci_mode, 303 NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA); 304 splx(s); 305 return datalen - resid; 306 } 307 308 static int 309 hcsc_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen, 310 u_char *data) 311 { 312 struct hcsc_softc *sc = (void *)ncr_sc; 313 bus_space_tag_t pdmat = sc->sc_pdmat; 314 bus_space_handle_t pdmah = sc->sc_pdmah; 315 int i, s, icmd, resid; 316 317 s = splbio(); 318 icmd = NCR5380_READ(ncr_sc, sci_icmd) & SCI_ICMD_RMASK; 319 NCR5380_WRITE(ncr_sc, sci_icmd, icmd | SCI_ICMD_DATA); 320 NCR5380_WRITE(ncr_sc, sci_mode, 321 NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA); 322 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 323 324 resid = datalen; 325 if (hcsc_ready(ncr_sc) == 0) 326 goto interrupt; 327 328 if (resid > HCSC_TSIZE_OUT) { 329 /* 330 * Because of the chips DMA prefetch, phase changes 331 * etc, won't be detected until we have written at 332 * least one byte more. We pre-write 4 bytes so 333 * subsequent transfers will be aligned to a 4 byte 334 * boundary. Assuming disconects will only occur on 335 * block boundaries, we then correct for the pre-write 336 * when and if we get a phase change. If the chip had 337 * DMA byte counting hardware, the assumption would not 338 * be necessary. 339 */ 340 bus_space_write_multi_1(pdmat, pdmah, 0, data, 4); 341 data += 4; 342 resid -= 4; 343 344 for (; resid >= HCSC_TSIZE_OUT; resid -= HCSC_TSIZE_OUT) { 345 if (hcsc_ready(ncr_sc) == 0) { 346 resid += 4; /* Overshot */ 347 goto interrupt; 348 } 349 bus_space_write_multi_1(pdmat, pdmah, 0, data, 350 HCSC_TSIZE_OUT); 351 data += HCSC_TSIZE_OUT; 352 } 353 if (hcsc_ready(ncr_sc) == 0) { 354 resid += 4; /* Overshot */ 355 goto interrupt; 356 } 357 } 358 359 if (resid) { 360 bus_space_write_multi_1(pdmat, pdmah, 0, data, resid); 361 resid = 0; 362 } 363 for (i = TIMEOUT; i > 0; i--) { 364 if ((NCR5380_READ(ncr_sc, sci_csr) 365 & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 366 != SCI_CSR_DREQ) 367 break; 368 } 369 if (i != 0) 370 bus_space_write_1(pdmat, pdmah, 0, 0); 371 else 372 printf("%s: timeout waiting for final SCI_DSR_DREQ.\n", 373 ncr_sc->sc_dev.dv_xname); 374 375 hcsc_wait_not_req(ncr_sc); 376 interrupt: 377 SCI_CLR_INTR(ncr_sc); 378 NCR5380_WRITE(ncr_sc, sci_mode, 379 NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA); 380 NCR5380_WRITE(ncr_sc, sci_icmd, icmd); 381 splx(s); 382 return(datalen - resid); 383 } 384