xref: /netbsd/sys/dev/qbus/dhureg.h (revision 6550d01e)
1 /*	$NetBSD: dhureg.h,v 1.5 2003/04/06 15:45:12 ragge Exp $	*/
2 /*
3  * Copyright (c) 1996  Ken C. Wellsch.  All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 3. All advertising materials mentioning features or use of this software
14  *    must display the following acknowledgement:
15  *	This product includes software developed by the University of
16  *	California, Berkeley and its contributors.
17  * 4. Neither the name of the University nor the names of its contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31  * SUCH DAMAGE.
32  */
33 
34 #ifdef notdef
35 union w_b
36 {
37 	u_short word;
38 	struct {
39 		u_char byte_lo;
40 		u_char byte_hi;
41 	} bytes;
42 };
43 
44 struct DHUregs
45 {
46 	volatile union w_b u_csr;	/* Control/Status Register (R/W) */
47 	volatile u_short dhu_rbuf;	/* Receive Buffer (R only) */
48 #define dhu_txchar	 dhu_rbuf	/* Transmit Character (W only) */
49 	volatile u_short dhu_lpr;	/* Line Parameter Register (R/W) */
50 	volatile u_short dhu_stat;	/* Line Status (R only) */
51 	volatile u_short dhu_lnctrl;	/* Line Control (R/W) */
52 	volatile u_short dhu_tbufad1;	/* Transmit Buffer Address 1 (R/W) */
53 	volatile u_short dhu_tbufad2;	/* Transmit Buffer Address 2 (R/W) */
54 	volatile u_short dhu_tbufcnt;	/* Transmit Buffer Count (R/W) */
55 };
56 
57 #define dhu_csr		u_csr.word
58 #define dhu_csr_lo	u_csr.bytes.byte_lo
59 #define dhu_csr_hi	u_csr.bytes.byte_hi
60 
61 typedef struct DHUregs dhuregs;
62 #endif
63 
64 #define	DHU_UBA_CSR	0
65 #define	DHU_UBA_CSR_HI	1
66 #define	DHU_UBA_RBUF	2
67 #define	DHU_UBA_TXCHAR	2
68 #define	DHU_UBA_RXTIME	DHU_UBA_TXCHAR	/* on a real dhu only */
69 #define	DHU_UBA_LPR	4
70 #define	DHU_UBA_STAT	6
71 #define	DHU_UBA_FIFO	DHU_UBA_STAT	/* on a real dhu only */
72 #define	DHU_UBA_LNCTRL	8
73 #define	DHU_UBA_TBUFAD1	10
74 #define	DHU_UBA_TBUFAD2	12
75 #define	DHU_UBA_TBUFCNT	14
76 
77 /* CSR bits */
78 
79 #define DHU_CSR_TX_ACTION	0100000
80 #define DHU_CSR_TXIE		0040000
81 #define DHU_CSR_DIAG_FAIL	0020000
82 #define DHU_CSR_TX_DMA_ERROR	0010000
83 #define DHU_CSR_TX_LINE_MASK	0007400
84 #define DHU_CSR_RX_DATA_AVAIL	0000200
85 #define DHU_CSR_RXIE		0000100
86 #define DHU_CSR_MASTER_RESET	0000040
87 #define DHU_CSR_UNUSED		0000020
88 #define DHU_CSR_CHANNEL_MASK	0000017
89 
90 /* RBUF bits */
91 
92 #define DHU_RBUF_DATA_VALID	0100000
93 #define DHU_RBUF_OVERRUN_ERR	0040000
94 #define DHU_RBUF_FRAMING_ERR	0020000
95 #define DHU_RBUF_PARITY_ERR	0010000
96 #define DHU_RBUF_RX_LINE_MASK	0007400
97 
98 #define DHU_DIAG_CODE		0070001
99 #define DHU_MODEM_CODE		0070000
100 
101 /* TXCHAR bits */
102 
103 #define DHU_TXCHAR_DATA_VALID	0100000
104 
105 /* LPR bits */
106 
107 #define DHU_LPR_B50		0x0
108 #define DHU_LPR_B75		0x1
109 #define DHU_LPR_B110		0x2
110 #define DHU_LPR_B134		0x3
111 #define DHU_LPR_B150		0x4
112 #define DHU_LPR_B300		0x5
113 #define DHU_LPR_B600		0x6
114 #define DHU_LPR_B1200		0x7
115 #define DHU_LPR_B1800		0x8
116 #define DHU_LPR_B2000		0x9
117 #define DHU_LPR_B2400		0xA
118 #define DHU_LPR_B4800		0xB
119 #define DHU_LPR_B7200		0xC
120 #define DHU_LPR_B9600		0xD
121 #define DHU_LPR_B19200		0xE
122 #define DHU_LPR_B38400		0xF
123 
124 #define DHU_LPR_5_BIT_CHAR	0000000
125 #define DHU_LPR_6_BIT_CHAR	0000010
126 #define DHU_LPR_7_BIT_CHAR	0000020
127 #define DHU_LPR_8_BIT_CHAR	0000030
128 #define DHU_LPR_PARENB		0000040
129 #define DHU_LPR_EPAR		0000100
130 #define DHU_LPR_2_STOP		0000200
131 
132 /* STAT bits */
133 
134 #define DHU_STAT_DSR		0100000
135 #define DHU_STAT_RI		0020000
136 #define DHU_STAT_DCD		0010000
137 #define DHU_STAT_CTS		0004000
138 #define	DHU_STAT_MDL		0001000
139 #define DHU_STAT_DHU		0000400
140 
141 /* LNCTRL bits */
142 
143 #define DHU_LNCTRL_DMA_ABORT	0000001
144 #define DHU_LNCTRL_IAUTO	0000002
145 #define DHU_LNCTRL_RX_ENABLE	0000004
146 #define DHU_LNCTRL_BREAK	0000010
147 #define DHU_LNCTRL_OAUTO	0000020
148 #define DHU_LNCTRL_FORCE_XOFF	0000040
149 #define DHU_LNCTRL_LINK_TYPE	0000400
150 #define DHU_LNCTRL_DTR		0001000
151 #define DHU_LNCTRL_RTS		0010000
152 
153 /* TBUFAD2 bits */
154 
155 #define DHU_TBUFAD2_DMA_START	0000200
156 #define DHU_TBUFAD2_TX_ENABLE	0100000
157