1 /* $NetBSD: dz_uba.c,v 1.14 2002/02/25 14:58:07 ad Exp $ */ 2 /* 3 * Copyright (c) 1998 Ludd, University of Lule}, Sweden. All rights reserved. 4 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed at Ludd, University of 17 * Lule}, Sweden and its contributors. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: dz_uba.c,v 1.14 2002/02/25 14:58:07 ad Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/ioctl.h> 39 #include <sys/tty.h> 40 #include <sys/proc.h> 41 #include <sys/map.h> 42 #include <sys/buf.h> 43 #include <sys/conf.h> 44 #include <sys/file.h> 45 #include <sys/uio.h> 46 #include <sys/kernel.h> 47 #include <sys/syslog.h> 48 #include <sys/device.h> 49 50 #include <machine/bus.h> 51 #include <machine/pte.h> 52 #include <machine/trap.h> 53 #include <machine/scb.h> 54 55 #include <dev/qbus/ubavar.h> 56 57 #include <dev/dec/dzreg.h> 58 #include <dev/dec/dzvar.h> 59 60 #include "ioconf.h" 61 62 static int dz_uba_match __P((struct device *, struct cfdata *, void *)); 63 static void dz_uba_attach __P((struct device *, struct device *, void *)); 64 65 struct cfattach dz_uba_ca = { 66 sizeof(struct dz_softc), dz_uba_match, dz_uba_attach 67 }; 68 69 /* Autoconfig handles: setup the controller to interrupt, */ 70 /* then complete the housecleaning for full operation */ 71 72 static int 73 dz_uba_match(parent, cf, aux) 74 struct device *parent; 75 struct cfdata *cf; 76 void *aux; 77 { 78 struct uba_attach_args *ua = aux; 79 bus_space_tag_t iot = ua->ua_iot; 80 bus_space_handle_t ioh = ua->ua_ioh; 81 int n; 82 83 iot = iot; /* Silly GCC */ 84 /* Reset controller to initialize, enable TX interrupts */ 85 /* to catch floating vector info elsewhere when completed */ 86 87 bus_space_write_2(iot, ioh, DZ_UBA_CSR, DZ_CSR_MSE | DZ_CSR_TXIE); 88 bus_space_write_1(iot, ioh, DZ_UBA_TCR, 1); 89 90 DELAY(100000); /* delay 1/10 second */ 91 92 bus_space_write_2(iot, ioh, DZ_UBA_CSR, DZ_CSR_RESET); 93 94 /* Now wait up to 3 seconds for reset/clear to complete. */ 95 96 for (n = 0; n < 300; n++) { 97 DELAY(10000); 98 if ((bus_space_read_2(iot, ioh, DZ_UBA_CSR)&DZ_CSR_RESET) == 0) 99 break; 100 } 101 102 /* If the RESET did not clear after 3 seconds, */ 103 /* the controller must be broken. */ 104 105 if (n >= 300) 106 return (0); 107 108 /* Register the TX interrupt handler */ 109 110 111 return (1); 112 } 113 114 static void 115 dz_uba_attach(parent, self, aux) 116 struct device *parent, *self; 117 void *aux; 118 { 119 struct dz_softc *sc = (void *)self; 120 struct uba_attach_args *ua = aux; 121 122 sc->sc_iot = ua->ua_iot; 123 sc->sc_ioh = ua->ua_ioh; 124 125 sc->sc_dr.dr_csr = DZ_UBA_CSR; 126 sc->sc_dr.dr_rbuf = DZ_UBA_RBUF; 127 sc->sc_dr.dr_dtr = DZ_UBA_DTR; 128 sc->sc_dr.dr_break = DZ_UBA_BREAK; 129 sc->sc_dr.dr_tbuf = DZ_UBA_TBUF; 130 sc->sc_dr.dr_tcr = DZ_UBA_TCR; 131 sc->sc_dr.dr_dcd = DZ_UBA_DCD; 132 sc->sc_dr.dr_ring = DZ_UBA_RING; 133 134 sc->sc_type = DZ_DZ; 135 136 /* Now register the TX & RX interrupt handlers */ 137 uba_intr_establish(ua->ua_icookie, ua->ua_cvec, 138 dzxint, sc, &sc->sc_tintrcnt); 139 uba_intr_establish(ua->ua_icookie, ua->ua_cvec - 4, 140 dzrint, sc, &sc->sc_rintrcnt); 141 uba_reset_establish(dzreset, self); 142 143 dzattach(sc, ua->ua_evcnt); 144 } 145