1 /* $NetBSD: if_dereg.h,v 1.2 2000/05/28 17:23:44 ragge Exp $ */ 2 3 /* 4 * Copyright (c) 1982, 1986 Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * @(#)if_dereg.h 7.3 (Berkeley) 6/28/90 36 */ 37 38 /* 39 * DEC DEUNA interface 40 */ 41 #ifdef notdef 42 struct dedevice { 43 union { 44 short p0_w; 45 char p0_b[2]; 46 } u_p0; 47 #define pcsr0 u_p0.p0_w 48 #define pclow u_p0.p0_b[0] 49 #define pchigh u_p0.p0_b[1] 50 short pcsr1; 51 short pcsr2; 52 short pcsr3; 53 }; 54 #endif 55 56 #define DE_PCSR0 0 57 #define DE_PCSR1 2 58 #define DE_PCSR2 4 59 #define DE_PCSR3 6 60 61 /* 62 * PCSR 0 bit descriptions 63 */ 64 #define PCSR0_SERI 0x8000 /* Status error interrupt */ 65 #define PCSR0_PCEI 0x4000 /* Port command error interrupt */ 66 #define PCSR0_RXI 0x2000 /* Receive done interrupt */ 67 #define PCSR0_TXI 0x1000 /* Transmit done interrupt */ 68 #define PCSR0_DNI 0x0800 /* Done interrupt */ 69 #define PCSR0_RCBI 0x0400 /* Receive buffer unavail intrpt */ 70 #define PCSR0_FATI 0x0100 /* Fatal error interrupt */ 71 #define PCSR0_INTR 0x0080 /* Interrupt summary */ 72 #define PCSR0_INTE 0x0040 /* Interrupt enable */ 73 #define PCSR0_RSET 0x0020 /* DEUNA reset */ 74 #define PCSR0_CMASK 0x000f /* command mask */ 75 76 #define PCSR0_BITS "\20\20SERI\17PCEI\16RXI\15TXI\14DNI\13RCBI\11FATI\10INTR\7INTE\6RSET" 77 78 /* bits 0-3 are for the PORT_COMMAND */ 79 #define CMD_NOOP 0x0 80 #define CMD_GETPCBB 0x1 /* Get PCB Block */ 81 #define CMD_GETCMD 0x2 /* Execute command in PCB */ 82 #define CMD_STEST 0x3 /* Self test mode */ 83 #define CMD_START 0x4 /* Reset xmit and receive ring ptrs */ 84 #define CMD_BOOT 0x5 /* Boot DEUNA */ 85 #define CMD_PDMD 0x8 /* Polling demand */ 86 #define CMD_TMRO 0x9 /* Sanity timer on */ 87 #define CMD_TMRF 0xa /* Sanity timer off */ 88 #define CMD_RSTT 0xb /* Reset sanity timer */ 89 #define CMD_STOP 0xf /* Suspend operation */ 90 91 /* 92 * PCSR 1 bit descriptions 93 */ 94 #define PCSR1_XPWR 0x8000 /* Transceiver power BAD */ 95 #define PCSR1_ICAB 0x4000 /* Interconnect cabling BAD */ 96 #define PCSR1_STCODE 0x3f00 /* Self test error code */ 97 #define PCSR1_PCTO 0x0080 /* Port command timed out */ 98 #define PCSR1_ILLINT 0x0040 /* Illegal interrupt */ 99 #define PCSR1_TIMEOUT 0x0020 /* Timeout */ 100 #define PCSR1_POWER 0x0010 /* Power fail */ 101 #define PCSR1_RMTC 0x0008 /* Remote console reserved */ 102 #define PCSR1_STMASK 0x0007 /* State */ 103 104 /* bit 0-3 are for STATE */ 105 #define STAT_RESET 0x0 106 #define STAT_PRIMLD 0x1 /* Primary load */ 107 #define STAT_READY 0x2 108 #define STAT_RUN 0x3 109 #define STAT_UHALT 0x5 /* UNIBUS halted */ 110 #define STAT_NIHALT 0x6 /* NI halted */ 111 #define STAT_NIUHALT 0x7 /* NI and UNIBUS Halted */ 112 113 #define PCSR1_BITS "\20\20XPWR\17ICAB\10PCTO\7ILLINT\6TIMEOUT\5POWER\4RMTC" 114 115 /* 116 * Port Control Block Base 117 */ 118 struct de_pcbb { 119 int16_t pcbb0; /* function */ 120 int16_t pcbb2; /* command specific */ 121 int16_t pcbb4; 122 int16_t pcbb6; 123 }; 124 125 /* PCBB function codes */ 126 #define FC_NOOP 0x00 /* NO-OP */ 127 #define FC_LSUADDR 0x01 /* Load and start microaddress */ 128 #define FC_RDDEFAULT 0x02 /* Read default physical address */ 129 #define FC_RDPHYAD 0x04 /* Read physical address */ 130 #define FC_WTPHYAD 0x05 /* Write physical address */ 131 #define FC_RDMULTI 0x06 /* Read multicast address list */ 132 #define FC_WTMULTI 0x07 /* Read multicast address list */ 133 #define FC_RDRING 0x08 /* Read ring format */ 134 #define FC_WTRING 0x09 /* Write ring format */ 135 #define FC_RDCNTS 0x0a /* Read counters */ 136 #define FC_RCCNTS 0x0b /* Read and clear counters */ 137 #define FC_RDMODE 0x0c /* Read mode */ 138 #define FC_WTMODE 0x0d /* Write mode */ 139 #define FC_RDSTATUS 0x0e /* Read port status */ 140 #define FC_RCSTATUS 0x0f /* Read and clear port status */ 141 #define FC_DUMPMEM 0x10 /* Dump internal memory */ 142 #define FC_LOADMEM 0x11 /* Load internal memory */ 143 #define FC_RDSYSID 0x12 /* Read system ID parameters */ 144 #define FC_WTSYSID 0x13 /* Write system ID parameters */ 145 #define FC_RDSERAD 0x14 /* Read load server address */ 146 #define FC_WTSERAD 0x15 /* Write load server address */ 147 148 /* 149 * Unibus Data Block Base (UDBB) for ring buffers 150 */ 151 struct de_udbbuf { 152 int16_t b_tdrbl; /* Transmit desc ring base low 16 bits */ 153 int8_t b_tdrbh; /* Transmit desc ring base high 2 bits */ 154 int8_t b_telen; /* Length of each transmit entry */ 155 int16_t b_trlen; /* Number of entries in the XMIT desc ring */ 156 int16_t b_rdrbl; /* Receive desc ring base low 16 bits */ 157 int8_t b_rdrbh; /* Receive desc ring base high 2 bits */ 158 int8_t b_relen; /* Length of each receive entry */ 159 int16_t b_rrlen; /* Number of entries in the RECV desc ring */ 160 }; 161 162 /* 163 * Transmit/Receive Ring Entry 164 */ 165 struct de_ring { 166 int16_t r_slen; /* Segment length */ 167 int16_t r_segbl; /* Segment address (low 16 bits) */ 168 int8_t r_segbh; /* Segment address (hi 2 bits) */ 169 u_int8_t r_flags; /* Status flags */ 170 u_int16_t r_tdrerr; /* Errors */ 171 #define r_lenerr r_tdrerr 172 }; 173 174 #define XFLG_OWN 0x80 /* If 0 then owned by driver */ 175 #define XFLG_ERRS 0x40 /* Error summary */ 176 #define XFLG_MTCH 0x20 /* Address match on xmit request */ 177 #define XFLG_MORE 0x10 /* More than one entry required */ 178 #define XFLG_ONE 0x08 /* One collision encountered */ 179 #define XFLG_DEF 0x04 /* Transmit deferred */ 180 #define XFLG_STP 0x02 /* Start of packet */ 181 #define XFLG_ENP 0x01 /* End of packet */ 182 183 #define XFLG_BITS "\10\10OWN\7ERRS\6MTCH\5MORE\4ONE\3DEF\2STP\1ENP" 184 185 #define XERR_BUFL 0x8000 /* Buffer length error */ 186 #define XERR_UBTO 0x4000 /* UNIBUS tiemout */ 187 #define XERR_LCOL 0x1000 /* Late collision */ 188 #define XERR_LCAR 0x0800 /* Loss of carrier */ 189 #define XERR_RTRY 0x0400 /* Failed after 16 retries */ 190 #define XERR_TDR 0x03ff /* TDR value */ 191 192 #define XERR_BITS "\20\20BUFL\17UBTO\15LCOL\14LCAR\13RTRY" 193 194 #define RFLG_OWN 0x80 /* If 0 then owned by driver */ 195 #define RFLG_ERRS 0x40 /* Error summary */ 196 #define RFLG_FRAM 0x20 /* Framing error */ 197 #define RFLG_OFLO 0x10 /* Message overflow */ 198 #define RFLG_CRC 0x08 /* CRC error */ 199 #define RFLG_STP 0x02 /* Start of packet */ 200 #define RFLG_ENP 0x01 /* End of packet */ 201 202 #define RFLG_BITS "\10\10OWN\7ERRS\6FRAM\5OFLO\4CRC\2STP\1ENP" 203 204 #define RERR_BUFL 0x8000 /* Buffer length error */ 205 #define RERR_UBTO 0x4000 /* UNIBUS tiemout */ 206 #define RERR_NCHN 0x2000 /* No data chaining */ 207 #define RERR_MLEN 0x0fff /* Message length */ 208 209 #define RERR_BITS "\20\20BUFL\17UBTO\16NCHN" 210 211 /* mode description bits */ 212 #define MOD_HDX 0x0001 /* Half duplex mode */ 213 #define MOD_LOOP 0x0004 /* Enable internal loopback */ 214 #define MOD_DTCR 0x0008 /* Disables CRC generation */ 215 #define MOD_DMNT 0x0200 /* Disable maintenance features */ 216 #define MOD_ECT 0x0400 /* Enable collision test */ 217 #define MOD_TPAD 0x1000 /* Transmit message pad enable */ 218 #define MOD_DRDC 0x2000 /* Disable data chaining */ 219 #define MOD_ENAL 0x4000 /* Enable all multicast */ 220 #define MOD_PROM 0x8000 /* Enable promiscuous mode */ 221