1 /* $NetBSD: if_qe.c,v 1.50 2002/05/22 16:03:17 wiz Exp $ */ 2 /* 3 * Copyright (c) 1999 Ludd, University of Lule}, Sweden. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed at Ludd, University of 16 * Lule}, Sweden and its contributors. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for DEQNA/DELQA ethernet cards. 34 * Things that is still to do: 35 * Handle ubaresets. Does not work at all right now. 36 * Fix ALLMULTI reception. But someone must tell me how... 37 * Collect statistics. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: if_qe.c,v 1.50 2002/05/22 16:03:17 wiz Exp $"); 42 43 #include "opt_inet.h" 44 #include "bpfilter.h" 45 46 #include <sys/param.h> 47 #include <sys/mbuf.h> 48 #include <sys/socket.h> 49 #include <sys/device.h> 50 #include <sys/systm.h> 51 #include <sys/sockio.h> 52 53 #include <net/if.h> 54 #include <net/if_ether.h> 55 #include <net/if_dl.h> 56 57 #include <netinet/in.h> 58 #include <netinet/if_inarp.h> 59 60 #if NBPFILTER > 0 61 #include <net/bpf.h> 62 #include <net/bpfdesc.h> 63 #endif 64 65 #include <machine/bus.h> 66 67 #include <dev/qbus/ubavar.h> 68 #include <dev/qbus/if_qereg.h> 69 70 #include "ioconf.h" 71 72 #define RXDESCS 30 /* # of receive descriptors */ 73 #define TXDESCS 60 /* # transmit descs */ 74 75 /* 76 * Structure containing the elements that must be in DMA-safe memory. 77 */ 78 struct qe_cdata { 79 struct qe_ring qc_recv[RXDESCS+1]; /* Receive descriptors */ 80 struct qe_ring qc_xmit[TXDESCS+1]; /* Transmit descriptors */ 81 u_int8_t qc_setup[128]; /* Setup packet layout */ 82 }; 83 84 struct qe_softc { 85 struct device sc_dev; /* Configuration common part */ 86 struct evcnt sc_intrcnt; /* Interrupt counting */ 87 struct ethercom sc_ec; /* Ethernet common part */ 88 #define sc_if sc_ec.ec_if /* network-visible interface */ 89 bus_space_tag_t sc_iot; 90 bus_addr_t sc_ioh; 91 bus_dma_tag_t sc_dmat; 92 struct qe_cdata *sc_qedata; /* Descriptor struct */ 93 struct qe_cdata *sc_pqedata; /* Unibus address of above */ 94 struct mbuf* sc_txmbuf[TXDESCS]; 95 struct mbuf* sc_rxmbuf[RXDESCS]; 96 bus_dmamap_t sc_xmtmap[TXDESCS]; 97 bus_dmamap_t sc_rcvmap[RXDESCS]; 98 struct ubinfo sc_ui; 99 int sc_intvec; /* Interrupt vector */ 100 int sc_nexttx; 101 int sc_inq; 102 int sc_lastack; 103 int sc_nextrx; 104 int sc_setup; /* Setup packet in queue */ 105 }; 106 107 static int qematch(struct device *, struct cfdata *, void *); 108 static void qeattach(struct device *, struct device *, void *); 109 static void qeinit(struct qe_softc *); 110 static void qestart(struct ifnet *); 111 static void qeintr(void *); 112 static int qeioctl(struct ifnet *, u_long, caddr_t); 113 static int qe_add_rxbuf(struct qe_softc *, int); 114 static void qe_setup(struct qe_softc *); 115 static void qetimeout(struct ifnet *); 116 117 struct cfattach qe_ca = { 118 sizeof(struct qe_softc), qematch, qeattach 119 }; 120 121 #define QE_WCSR(csr, val) \ 122 bus_space_write_2(sc->sc_iot, sc->sc_ioh, csr, val) 123 #define QE_RCSR(csr) \ 124 bus_space_read_2(sc->sc_iot, sc->sc_ioh, csr) 125 126 #define LOWORD(x) ((int)(x) & 0xffff) 127 #define HIWORD(x) (((int)(x) >> 16) & 0x3f) 128 129 /* 130 * Check for present DEQNA. Done by sending a fake setup packet 131 * and wait for interrupt. 132 */ 133 int 134 qematch(struct device *parent, struct cfdata *cf, void *aux) 135 { 136 struct qe_softc ssc; 137 struct qe_softc *sc = &ssc; 138 struct uba_attach_args *ua = aux; 139 struct uba_softc *ubasc = (struct uba_softc *)parent; 140 struct ubinfo ui; 141 142 #define PROBESIZE (sizeof(struct qe_ring) * 4 + 128) 143 struct qe_ring ring[15]; /* For diag purposes only */ 144 struct qe_ring *rp; 145 int error; 146 147 bzero(sc, sizeof(struct qe_softc)); 148 bzero(ring, PROBESIZE); 149 sc->sc_iot = ua->ua_iot; 150 sc->sc_ioh = ua->ua_ioh; 151 sc->sc_dmat = ua->ua_dmat; 152 153 ubasc->uh_lastiv -= 4; 154 QE_WCSR(QE_CSR_CSR, QE_RESET); 155 QE_WCSR(QE_CSR_VECTOR, ubasc->uh_lastiv); 156 157 /* 158 * Map the ring area. Actually this is done only to be able to 159 * send and receive a internal packet; some junk is loopbacked 160 * so that the DEQNA has a reason to interrupt. 161 */ 162 ui.ui_size = PROBESIZE; 163 ui.ui_vaddr = (caddr_t)&ring[0]; 164 if ((error = uballoc((void *)parent, &ui, UBA_CANTWAIT))) 165 return 0; 166 167 /* 168 * Init a simple "fake" receive and transmit descriptor that 169 * points to some unused area. Send a fake setup packet. 170 */ 171 rp = (void *)ui.ui_baddr; 172 ring[0].qe_flag = ring[0].qe_status1 = QE_NOTYET; 173 ring[0].qe_addr_lo = LOWORD(&rp[4]); 174 ring[0].qe_addr_hi = HIWORD(&rp[4]) | QE_VALID | QE_EOMSG | QE_SETUP; 175 ring[0].qe_buf_len = 128; 176 177 ring[2].qe_flag = ring[2].qe_status1 = QE_NOTYET; 178 ring[2].qe_addr_lo = LOWORD(&rp[4]); 179 ring[2].qe_addr_hi = HIWORD(&rp[4]) | QE_VALID; 180 ring[2].qe_buf_len = 128; 181 182 QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET); 183 DELAY(1000); 184 185 /* 186 * Start the interface and wait for the packet. 187 */ 188 QE_WCSR(QE_CSR_CSR, QE_INT_ENABLE|QE_XMIT_INT|QE_RCV_INT); 189 QE_WCSR(QE_CSR_RCLL, LOWORD(&rp[2])); 190 QE_WCSR(QE_CSR_RCLH, HIWORD(&rp[2])); 191 QE_WCSR(QE_CSR_XMTL, LOWORD(rp)); 192 QE_WCSR(QE_CSR_XMTH, HIWORD(rp)); 193 DELAY(10000); 194 195 /* 196 * All done with the bus resources. 197 */ 198 ubfree((void *)parent, &ui); 199 return 1; 200 } 201 202 /* 203 * Interface exists: make available by filling in network interface 204 * record. System will initialize the interface when it is ready 205 * to accept packets. 206 */ 207 void 208 qeattach(struct device *parent, struct device *self, void *aux) 209 { 210 struct uba_attach_args *ua = aux; 211 struct uba_softc *ubasc = (struct uba_softc *)parent; 212 struct qe_softc *sc = (struct qe_softc *)self; 213 struct ifnet *ifp = (struct ifnet *)&sc->sc_if; 214 struct qe_ring *rp; 215 u_int8_t enaddr[ETHER_ADDR_LEN]; 216 int i, error; 217 218 sc->sc_iot = ua->ua_iot; 219 sc->sc_ioh = ua->ua_ioh; 220 sc->sc_dmat = ua->ua_dmat; 221 222 /* 223 * Allocate DMA safe memory for descriptors and setup memory. 224 */ 225 226 sc->sc_ui.ui_size = sizeof(struct qe_cdata); 227 if ((error = ubmemalloc((struct uba_softc *)parent, &sc->sc_ui, 0))) { 228 printf(": unable to ubmemalloc(), error = %d\n", error); 229 return; 230 } 231 sc->sc_pqedata = (struct qe_cdata *)sc->sc_ui.ui_baddr; 232 sc->sc_qedata = (struct qe_cdata *)sc->sc_ui.ui_vaddr; 233 234 /* 235 * Zero the newly allocated memory. 236 */ 237 bzero(sc->sc_qedata, sizeof(struct qe_cdata)); 238 /* 239 * Create the transmit descriptor DMA maps. We take advantage 240 * of the fact that the Qbus address space is big, and therefore 241 * allocate map registers for all transmit descriptors also, 242 * so that we can avoid this each time we send a packet. 243 */ 244 for (i = 0; i < TXDESCS; i++) { 245 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 246 1, MCLBYTES, 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 247 &sc->sc_xmtmap[i]))) { 248 printf(": unable to create tx DMA map %d, error = %d\n", 249 i, error); 250 goto fail_4; 251 } 252 } 253 254 /* 255 * Create receive buffer DMA maps. 256 */ 257 for (i = 0; i < RXDESCS; i++) { 258 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 259 MCLBYTES, 0, BUS_DMA_NOWAIT, 260 &sc->sc_rcvmap[i]))) { 261 printf(": unable to create rx DMA map %d, error = %d\n", 262 i, error); 263 goto fail_5; 264 } 265 } 266 /* 267 * Pre-allocate the receive buffers. 268 */ 269 for (i = 0; i < RXDESCS; i++) { 270 if ((error = qe_add_rxbuf(sc, i)) != 0) { 271 printf(": unable to allocate or map rx buffer %d\n," 272 " error = %d\n", i, error); 273 goto fail_6; 274 } 275 } 276 277 /* 278 * Create ring loops of the buffer chains. 279 * This is only done once. 280 */ 281 282 rp = sc->sc_qedata->qc_recv; 283 rp[RXDESCS].qe_addr_lo = LOWORD(&sc->sc_pqedata->qc_recv[0]); 284 rp[RXDESCS].qe_addr_hi = HIWORD(&sc->sc_pqedata->qc_recv[0]) | 285 QE_VALID | QE_CHAIN; 286 rp[RXDESCS].qe_flag = rp[RXDESCS].qe_status1 = QE_NOTYET; 287 288 rp = sc->sc_qedata->qc_xmit; 289 rp[TXDESCS].qe_addr_lo = LOWORD(&sc->sc_pqedata->qc_xmit[0]); 290 rp[TXDESCS].qe_addr_hi = HIWORD(&sc->sc_pqedata->qc_xmit[0]) | 291 QE_VALID | QE_CHAIN; 292 rp[TXDESCS].qe_flag = rp[TXDESCS].qe_status1 = QE_NOTYET; 293 294 /* 295 * Get the vector that were set at match time, and remember it. 296 */ 297 sc->sc_intvec = ubasc->uh_lastiv; 298 QE_WCSR(QE_CSR_CSR, QE_RESET); 299 DELAY(1000); 300 QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET); 301 302 /* 303 * Read out ethernet address and tell which type this card is. 304 */ 305 for (i = 0; i < 6; i++) 306 enaddr[i] = QE_RCSR(i * 2) & 0xff; 307 308 QE_WCSR(QE_CSR_VECTOR, sc->sc_intvec | 1); 309 printf("\n%s: %s, hardware address %s\n", sc->sc_dev.dv_xname, 310 QE_RCSR(QE_CSR_VECTOR) & 1 ? "delqa":"deqna", 311 ether_sprintf(enaddr)); 312 313 QE_WCSR(QE_CSR_VECTOR, QE_RCSR(QE_CSR_VECTOR) & ~1); /* ??? */ 314 315 uba_intr_establish(ua->ua_icookie, ua->ua_cvec, qeintr, 316 sc, &sc->sc_intrcnt); 317 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 318 sc->sc_dev.dv_xname, "intr"); 319 320 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 321 ifp->if_softc = sc; 322 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 323 ifp->if_start = qestart; 324 ifp->if_ioctl = qeioctl; 325 ifp->if_watchdog = qetimeout; 326 IFQ_SET_READY(&ifp->if_snd); 327 328 /* 329 * Attach the interface. 330 */ 331 if_attach(ifp); 332 ether_ifattach(ifp, enaddr); 333 334 return; 335 336 /* 337 * Free any resources we've allocated during the failed attach 338 * attempt. Do this in reverse order and fall through. 339 */ 340 fail_6: 341 for (i = 0; i < RXDESCS; i++) { 342 if (sc->sc_rxmbuf[i] != NULL) { 343 bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[i]); 344 m_freem(sc->sc_rxmbuf[i]); 345 } 346 } 347 fail_5: 348 for (i = 0; i < RXDESCS; i++) { 349 if (sc->sc_xmtmap[i] != NULL) 350 bus_dmamap_destroy(sc->sc_dmat, sc->sc_xmtmap[i]); 351 } 352 fail_4: 353 for (i = 0; i < TXDESCS; i++) { 354 if (sc->sc_rcvmap[i] != NULL) 355 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rcvmap[i]); 356 } 357 } 358 359 /* 360 * Initialization of interface. 361 */ 362 void 363 qeinit(struct qe_softc *sc) 364 { 365 struct ifnet *ifp = (struct ifnet *)&sc->sc_if; 366 struct qe_cdata *qc = sc->sc_qedata; 367 int i; 368 369 370 /* 371 * Reset the interface. 372 */ 373 QE_WCSR(QE_CSR_CSR, QE_RESET); 374 DELAY(1000); 375 QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET); 376 QE_WCSR(QE_CSR_VECTOR, sc->sc_intvec); 377 378 sc->sc_nexttx = sc->sc_inq = sc->sc_lastack = 0; 379 /* 380 * Release and init transmit descriptors. 381 */ 382 for (i = 0; i < TXDESCS; i++) { 383 if (sc->sc_txmbuf[i]) { 384 bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[i]); 385 m_freem(sc->sc_txmbuf[i]); 386 sc->sc_txmbuf[i] = 0; 387 } 388 qc->qc_xmit[i].qe_addr_hi = 0; /* Clear valid bit */ 389 qc->qc_xmit[i].qe_status1 = qc->qc_xmit[i].qe_flag = QE_NOTYET; 390 } 391 392 393 /* 394 * Init receive descriptors. 395 */ 396 for (i = 0; i < RXDESCS; i++) 397 qc->qc_recv[i].qe_status1 = qc->qc_recv[i].qe_flag = QE_NOTYET; 398 sc->sc_nextrx = 0; 399 400 /* 401 * Write the descriptor addresses to the device. 402 * Receiving packets will be enabled in the interrupt routine. 403 */ 404 QE_WCSR(QE_CSR_CSR, QE_INT_ENABLE|QE_XMIT_INT|QE_RCV_INT); 405 QE_WCSR(QE_CSR_RCLL, LOWORD(sc->sc_pqedata->qc_recv)); 406 QE_WCSR(QE_CSR_RCLH, HIWORD(sc->sc_pqedata->qc_recv)); 407 408 ifp->if_flags |= IFF_RUNNING; 409 ifp->if_flags &= ~IFF_OACTIVE; 410 411 /* 412 * Send a setup frame. 413 * This will start the transmit machinery as well. 414 */ 415 qe_setup(sc); 416 417 } 418 419 /* 420 * Start output on interface. 421 */ 422 void 423 qestart(struct ifnet *ifp) 424 { 425 struct qe_softc *sc = ifp->if_softc; 426 struct qe_cdata *qc = sc->sc_qedata; 427 paddr_t buffer; 428 struct mbuf *m, *m0; 429 int idx, len, s, i, totlen, error; 430 short orword, csr; 431 432 if ((QE_RCSR(QE_CSR_CSR) & QE_RCV_ENABLE) == 0) 433 return; 434 435 s = splnet(); 436 while (sc->sc_inq < (TXDESCS - 1)) { 437 438 if (sc->sc_setup) { 439 qe_setup(sc); 440 continue; 441 } 442 idx = sc->sc_nexttx; 443 IFQ_POLL(&ifp->if_snd, m); 444 if (m == 0) 445 goto out; 446 /* 447 * Count number of mbufs in chain. 448 * Always do DMA directly from mbufs, therefore the transmit 449 * ring is really big. 450 */ 451 for (m0 = m, i = 0; m0; m0 = m0->m_next) 452 if (m0->m_len) 453 i++; 454 if (i >= TXDESCS) 455 panic("qestart"); 456 457 if ((i + sc->sc_inq) >= (TXDESCS - 1)) { 458 ifp->if_flags |= IFF_OACTIVE; 459 goto out; 460 } 461 462 IFQ_DEQUEUE(&ifp->if_snd, m); 463 464 #if NBPFILTER > 0 465 if (ifp->if_bpf) 466 bpf_mtap(ifp->if_bpf, m); 467 #endif 468 /* 469 * m now points to a mbuf chain that can be loaded. 470 * Loop around and set it. 471 */ 472 totlen = 0; 473 for (m0 = m; m0; m0 = m0->m_next) { 474 error = bus_dmamap_load(sc->sc_dmat, sc->sc_xmtmap[idx], 475 mtod(m0, void *), m0->m_len, 0, 0); 476 buffer = sc->sc_xmtmap[idx]->dm_segs[0].ds_addr; 477 len = m0->m_len; 478 if (len == 0) 479 continue; 480 481 totlen += len; 482 /* Word alignment calc */ 483 orword = 0; 484 if (totlen == m->m_pkthdr.len) { 485 if (totlen < ETHER_MIN_LEN) 486 len += (ETHER_MIN_LEN - totlen); 487 orword |= QE_EOMSG; 488 sc->sc_txmbuf[idx] = m; 489 } 490 if ((buffer & 1) || (len & 1)) 491 len += 2; 492 if (buffer & 1) 493 orword |= QE_ODDBEGIN; 494 if ((buffer + len) & 1) 495 orword |= QE_ODDEND; 496 qc->qc_xmit[idx].qe_buf_len = -(len/2); 497 qc->qc_xmit[idx].qe_addr_lo = LOWORD(buffer); 498 qc->qc_xmit[idx].qe_addr_hi = HIWORD(buffer); 499 qc->qc_xmit[idx].qe_flag = 500 qc->qc_xmit[idx].qe_status1 = QE_NOTYET; 501 qc->qc_xmit[idx].qe_addr_hi |= (QE_VALID | orword); 502 if (++idx == TXDESCS) 503 idx = 0; 504 sc->sc_inq++; 505 } 506 #ifdef DIAGNOSTIC 507 if (totlen != m->m_pkthdr.len) 508 panic("qestart: len fault"); 509 #endif 510 511 /* 512 * Kick off the transmit logic, if it is stopped. 513 */ 514 csr = QE_RCSR(QE_CSR_CSR); 515 if (csr & QE_XL_INVALID) { 516 QE_WCSR(QE_CSR_XMTL, 517 LOWORD(&sc->sc_pqedata->qc_xmit[sc->sc_nexttx])); 518 QE_WCSR(QE_CSR_XMTH, 519 HIWORD(&sc->sc_pqedata->qc_xmit[sc->sc_nexttx])); 520 } 521 sc->sc_nexttx = idx; 522 } 523 if (sc->sc_inq == (TXDESCS - 1)) 524 ifp->if_flags |= IFF_OACTIVE; 525 526 out: if (sc->sc_inq) 527 ifp->if_timer = 5; /* If transmit logic dies */ 528 splx(s); 529 } 530 531 static void 532 qeintr(void *arg) 533 { 534 struct qe_softc *sc = arg; 535 struct qe_cdata *qc = sc->sc_qedata; 536 struct ifnet *ifp = &sc->sc_if; 537 struct mbuf *m; 538 int csr, status1, status2, len; 539 540 csr = QE_RCSR(QE_CSR_CSR); 541 542 QE_WCSR(QE_CSR_CSR, QE_RCV_ENABLE | QE_INT_ENABLE | QE_XMIT_INT | 543 QE_RCV_INT | QE_ILOOP); 544 545 if (csr & QE_RCV_INT) 546 while (qc->qc_recv[sc->sc_nextrx].qe_status1 != QE_NOTYET) { 547 status1 = qc->qc_recv[sc->sc_nextrx].qe_status1; 548 status2 = qc->qc_recv[sc->sc_nextrx].qe_status2; 549 550 m = sc->sc_rxmbuf[sc->sc_nextrx]; 551 len = ((status1 & QE_RBL_HI) | 552 (status2 & QE_RBL_LO)) + 60; 553 qe_add_rxbuf(sc, sc->sc_nextrx); 554 m->m_pkthdr.rcvif = ifp; 555 m->m_pkthdr.len = m->m_len = len; 556 if (++sc->sc_nextrx == RXDESCS) 557 sc->sc_nextrx = 0; 558 #if NBPFILTER > 0 559 if (ifp->if_bpf) 560 bpf_mtap(ifp->if_bpf, m); 561 #endif 562 if ((status1 & QE_ESETUP) == 0) 563 (*ifp->if_input)(ifp, m); 564 else 565 m_freem(m); 566 } 567 568 if (csr & (QE_XMIT_INT|QE_XL_INVALID)) { 569 while (qc->qc_xmit[sc->sc_lastack].qe_status1 != QE_NOTYET) { 570 int idx = sc->sc_lastack; 571 572 sc->sc_inq--; 573 if (++sc->sc_lastack == TXDESCS) 574 sc->sc_lastack = 0; 575 576 /* XXX collect statistics */ 577 qc->qc_xmit[idx].qe_addr_hi &= ~QE_VALID; 578 qc->qc_xmit[idx].qe_status1 = 579 qc->qc_xmit[idx].qe_flag = QE_NOTYET; 580 581 if (qc->qc_xmit[idx].qe_addr_hi & QE_SETUP) 582 continue; 583 bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[idx]); 584 if (sc->sc_txmbuf[idx]) { 585 m_freem(sc->sc_txmbuf[idx]); 586 sc->sc_txmbuf[idx] = 0; 587 } 588 } 589 ifp->if_timer = 0; 590 ifp->if_flags &= ~IFF_OACTIVE; 591 qestart(ifp); /* Put in more in queue */ 592 } 593 /* 594 * How can the receive list get invalid??? 595 * Verified that it happens anyway. 596 */ 597 if ((qc->qc_recv[sc->sc_nextrx].qe_status1 == QE_NOTYET) && 598 (QE_RCSR(QE_CSR_CSR) & QE_RL_INVALID)) { 599 QE_WCSR(QE_CSR_RCLL, 600 LOWORD(&sc->sc_pqedata->qc_recv[sc->sc_nextrx])); 601 QE_WCSR(QE_CSR_RCLH, 602 HIWORD(&sc->sc_pqedata->qc_recv[sc->sc_nextrx])); 603 } 604 } 605 606 /* 607 * Process an ioctl request. 608 */ 609 int 610 qeioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 611 { 612 struct qe_softc *sc = ifp->if_softc; 613 struct ifreq *ifr = (struct ifreq *)data; 614 struct ifaddr *ifa = (struct ifaddr *)data; 615 int s = splnet(), error = 0; 616 617 switch (cmd) { 618 619 case SIOCSIFADDR: 620 ifp->if_flags |= IFF_UP; 621 switch(ifa->ifa_addr->sa_family) { 622 #ifdef INET 623 case AF_INET: 624 qeinit(sc); 625 arp_ifinit(ifp, ifa); 626 break; 627 #endif 628 } 629 break; 630 631 case SIOCSIFFLAGS: 632 if ((ifp->if_flags & IFF_UP) == 0 && 633 (ifp->if_flags & IFF_RUNNING) != 0) { 634 /* 635 * If interface is marked down and it is running, 636 * stop it. (by disabling receive mechanism). 637 */ 638 QE_WCSR(QE_CSR_CSR, 639 QE_RCSR(QE_CSR_CSR) & ~QE_RCV_ENABLE); 640 ifp->if_flags &= ~IFF_RUNNING; 641 } else if ((ifp->if_flags & IFF_UP) != 0 && 642 (ifp->if_flags & IFF_RUNNING) == 0) { 643 /* 644 * If interface it marked up and it is stopped, then 645 * start it. 646 */ 647 qeinit(sc); 648 } else if ((ifp->if_flags & IFF_UP) != 0) { 649 /* 650 * Send a new setup packet to match any new changes. 651 * (Like IFF_PROMISC etc) 652 */ 653 qe_setup(sc); 654 } 655 break; 656 657 case SIOCADDMULTI: 658 case SIOCDELMULTI: 659 /* 660 * Update our multicast list. 661 */ 662 error = (cmd == SIOCADDMULTI) ? 663 ether_addmulti(ifr, &sc->sc_ec): 664 ether_delmulti(ifr, &sc->sc_ec); 665 666 if (error == ENETRESET) { 667 /* 668 * Multicast list has changed; set the hardware filter 669 * accordingly. 670 */ 671 qe_setup(sc); 672 error = 0; 673 } 674 break; 675 676 default: 677 error = EINVAL; 678 679 } 680 splx(s); 681 return (error); 682 } 683 684 /* 685 * Add a receive buffer to the indicated descriptor. 686 */ 687 int 688 qe_add_rxbuf(struct qe_softc *sc, int i) 689 { 690 struct mbuf *m; 691 struct qe_ring *rp; 692 vaddr_t addr; 693 int error; 694 695 MGETHDR(m, M_DONTWAIT, MT_DATA); 696 if (m == NULL) 697 return (ENOBUFS); 698 699 MCLGET(m, M_DONTWAIT); 700 if ((m->m_flags & M_EXT) == 0) { 701 m_freem(m); 702 return (ENOBUFS); 703 } 704 705 if (sc->sc_rxmbuf[i] != NULL) 706 bus_dmamap_unload(sc->sc_dmat, sc->sc_rcvmap[i]); 707 708 error = bus_dmamap_load(sc->sc_dmat, sc->sc_rcvmap[i], 709 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 710 if (error) 711 panic("%s: can't load rx DMA map %d, error = %d\n", 712 sc->sc_dev.dv_xname, i, error); 713 sc->sc_rxmbuf[i] = m; 714 715 bus_dmamap_sync(sc->sc_dmat, sc->sc_rcvmap[i], 0, 716 sc->sc_rcvmap[i]->dm_mapsize, BUS_DMASYNC_PREREAD); 717 718 /* 719 * We know that the mbuf cluster is page aligned. Also, be sure 720 * that the IP header will be longword aligned. 721 */ 722 m->m_data += 2; 723 addr = sc->sc_rcvmap[i]->dm_segs[0].ds_addr + 2; 724 rp = &sc->sc_qedata->qc_recv[i]; 725 rp->qe_flag = rp->qe_status1 = QE_NOTYET; 726 rp->qe_addr_lo = LOWORD(addr); 727 rp->qe_addr_hi = HIWORD(addr) | QE_VALID; 728 rp->qe_buf_len = -(m->m_ext.ext_size - 2)/2; 729 730 return (0); 731 } 732 733 /* 734 * Create a setup packet and put in queue for sending. 735 */ 736 void 737 qe_setup(struct qe_softc *sc) 738 { 739 struct ether_multi *enm; 740 struct ether_multistep step; 741 struct qe_cdata *qc = sc->sc_qedata; 742 struct ifnet *ifp = &sc->sc_if; 743 u_int8_t *enaddr = LLADDR(ifp->if_sadl); 744 int i, j, k, idx, s; 745 746 s = splnet(); 747 if (sc->sc_inq == (TXDESCS - 1)) { 748 sc->sc_setup = 1; 749 splx(s); 750 return; 751 } 752 sc->sc_setup = 0; 753 /* 754 * Init the setup packet with valid info. 755 */ 756 memset(qc->qc_setup, 0xff, sizeof(qc->qc_setup)); /* Broadcast */ 757 for (i = 0; i < ETHER_ADDR_LEN; i++) 758 qc->qc_setup[i * 8 + 1] = enaddr[i]; /* Own address */ 759 760 /* 761 * Multicast handling. The DEQNA can handle up to 12 direct 762 * ethernet addresses. 763 */ 764 j = 3; k = 0; 765 ifp->if_flags &= ~IFF_ALLMULTI; 766 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 767 while (enm != NULL) { 768 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) { 769 ifp->if_flags |= IFF_ALLMULTI; 770 break; 771 } 772 for (i = 0; i < ETHER_ADDR_LEN; i++) 773 qc->qc_setup[i * 8 + j + k] = enm->enm_addrlo[i]; 774 j++; 775 if (j == 8) { 776 j = 1; k += 64; 777 } 778 if (k > 64) { 779 ifp->if_flags |= IFF_ALLMULTI; 780 break; 781 } 782 ETHER_NEXT_MULTI(step, enm); 783 } 784 idx = sc->sc_nexttx; 785 qc->qc_xmit[idx].qe_buf_len = -64; 786 787 /* 788 * How is the DEQNA turned in ALLMULTI mode??? 789 * Until someone tells me, fall back to PROMISC when more than 790 * 12 ethernet addresses. 791 */ 792 if (ifp->if_flags & IFF_ALLMULTI) 793 ifp->if_flags |= IFF_PROMISC; 794 else if (ifp->if_pcount == 0) 795 ifp->if_flags &= ~IFF_PROMISC; 796 if (ifp->if_flags & IFF_PROMISC) 797 qc->qc_xmit[idx].qe_buf_len = -65; 798 799 qc->qc_xmit[idx].qe_addr_lo = LOWORD(sc->sc_pqedata->qc_setup); 800 qc->qc_xmit[idx].qe_addr_hi = 801 HIWORD(sc->sc_pqedata->qc_setup) | QE_SETUP | QE_EOMSG; 802 qc->qc_xmit[idx].qe_status1 = qc->qc_xmit[idx].qe_flag = QE_NOTYET; 803 qc->qc_xmit[idx].qe_addr_hi |= QE_VALID; 804 805 if (QE_RCSR(QE_CSR_CSR) & QE_XL_INVALID) { 806 QE_WCSR(QE_CSR_XMTL, 807 LOWORD(&sc->sc_pqedata->qc_xmit[idx])); 808 QE_WCSR(QE_CSR_XMTH, 809 HIWORD(&sc->sc_pqedata->qc_xmit[idx])); 810 } 811 812 sc->sc_inq++; 813 if (++sc->sc_nexttx == TXDESCS) 814 sc->sc_nexttx = 0; 815 splx(s); 816 } 817 818 /* 819 * Check for dead transmit logic. Not uncommon. 820 */ 821 void 822 qetimeout(struct ifnet *ifp) 823 { 824 struct qe_softc *sc = ifp->if_softc; 825 826 if (sc->sc_inq == 0) 827 return; 828 829 printf("%s: xmit logic died, resetting...\n", sc->sc_dev.dv_xname); 830 /* 831 * Do a reset of interface, to get it going again. 832 * Will it work by just restart the transmit logic? 833 */ 834 qeinit(sc); 835 } 836