1 /* $NetBSD: if_qereg.h,v 1.6 2001/06/19 13:42:18 wiz Exp $ */ 2 /* 3 * Copyright (c) 1988 Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * Digital Equipment Corp. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * @(#)if_qereg.h 7.3 (Berkeley) 6/28/90 38 */ 39 40 /* @(#)if_qereg.h 1.2 (ULTRIX) 1/3/85 */ 41 42 /**************************************************************** 43 * * 44 * Licensed from Digital Equipment Corporation * 45 * Copyright (c) * 46 * Digital Equipment Corporation * 47 * Maynard, Massachusetts * 48 * 1985, 1986 * 49 * All rights reserved. * 50 * * 51 * The Information in this software is subject to change * 52 * without notice and should not be construed as a commitment * 53 * by Digital Equipment Corporation. Digital makes no * 54 * representations about the suitability of this software for * 55 * any purpose. It is supplied "As Is" without expressed or * 56 * implied warranty. * 57 * * 58 * If the Regents of the University of California or its * 59 * licensees modify the software in a manner creating * 60 * derivative copyright rights, appropriate copyright * 61 * legends may be placed on the derivative work in addition * 62 * to that set forth above. * 63 * * 64 ****************************************************************/ 65 /* --------------------------------------------------------------------- 66 * Modification History 67 * 68 * 13 Feb. 84 -- rjl 69 * 70 * Initial version of driver. derived from IL driver. 71 * 72 * --------------------------------------------------------------------- 73 */ 74 75 /* 76 * Digital Q-BUS to NI Adapter 77 */ 78 #ifdef notdef 79 struct qedevice { 80 u_short qe_sta_addr[2]; /* Station address (actually 6 */ 81 u_short qe_rcvlist_lo; /* Receive list lo address */ 82 u_short qe_rcvlist_hi; /* Receive list hi address */ 83 u_short qe_xmtlist_lo; /* Transmit list lo address */ 84 u_short qe_xmtlist_hi; /* Transmit list hi address */ 85 u_short qe_vector; /* Interrupt vector */ 86 u_short qe_csr; /* Command and Status Register */ 87 }; 88 #endif 89 90 /* 91 * Register offsets in register space. 92 */ 93 #define QE_CSR_ADDR1 0 94 #define QE_CSR_ADDR2 2 95 #define QE_CSR_RCLL 4 96 #define QE_CSR_RCLH 6 97 #define QE_CSR_XMTL 8 98 #define QE_CSR_XMTH 10 99 #define QE_CSR_VECTOR 12 100 #define QE_CSR_CSR 14 101 102 /* 103 * Command and status bits (csr) 104 */ 105 #define QE_RCV_ENABLE 0x0001 /* Receiver enable */ 106 #define QE_RESET 0x0002 /* Software reset */ 107 #define QE_NEX_MEM_INT 0x0004 /* Non existent mem interrupt */ 108 #define QE_LOAD_ROM 0x0008 /* Load boot/diag from rom */ 109 #define QE_XL_INVALID 0x0010 /* Transmit list invalid */ 110 #define QE_RL_INVALID 0x0020 /* Receive list invalid */ 111 #define QE_INT_ENABLE 0x0040 /* Interrupt enable */ 112 #define QE_XMIT_INT 0x0080 /* Transmit interrupt */ 113 #define QE_ILOOP 0x0100 /* Internal loopback */ 114 #define QE_ELOOP 0x0200 /* External loopback */ 115 #define QE_STIM_ENABLE 0x0400 /* Sanity timer enable */ 116 #define QE_POWERUP 0x1000 /* Tranceiver power on */ 117 #define QE_CARRIER 0x2000 /* Carrier detect */ 118 #define QE_RCV_INT 0x8000 /* Receiver interrupt */ 119 120 /* 121 * Transmit and receive ring discriptor --------------------------- 122 * 123 * The QNA uses the flag, status1 and the valid bit as a handshake/semiphore 124 * mechinism. 125 * 126 * The flag word is written on ( bits 15,15 set to 1 ) when it reads the 127 * descriptor. If the valid bit is set it considers the address to be valid. 128 * When it uses the buffer pointed to by the valid address it sets status word 129 * one. 130 */ 131 struct qe_ring { 132 u_short qe_flag; /* Buffer utilization flags */ 133 u_short qe_addr_hi; 134 u_short qe_addr_lo; /* Low order bits of address */ 135 short qe_buf_len; /* Negative buffer length */ 136 u_short qe_status1; /* Status word one */ 137 u_short qe_status2; /* Status word two */ 138 }; 139 140 /* 141 * High word address control bits. 142 */ 143 #define QE_VALID 0x8000 144 #define QE_CHAIN 0x4000 145 #define QE_EOMSG 0x2000 146 #define QE_SETUP 0x1000 147 #define QE_ODDEND 0x0080 148 #define QE_ODDBEGIN 0x0040 149 150 /* 151 * Status word definations (receive) 152 * word1 153 */ 154 #define QE_OVF 0x0001 /* Receiver overflow */ 155 #define QE_CRCERR 0x0002 /* CRC error */ 156 #define QE_FRAME 0x0004 /* Framing alignment error */ 157 #define QE_SHORT 0x0008 /* Packet size < 10 bytes */ 158 #define QE_RBL_HI 0x0700 /* Hi bits of receive len */ 159 #define QE_RUNT 0x0800 /* Runt packet */ 160 #define QE_DISCARD 0x1000 /* Discard the packet */ 161 #define QE_ESETUP 0x2000 /* Looped back setup or eloop */ 162 #define QE_ERROR 0x4000 /* Receiver error */ 163 #define QE_LASTNOT 0x8000 /* Not the last in the packet */ 164 /* word2 */ 165 #define QE_RBL_LO 0x00ff /* Low bits of receive len */ 166 167 /* 168 * Status word definations (transmit) 169 * word1 170 */ 171 #define QE_CCNT 0x00f0 /* Collision count this packet */ 172 #define QE_FAIL 0x0100 /* Heart beat check failure */ 173 #define QE_ABORT 0x0200 /* Transmission abort */ 174 #define QE_STE16 0x0400 /* Sanity timer default on */ 175 #define QE_NOCAR 0x0800 /* No carrier */ 176 #define QE_LOSS 0x1000 /* Loss of carrier while xmit */ 177 /* word2 */ 178 #define QE_TDR 0x3fff /* Time domain reflectometry */ 179 180 /* 181 * General constant definations 182 */ 183 #define QEALLOC 0 /* Allocate an mbuf */ 184 #define QENOALLOC 1 /* No mbuf allocation */ 185 #define QEDEALLOC 2 /* Release an mbuf chain */ 186 187 #define QE_NOTYET 0x8000 /* Descriptor not in use yet */ 188 #define QE_INUSE 0x4000 /* Descriptor being used by QNA */ 189 #define QE_MASK 0xc000 /* Lastnot/error/used mask */ 190 191 /* 192 * Values for the length of the setup packet that control reception filter. 193 */ 194 #define QE_SETUPLEN 128 /* Size of setup packet */ 195 #define QE_ALLMULTI 1 /* Receive all multicasts */ 196 #define QE_PROMISC 2 /* Receive all packets */ 197