1 /* $NetBSD: be.c,v 1.37 2002/10/02 16:52:32 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.37 2002/10/02 16:52:32 thorpej Exp $"); 68 69 #include "opt_ddb.h" 70 #include "opt_inet.h" 71 #include "opt_ccitt.h" 72 #include "opt_llc.h" 73 #include "opt_ns.h" 74 #include "bpfilter.h" 75 #include "rnd.h" 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/callout.h> 80 #include <sys/kernel.h> 81 #include <sys/errno.h> 82 #include <sys/ioctl.h> 83 #include <sys/mbuf.h> 84 #include <sys/socket.h> 85 #include <sys/syslog.h> 86 #include <sys/device.h> 87 #include <sys/malloc.h> 88 #if NRND > 0 89 #include <sys/rnd.h> 90 #endif 91 92 #include <net/if.h> 93 #include <net/if_dl.h> 94 #include <net/if_types.h> 95 #include <net/netisr.h> 96 #include <net/if_media.h> 97 #include <net/if_ether.h> 98 99 #ifdef INET 100 #include <netinet/in.h> 101 #include <netinet/if_inarp.h> 102 #include <netinet/in_systm.h> 103 #include <netinet/in_var.h> 104 #include <netinet/ip.h> 105 #endif 106 107 #ifdef NS 108 #include <netns/ns.h> 109 #include <netns/ns_if.h> 110 #endif 111 112 #if NBPFILTER > 0 113 #include <net/bpf.h> 114 #include <net/bpfdesc.h> 115 #endif 116 117 #include <machine/bus.h> 118 #include <machine/intr.h> 119 #include <machine/autoconf.h> 120 121 #include <dev/sbus/sbusvar.h> 122 123 #include <dev/mii/mii.h> 124 #include <dev/mii/miivar.h> 125 126 #include <dev/sbus/qecreg.h> 127 #include <dev/sbus/qecvar.h> 128 #include <dev/sbus/bereg.h> 129 130 struct be_softc { 131 struct device sc_dev; 132 struct sbusdev sc_sd; /* sbus device */ 133 bus_space_tag_t sc_bustag; /* bus & dma tags */ 134 bus_dma_tag_t sc_dmatag; 135 bus_dmamap_t sc_dmamap; 136 struct ethercom sc_ethercom; 137 /*struct ifmedia sc_ifmedia; -* interface media */ 138 struct mii_data sc_mii; /* MII media control */ 139 #define sc_media sc_mii.mii_media/* shorthand */ 140 int sc_phys[2]; /* MII instance -> phy */ 141 142 struct callout sc_tick_ch; 143 144 /* 145 * Some `mii_softc' items we need to emulate MII operation 146 * for our internal transceiver. 147 */ 148 int sc_mii_inst; /* instance of internal phy */ 149 int sc_mii_active; /* currently active medium */ 150 int sc_mii_ticks; /* tick counter */ 151 int sc_mii_flags; /* phy status flags */ 152 #define MIIF_HAVELINK 0x04000000 153 int sc_intphy_curspeed; /* Established link speed */ 154 155 struct qec_softc *sc_qec; /* QEC parent */ 156 157 bus_space_handle_t sc_qr; /* QEC registers */ 158 bus_space_handle_t sc_br; /* BE registers */ 159 bus_space_handle_t sc_cr; /* channel registers */ 160 bus_space_handle_t sc_tr; /* transceiver registers */ 161 162 u_int sc_rev; 163 164 int sc_channel; /* channel number */ 165 int sc_burst; 166 167 struct qec_ring sc_rb; /* Packet Ring Buffer */ 168 169 /* MAC address */ 170 u_int8_t sc_enaddr[6]; 171 }; 172 173 int bematch __P((struct device *, struct cfdata *, void *)); 174 void beattach __P((struct device *, struct device *, void *)); 175 176 void beinit __P((struct be_softc *)); 177 void bestart __P((struct ifnet *)); 178 void bestop __P((struct be_softc *)); 179 void bewatchdog __P((struct ifnet *)); 180 int beioctl __P((struct ifnet *, u_long, caddr_t)); 181 void bereset __P((struct be_softc *)); 182 183 int beintr __P((void *)); 184 int berint __P((struct be_softc *)); 185 int betint __P((struct be_softc *)); 186 int beqint __P((struct be_softc *, u_int32_t)); 187 int beeint __P((struct be_softc *, u_int32_t)); 188 189 static void be_read __P((struct be_softc *, int, int)); 190 static int be_put __P((struct be_softc *, int, struct mbuf *)); 191 static struct mbuf *be_get __P((struct be_softc *, int, int)); 192 193 void be_pal_gate __P((struct be_softc *, int)); 194 195 /* ifmedia callbacks */ 196 void be_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 197 int be_ifmedia_upd __P((struct ifnet *)); 198 199 void be_mcreset __P((struct be_softc *)); 200 201 /* MII methods & callbacks */ 202 static int be_mii_readreg __P((struct device *, int, int)); 203 static void be_mii_writereg __P((struct device *, int, int, int)); 204 static void be_mii_statchg __P((struct device *)); 205 206 /* MII helpers */ 207 static void be_mii_sync __P((struct be_softc *)); 208 static void be_mii_sendbits __P((struct be_softc *, int, u_int32_t, int)); 209 static int be_mii_reset __P((struct be_softc *, int)); 210 static int be_tcvr_read_bit __P((struct be_softc *, int)); 211 static void be_tcvr_write_bit __P((struct be_softc *, int, int)); 212 213 void be_tick __P((void *)); 214 void be_intphy_auto __P((struct be_softc *)); 215 void be_intphy_status __P((struct be_softc *)); 216 int be_intphy_service __P((struct be_softc *, struct mii_data *, int)); 217 218 219 CFATTACH_DECL(be, sizeof(struct be_softc), 220 bematch, beattach, NULL, NULL); 221 222 int 223 bematch(parent, cf, aux) 224 struct device *parent; 225 struct cfdata *cf; 226 void *aux; 227 { 228 struct sbus_attach_args *sa = aux; 229 230 return (strcmp(cf->cf_name, sa->sa_name) == 0); 231 } 232 233 void 234 beattach(parent, self, aux) 235 struct device *parent, *self; 236 void *aux; 237 { 238 struct sbus_attach_args *sa = aux; 239 struct qec_softc *qec = (struct qec_softc *)parent; 240 struct be_softc *sc = (struct be_softc *)self; 241 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 242 struct mii_data *mii = &sc->sc_mii; 243 struct mii_softc *child; 244 int node = sa->sa_node; 245 bus_dma_tag_t dmatag = sa->sa_dmatag; 246 bus_dma_segment_t seg; 247 bus_size_t size; 248 int instance; 249 int rseg, error; 250 u_int32_t v; 251 extern void myetheraddr __P((u_char *)); 252 253 if (sa->sa_nreg < 3) { 254 printf("%s: only %d register sets\n", 255 self->dv_xname, sa->sa_nreg); 256 return; 257 } 258 259 if (bus_space_map(sa->sa_bustag, 260 (bus_addr_t)BUS_ADDR( 261 sa->sa_reg[0].oa_space, 262 sa->sa_reg[0].oa_base), 263 (bus_size_t)sa->sa_reg[0].oa_size, 264 0, &sc->sc_cr) != 0) { 265 printf("beattach: cannot map registers\n"); 266 return; 267 } 268 269 if (bus_space_map(sa->sa_bustag, 270 (bus_addr_t)BUS_ADDR( 271 sa->sa_reg[1].oa_space, 272 sa->sa_reg[1].oa_base), 273 (bus_size_t)sa->sa_reg[1].oa_size, 274 0, &sc->sc_br) != 0) { 275 printf("beattach: cannot map registers\n"); 276 return; 277 } 278 279 if (bus_space_map(sa->sa_bustag, 280 (bus_addr_t)BUS_ADDR( 281 sa->sa_reg[2].oa_space, 282 sa->sa_reg[2].oa_base), 283 (bus_size_t)sa->sa_reg[2].oa_size, 284 0, &sc->sc_tr) != 0) { 285 printf("beattach: cannot map registers\n"); 286 return; 287 } 288 289 sc->sc_bustag = sa->sa_bustag; 290 sc->sc_qec = qec; 291 sc->sc_qr = qec->sc_regs; 292 293 sc->sc_rev = PROM_getpropint(node, "board-version", -1); 294 printf(" rev %x", sc->sc_rev); 295 296 bestop(sc); 297 298 sc->sc_channel = PROM_getpropint(node, "channel#", -1); 299 if (sc->sc_channel == -1) 300 sc->sc_channel = 0; 301 302 sc->sc_burst = PROM_getpropint(node, "burst-sizes", -1); 303 if (sc->sc_burst == -1) 304 sc->sc_burst = qec->sc_burst; 305 306 /* Clamp at parent's burst sizes */ 307 sc->sc_burst &= qec->sc_burst; 308 309 /* Establish interrupt handler */ 310 if (sa->sa_nintr) 311 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 312 0, beintr, sc); 313 314 myetheraddr(sc->sc_enaddr); 315 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 316 317 /* 318 * Allocate descriptor ring and buffers. 319 */ 320 321 /* for now, allocate as many bufs as there are ring descriptors */ 322 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 323 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 324 325 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 326 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 327 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 328 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 329 330 /* Get a DMA handle */ 331 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 332 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 333 printf("%s: DMA map create error %d\n", self->dv_xname, error); 334 return; 335 } 336 337 /* Allocate DMA buffer */ 338 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 339 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 340 printf("%s: DMA buffer alloc error %d\n", 341 self->dv_xname, error); 342 return; 343 } 344 345 /* Map DMA memory in CPU addressable space */ 346 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 347 &sc->sc_rb.rb_membase, 348 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 349 printf("%s: DMA buffer map error %d\n", 350 self->dv_xname, error); 351 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 352 return; 353 } 354 355 /* Load the buffer */ 356 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 357 sc->sc_rb.rb_membase, size, NULL, 358 BUS_DMA_NOWAIT)) != 0) { 359 printf("%s: DMA buffer map load error %d\n", 360 self->dv_xname, error); 361 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 362 bus_dmamem_free(dmatag, &seg, rseg); 363 return; 364 } 365 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 366 367 /* 368 * Initialize our media structures and MII info. 369 */ 370 mii->mii_ifp = ifp; 371 mii->mii_readreg = be_mii_readreg; 372 mii->mii_writereg = be_mii_writereg; 373 mii->mii_statchg = be_mii_statchg; 374 375 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 376 377 callout_init(&sc->sc_tick_ch); 378 379 /* 380 * Initialize transceiver and determine which PHY connection to use. 381 */ 382 be_mii_sync(sc); 383 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 384 385 instance = 0; 386 387 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 388 389 mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, 390 MII_OFFSET_ANY, 0); 391 392 child = LIST_FIRST(&mii->mii_phys); 393 if (child == NULL) { 394 /* No PHY attached */ 395 ifmedia_add(&sc->sc_media, 396 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 397 0, NULL); 398 ifmedia_set(&sc->sc_media, 399 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 400 } else { 401 /* 402 * Note: we support just one PHY on the external 403 * MII connector. 404 */ 405 #ifdef DIAGNOSTIC 406 if (LIST_NEXT(child, mii_list) != NULL) { 407 printf("%s: spurious MII device %s attached\n", 408 sc->sc_dev.dv_xname, 409 child->mii_dev.dv_xname); 410 } 411 #endif 412 if (child->mii_phy != BE_PHY_EXTERNAL || 413 child->mii_inst > 0) { 414 printf("%s: cannot accomodate MII device %s" 415 " at phy %d, instance %d\n", 416 sc->sc_dev.dv_xname, 417 child->mii_dev.dv_xname, 418 child->mii_phy, child->mii_inst); 419 } else { 420 sc->sc_phys[instance] = child->mii_phy; 421 } 422 423 /* 424 * XXX - we can really do the following ONLY if the 425 * phy indeed has the auto negotiation capability!! 426 */ 427 ifmedia_set(&sc->sc_media, 428 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 429 430 /* Mark our current media setting */ 431 be_pal_gate(sc, BE_PHY_EXTERNAL); 432 instance++; 433 } 434 435 } 436 437 if ((v & MGMT_PAL_INT_MDIO) != 0) { 438 /* 439 * The be internal phy looks vaguely like MII hardware, 440 * but not enough to be able to use the MII device 441 * layer. Hence, we have to take care of media selection 442 * ourselves. 443 */ 444 445 sc->sc_mii_inst = instance; 446 sc->sc_phys[instance] = BE_PHY_INTERNAL; 447 448 /* Use `ifm_data' to store BMCR bits */ 449 ifmedia_add(&sc->sc_media, 450 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 451 0, NULL); 452 ifmedia_add(&sc->sc_media, 453 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 454 BMCR_S100, NULL); 455 ifmedia_add(&sc->sc_media, 456 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 457 0, NULL); 458 459 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 460 self->dv_xname); 461 462 be_mii_reset(sc, BE_PHY_INTERNAL); 463 /* Only set default medium here if there's no external PHY */ 464 if (instance == 0) { 465 be_pal_gate(sc, BE_PHY_INTERNAL); 466 ifmedia_set(&sc->sc_media, 467 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 468 } else 469 be_mii_writereg((void *)sc, 470 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 471 } 472 473 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 474 ifp->if_softc = sc; 475 ifp->if_start = bestart; 476 ifp->if_ioctl = beioctl; 477 ifp->if_watchdog = bewatchdog; 478 ifp->if_flags = 479 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 480 IFQ_SET_READY(&ifp->if_snd); 481 482 /* Attach the interface. */ 483 if_attach(ifp); 484 ether_ifattach(ifp, sc->sc_enaddr); 485 } 486 487 488 /* 489 * Routine to copy from mbuf chain to transmit buffer in 490 * network buffer memory. 491 */ 492 static __inline__ int 493 be_put(sc, idx, m) 494 struct be_softc *sc; 495 int idx; 496 struct mbuf *m; 497 { 498 struct mbuf *n; 499 int len, tlen = 0, boff = 0; 500 caddr_t bp; 501 502 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 503 504 for (; m; m = n) { 505 len = m->m_len; 506 if (len == 0) { 507 MFREE(m, n); 508 continue; 509 } 510 bcopy(mtod(m, caddr_t), bp+boff, len); 511 boff += len; 512 tlen += len; 513 MFREE(m, n); 514 } 515 return (tlen); 516 } 517 518 /* 519 * Pull data off an interface. 520 * Len is the length of data, with local net header stripped. 521 * We copy the data into mbufs. When full cluster sized units are present, 522 * we copy into clusters. 523 */ 524 static __inline__ struct mbuf * 525 be_get(sc, idx, totlen) 526 struct be_softc *sc; 527 int idx, totlen; 528 { 529 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 530 struct mbuf *m; 531 struct mbuf *top, **mp; 532 int len, pad, boff = 0; 533 caddr_t bp; 534 535 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 536 537 MGETHDR(m, M_DONTWAIT, MT_DATA); 538 if (m == NULL) 539 return (NULL); 540 m->m_pkthdr.rcvif = ifp; 541 m->m_pkthdr.len = totlen; 542 543 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 544 m->m_data += pad; 545 len = MHLEN - pad; 546 top = NULL; 547 mp = ⊤ 548 549 while (totlen > 0) { 550 if (top) { 551 MGET(m, M_DONTWAIT, MT_DATA); 552 if (m == NULL) { 553 m_freem(top); 554 return (NULL); 555 } 556 len = MLEN; 557 } 558 if (top && totlen >= MINCLSIZE) { 559 MCLGET(m, M_DONTWAIT); 560 if (m->m_flags & M_EXT) 561 len = MCLBYTES; 562 } 563 m->m_len = len = min(totlen, len); 564 bcopy(bp + boff, mtod(m, caddr_t), len); 565 boff += len; 566 totlen -= len; 567 *mp = m; 568 mp = &m->m_next; 569 } 570 571 return (top); 572 } 573 574 /* 575 * Pass a packet to the higher levels. 576 */ 577 static __inline__ void 578 be_read(sc, idx, len) 579 struct be_softc *sc; 580 int idx, len; 581 { 582 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 583 struct mbuf *m; 584 585 if (len <= sizeof(struct ether_header) || 586 len > ETHERMTU + sizeof(struct ether_header)) { 587 588 printf("%s: invalid packet size %d; dropping\n", 589 ifp->if_xname, len); 590 591 ifp->if_ierrors++; 592 return; 593 } 594 595 /* 596 * Pull packet off interface. 597 */ 598 m = be_get(sc, idx, len); 599 if (m == NULL) { 600 ifp->if_ierrors++; 601 return; 602 } 603 ifp->if_ipackets++; 604 605 #if NBPFILTER > 0 606 /* 607 * Check if there's a BPF listener on this interface. 608 * If so, hand off the raw packet to BPF. 609 */ 610 if (ifp->if_bpf) 611 bpf_mtap(ifp->if_bpf, m); 612 #endif 613 /* Pass the packet up. */ 614 (*ifp->if_input)(ifp, m); 615 } 616 617 /* 618 * Start output on interface. 619 * We make two assumptions here: 620 * 1) that the current priority is set to splnet _before_ this code 621 * is called *and* is returned to the appropriate priority after 622 * return 623 * 2) that the IFF_OACTIVE flag is checked before this code is called 624 * (i.e. that the output part of the interface is idle) 625 */ 626 void 627 bestart(ifp) 628 struct ifnet *ifp; 629 { 630 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 631 struct qec_xd *txd = sc->sc_rb.rb_txd; 632 struct mbuf *m; 633 unsigned int bix, len; 634 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 635 636 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 637 return; 638 639 bix = sc->sc_rb.rb_tdhead; 640 641 for (;;) { 642 IFQ_DEQUEUE(&ifp->if_snd, m); 643 if (m == 0) 644 break; 645 646 #if NBPFILTER > 0 647 /* 648 * If BPF is listening on this interface, let it see the 649 * packet before we commit it to the wire. 650 */ 651 if (ifp->if_bpf) 652 bpf_mtap(ifp->if_bpf, m); 653 #endif 654 655 /* 656 * Copy the mbuf chain into the transmit buffer. 657 */ 658 len = be_put(sc, bix, m); 659 660 /* 661 * Initialize transmit registers and start transmission 662 */ 663 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 664 (len & QEC_XD_LENGTH); 665 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 666 BE_CR_CTRL_TWAKEUP); 667 668 if (++bix == QEC_XD_RING_MAXSIZE) 669 bix = 0; 670 671 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 672 ifp->if_flags |= IFF_OACTIVE; 673 break; 674 } 675 } 676 677 sc->sc_rb.rb_tdhead = bix; 678 } 679 680 void 681 bestop(sc) 682 struct be_softc *sc; 683 { 684 int n; 685 bus_space_tag_t t = sc->sc_bustag; 686 bus_space_handle_t br = sc->sc_br; 687 688 callout_stop(&sc->sc_tick_ch); 689 690 /* Down the MII. */ 691 mii_down(&sc->sc_mii); 692 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 693 694 /* Stop the transmitter */ 695 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 696 for (n = 32; n > 0; n--) { 697 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 698 break; 699 DELAY(20); 700 } 701 702 /* Stop the receiver */ 703 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 704 for (n = 32; n > 0; n--) { 705 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 706 break; 707 DELAY(20); 708 } 709 } 710 711 /* 712 * Reset interface. 713 */ 714 void 715 bereset(sc) 716 struct be_softc *sc; 717 { 718 int s; 719 720 s = splnet(); 721 bestop(sc); 722 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 723 beinit(sc); 724 splx(s); 725 } 726 727 void 728 bewatchdog(ifp) 729 struct ifnet *ifp; 730 { 731 struct be_softc *sc = ifp->if_softc; 732 733 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 734 ++sc->sc_ethercom.ec_if.if_oerrors; 735 736 bereset(sc); 737 } 738 739 int 740 beintr(v) 741 void *v; 742 { 743 struct be_softc *sc = (struct be_softc *)v; 744 bus_space_tag_t t = sc->sc_bustag; 745 u_int32_t whyq, whyb, whyc; 746 int r = 0; 747 748 /* Read QEC status, channel status and BE status */ 749 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 750 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 751 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 752 753 if (whyq & QEC_STAT_BM) 754 r |= beeint(sc, whyb); 755 756 if (whyq & QEC_STAT_ER) 757 r |= beqint(sc, whyc); 758 759 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 760 r |= betint(sc); 761 762 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 763 r |= berint(sc); 764 765 return (r); 766 } 767 768 /* 769 * QEC Interrupt. 770 */ 771 int 772 beqint(sc, why) 773 struct be_softc *sc; 774 u_int32_t why; 775 { 776 int r = 0, rst = 0; 777 778 if (why & BE_CR_STAT_TXIRQ) 779 r |= 1; 780 if (why & BE_CR_STAT_RXIRQ) 781 r |= 1; 782 783 if (why & BE_CR_STAT_BERROR) { 784 r |= 1; 785 rst = 1; 786 printf("%s: bigmac error\n", sc->sc_dev.dv_xname); 787 } 788 789 if (why & BE_CR_STAT_TXDERR) { 790 r |= 1; 791 rst = 1; 792 printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname); 793 } 794 795 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 796 r |= 1; 797 rst = 1; 798 printf("%s: tx dma error ( ", sc->sc_dev.dv_xname); 799 if (why & BE_CR_STAT_TXLERR) 800 printf("Late "); 801 if (why & BE_CR_STAT_TXPERR) 802 printf("Parity "); 803 if (why & BE_CR_STAT_TXSERR) 804 printf("Generic "); 805 printf(")\n"); 806 } 807 808 if (why & BE_CR_STAT_RXDROP) { 809 r |= 1; 810 rst = 1; 811 printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname); 812 } 813 814 if (why & BE_CR_STAT_RXSMALL) { 815 r |= 1; 816 rst = 1; 817 printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname); 818 } 819 820 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 821 r |= 1; 822 rst = 1; 823 printf("%s: rx dma error ( ", sc->sc_dev.dv_xname); 824 if (why & BE_CR_STAT_RXLERR) 825 printf("Late "); 826 if (why & BE_CR_STAT_RXPERR) 827 printf("Parity "); 828 if (why & BE_CR_STAT_RXSERR) 829 printf("Generic "); 830 printf(")\n"); 831 } 832 833 if (!r) { 834 rst = 1; 835 printf("%s: unexpected error interrupt %08x\n", 836 sc->sc_dev.dv_xname, why); 837 } 838 839 if (rst) { 840 printf("%s: resetting\n", sc->sc_dev.dv_xname); 841 bereset(sc); 842 } 843 844 return (r); 845 } 846 847 /* 848 * Error interrupt. 849 */ 850 int 851 beeint(sc, why) 852 struct be_softc *sc; 853 u_int32_t why; 854 { 855 int r = 0, rst = 0; 856 857 if (why & BE_BR_STAT_RFIFOVF) { 858 r |= 1; 859 rst = 1; 860 printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname); 861 } 862 if (why & BE_BR_STAT_TFIFO_UND) { 863 r |= 1; 864 rst = 1; 865 printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname); 866 } 867 if (why & BE_BR_STAT_MAXPKTERR) { 868 r |= 1; 869 rst = 1; 870 printf("%s: max packet size error\n", sc->sc_dev.dv_xname); 871 } 872 873 if (!r) { 874 rst = 1; 875 printf("%s: unexpected error interrupt %08x\n", 876 sc->sc_dev.dv_xname, why); 877 } 878 879 if (rst) { 880 printf("%s: resetting\n", sc->sc_dev.dv_xname); 881 bereset(sc); 882 } 883 884 return (r); 885 } 886 887 /* 888 * Transmit interrupt. 889 */ 890 int 891 betint(sc) 892 struct be_softc *sc; 893 { 894 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 895 bus_space_tag_t t = sc->sc_bustag; 896 bus_space_handle_t br = sc->sc_br; 897 unsigned int bix, txflags; 898 899 /* 900 * Unload collision counters 901 */ 902 ifp->if_collisions += 903 bus_space_read_4(t, br, BE_BRI_NCCNT) + 904 bus_space_read_4(t, br, BE_BRI_FCCNT) + 905 bus_space_read_4(t, br, BE_BRI_EXCNT) + 906 bus_space_read_4(t, br, BE_BRI_LTCNT); 907 908 /* 909 * the clear the hardware counters 910 */ 911 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 912 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 913 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 914 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 915 916 bix = sc->sc_rb.rb_tdtail; 917 918 for (;;) { 919 if (sc->sc_rb.rb_td_nbusy <= 0) 920 break; 921 922 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 923 924 if (txflags & QEC_XD_OWN) 925 break; 926 927 ifp->if_flags &= ~IFF_OACTIVE; 928 ifp->if_opackets++; 929 930 if (++bix == QEC_XD_RING_MAXSIZE) 931 bix = 0; 932 933 --sc->sc_rb.rb_td_nbusy; 934 } 935 936 sc->sc_rb.rb_tdtail = bix; 937 938 bestart(ifp); 939 940 if (sc->sc_rb.rb_td_nbusy == 0) 941 ifp->if_timer = 0; 942 943 return (1); 944 } 945 946 /* 947 * Receive interrupt. 948 */ 949 int 950 berint(sc) 951 struct be_softc *sc; 952 { 953 struct qec_xd *xd = sc->sc_rb.rb_rxd; 954 unsigned int bix, len; 955 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 956 957 bix = sc->sc_rb.rb_rdtail; 958 959 /* 960 * Process all buffers with valid data. 961 */ 962 for (;;) { 963 len = xd[bix].xd_flags; 964 if (len & QEC_XD_OWN) 965 break; 966 967 len &= QEC_XD_LENGTH; 968 be_read(sc, bix, len); 969 970 /* ... */ 971 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 972 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 973 974 if (++bix == QEC_XD_RING_MAXSIZE) 975 bix = 0; 976 } 977 978 sc->sc_rb.rb_rdtail = bix; 979 980 return (1); 981 } 982 983 int 984 beioctl(ifp, cmd, data) 985 struct ifnet *ifp; 986 u_long cmd; 987 caddr_t data; 988 { 989 struct be_softc *sc = ifp->if_softc; 990 struct ifaddr *ifa = (struct ifaddr *)data; 991 struct ifreq *ifr = (struct ifreq *)data; 992 int s, error = 0; 993 994 s = splnet(); 995 996 switch (cmd) { 997 case SIOCSIFADDR: 998 ifp->if_flags |= IFF_UP; 999 switch (ifa->ifa_addr->sa_family) { 1000 #ifdef INET 1001 case AF_INET: 1002 beinit(sc); 1003 arp_ifinit(ifp, ifa); 1004 break; 1005 #endif /* INET */ 1006 #ifdef NS 1007 case AF_NS: 1008 { 1009 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1010 1011 if (ns_nullhost(*ina)) 1012 ina->x_host = 1013 *(union ns_host *)LLADDR(ifp->if_sadl); 1014 else 1015 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1016 sizeof(sc->sc_enaddr)); 1017 /* Set new address. */ 1018 beinit(sc); 1019 break; 1020 } 1021 #endif /* NS */ 1022 default: 1023 beinit(sc); 1024 break; 1025 } 1026 break; 1027 1028 case SIOCSIFFLAGS: 1029 if ((ifp->if_flags & IFF_UP) == 0 && 1030 (ifp->if_flags & IFF_RUNNING) != 0) { 1031 /* 1032 * If interface is marked down and it is running, then 1033 * stop it. 1034 */ 1035 bestop(sc); 1036 ifp->if_flags &= ~IFF_RUNNING; 1037 } else if ((ifp->if_flags & IFF_UP) != 0 && 1038 (ifp->if_flags & IFF_RUNNING) == 0) { 1039 /* 1040 * If interface is marked up and it is stopped, then 1041 * start it. 1042 */ 1043 beinit(sc); 1044 } else { 1045 /* 1046 * Reset the interface to pick up changes in any other 1047 * flags that affect hardware registers. 1048 */ 1049 bestop(sc); 1050 beinit(sc); 1051 } 1052 #ifdef BEDEBUG 1053 if (ifp->if_flags & IFF_DEBUG) 1054 sc->sc_debug = 1; 1055 else 1056 sc->sc_debug = 0; 1057 #endif 1058 break; 1059 1060 case SIOCADDMULTI: 1061 case SIOCDELMULTI: 1062 error = (cmd == SIOCADDMULTI) ? 1063 ether_addmulti(ifr, &sc->sc_ethercom): 1064 ether_delmulti(ifr, &sc->sc_ethercom); 1065 1066 if (error == ENETRESET) { 1067 /* 1068 * Multicast list has changed; set the hardware filter 1069 * accordingly. 1070 */ 1071 be_mcreset(sc); 1072 error = 0; 1073 } 1074 break; 1075 case SIOCGIFMEDIA: 1076 case SIOCSIFMEDIA: 1077 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1078 break; 1079 default: 1080 error = EINVAL; 1081 break; 1082 } 1083 splx(s); 1084 return (error); 1085 } 1086 1087 1088 void 1089 beinit(sc) 1090 struct be_softc *sc; 1091 { 1092 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1093 bus_space_tag_t t = sc->sc_bustag; 1094 bus_space_handle_t br = sc->sc_br; 1095 bus_space_handle_t cr = sc->sc_cr; 1096 struct qec_softc *qec = sc->sc_qec; 1097 u_int32_t v; 1098 u_int32_t qecaddr; 1099 u_int8_t *ea; 1100 int s; 1101 1102 s = splnet(); 1103 1104 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1105 1106 bestop(sc); 1107 1108 ea = sc->sc_enaddr; 1109 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1110 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1111 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1112 1113 /* Clear hash table */ 1114 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1115 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1116 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1117 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1118 1119 /* Re-initialize RX configuration */ 1120 v = BE_BR_RXCFG_FIFO; 1121 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1122 1123 be_mcreset(sc); 1124 1125 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1126 1127 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1128 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1129 1130 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1131 1132 /* 1133 * Turn off counter expiration interrupts as well as 1134 * 'gotframe' and 'sentframe' 1135 */ 1136 bus_space_write_4(t, br, BE_BRI_IMASK, 1137 BE_BR_IMASK_GOTFRAME | 1138 BE_BR_IMASK_RCNTEXP | 1139 BE_BR_IMASK_ACNTEXP | 1140 BE_BR_IMASK_CCNTEXP | 1141 BE_BR_IMASK_LCNTEXP | 1142 BE_BR_IMASK_CVCNTEXP | 1143 BE_BR_IMASK_SENTFRAME | 1144 BE_BR_IMASK_NCNTEXP | 1145 BE_BR_IMASK_ECNTEXP | 1146 BE_BR_IMASK_LCCNTEXP | 1147 BE_BR_IMASK_FCNTEXP | 1148 BE_BR_IMASK_DTIMEXP); 1149 1150 /* Channel registers: */ 1151 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1152 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1153 1154 qecaddr = sc->sc_channel * qec->sc_msize; 1155 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1156 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1157 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1158 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1159 1160 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1161 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1162 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1163 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1164 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1165 1166 /* Enable transmitter */ 1167 bus_space_write_4(t, br, BE_BRI_TXCFG, 1168 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1169 1170 /* Enable receiver */ 1171 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1172 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1173 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1174 1175 ifp->if_flags |= IFF_RUNNING; 1176 ifp->if_flags &= ~IFF_OACTIVE; 1177 1178 be_ifmedia_upd(ifp); 1179 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1180 splx(s); 1181 } 1182 1183 void 1184 be_mcreset(sc) 1185 struct be_softc *sc; 1186 { 1187 struct ethercom *ec = &sc->sc_ethercom; 1188 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1189 bus_space_tag_t t = sc->sc_bustag; 1190 bus_space_handle_t br = sc->sc_br; 1191 u_int32_t crc; 1192 u_int16_t hash[4]; 1193 u_int8_t octet; 1194 u_int32_t v; 1195 int i, j; 1196 struct ether_multi *enm; 1197 struct ether_multistep step; 1198 1199 if (ifp->if_flags & IFF_PROMISC) { 1200 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1201 v |= BE_BR_RXCFG_PMISC; 1202 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1203 return; 1204 } 1205 1206 if (ifp->if_flags & IFF_ALLMULTI) { 1207 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1208 goto chipit; 1209 } 1210 1211 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1212 1213 ETHER_FIRST_MULTI(step, ec, enm); 1214 while (enm != NULL) { 1215 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1216 /* 1217 * We must listen to a range of multicast 1218 * addresses. For now, just accept all 1219 * multicasts, rather than trying to set only 1220 * those filter bits needed to match the range. 1221 * (At this time, the only use of address 1222 * ranges is for IP multicast routing, for 1223 * which the range is big enough to require 1224 * all bits set.) 1225 */ 1226 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1227 ifp->if_flags |= IFF_ALLMULTI; 1228 goto chipit; 1229 } 1230 1231 crc = 0xffffffff; 1232 1233 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1234 octet = enm->enm_addrlo[i]; 1235 1236 for (j = 0; j < 8; j++) { 1237 if ((crc & 1) ^ (octet & 1)) { 1238 crc >>= 1; 1239 crc ^= MC_POLY_LE; 1240 } 1241 else 1242 crc >>= 1; 1243 octet >>= 1; 1244 } 1245 } 1246 1247 crc >>= 26; 1248 hash[crc >> 4] |= 1 << (crc & 0xf); 1249 ETHER_NEXT_MULTI(step, enm); 1250 } 1251 1252 ifp->if_flags &= ~IFF_ALLMULTI; 1253 1254 chipit: 1255 /* Enable the hash filter */ 1256 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1257 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1258 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1259 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1260 1261 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1262 v &= ~BE_BR_RXCFG_PMISC; 1263 v |= BE_BR_RXCFG_HENABLE; 1264 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1265 } 1266 1267 /* 1268 * Set the tcvr to an idle state 1269 */ 1270 void 1271 be_mii_sync(sc) 1272 struct be_softc *sc; 1273 { 1274 bus_space_tag_t t = sc->sc_bustag; 1275 bus_space_handle_t tr = sc->sc_tr; 1276 int n = 32; 1277 1278 while (n--) { 1279 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1280 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1281 MGMT_PAL_OENAB); 1282 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1283 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1284 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1285 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1286 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1287 } 1288 } 1289 1290 void 1291 be_pal_gate(sc, phy) 1292 struct be_softc *sc; 1293 int phy; 1294 { 1295 bus_space_tag_t t = sc->sc_bustag; 1296 bus_space_handle_t tr = sc->sc_tr; 1297 u_int32_t v; 1298 1299 be_mii_sync(sc); 1300 1301 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1302 if (phy == BE_PHY_INTERNAL) 1303 v &= ~TCVR_PAL_SERIAL; 1304 1305 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1306 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1307 } 1308 1309 static int 1310 be_tcvr_read_bit(sc, phy) 1311 struct be_softc *sc; 1312 int phy; 1313 { 1314 bus_space_tag_t t = sc->sc_bustag; 1315 bus_space_handle_t tr = sc->sc_tr; 1316 int ret; 1317 1318 if (phy == BE_PHY_INTERNAL) { 1319 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1320 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1321 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1322 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1323 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1324 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1325 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1326 } else { 1327 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1328 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1329 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1330 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1331 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1332 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1333 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1334 } 1335 1336 return (ret); 1337 } 1338 1339 static void 1340 be_tcvr_write_bit(sc, phy, bit) 1341 struct be_softc *sc; 1342 int phy; 1343 int bit; 1344 { 1345 bus_space_tag_t t = sc->sc_bustag; 1346 bus_space_handle_t tr = sc->sc_tr; 1347 u_int32_t v; 1348 1349 if (phy == BE_PHY_INTERNAL) { 1350 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1351 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1352 } else { 1353 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1354 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1355 } 1356 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1357 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1358 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1359 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1360 } 1361 1362 static void 1363 be_mii_sendbits(sc, phy, data, nbits) 1364 struct be_softc *sc; 1365 int phy; 1366 u_int32_t data; 1367 int nbits; 1368 { 1369 int i; 1370 1371 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1372 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1373 } 1374 } 1375 1376 static int 1377 be_mii_readreg(self, phy, reg) 1378 struct device *self; 1379 int phy, reg; 1380 { 1381 struct be_softc *sc = (struct be_softc *)self; 1382 int val = 0, i; 1383 1384 /* 1385 * Read the PHY register by manually driving the MII control lines. 1386 */ 1387 be_mii_sync(sc); 1388 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1389 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1390 be_mii_sendbits(sc, phy, phy, 5); 1391 be_mii_sendbits(sc, phy, reg, 5); 1392 1393 (void) be_tcvr_read_bit(sc, phy); 1394 (void) be_tcvr_read_bit(sc, phy); 1395 1396 for (i = 15; i >= 0; i--) 1397 val |= (be_tcvr_read_bit(sc, phy) << i); 1398 1399 (void) be_tcvr_read_bit(sc, phy); 1400 (void) be_tcvr_read_bit(sc, phy); 1401 (void) be_tcvr_read_bit(sc, phy); 1402 1403 return (val); 1404 } 1405 1406 void 1407 be_mii_writereg(self, phy, reg, val) 1408 struct device *self; 1409 int phy, reg, val; 1410 { 1411 struct be_softc *sc = (struct be_softc *)self; 1412 int i; 1413 1414 /* 1415 * Write the PHY register by manually driving the MII control lines. 1416 */ 1417 be_mii_sync(sc); 1418 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1419 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1420 be_mii_sendbits(sc, phy, phy, 5); 1421 be_mii_sendbits(sc, phy, reg, 5); 1422 1423 be_tcvr_write_bit(sc, phy, 1); 1424 be_tcvr_write_bit(sc, phy, 0); 1425 1426 for (i = 15; i >= 0; i--) 1427 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1428 } 1429 1430 int 1431 be_mii_reset(sc, phy) 1432 struct be_softc *sc; 1433 int phy; 1434 { 1435 int n; 1436 1437 be_mii_writereg((struct device *)sc, phy, MII_BMCR, 1438 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1439 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET); 1440 1441 for (n = 16; n >= 0; n--) { 1442 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1443 if ((bmcr & BMCR_RESET) == 0) 1444 break; 1445 DELAY(20); 1446 } 1447 if (n == 0) { 1448 printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname); 1449 return (EIO); 1450 } 1451 1452 return (0); 1453 } 1454 1455 void 1456 be_tick(arg) 1457 void *arg; 1458 { 1459 struct be_softc *sc = arg; 1460 int s = splnet(); 1461 1462 mii_tick(&sc->sc_mii); 1463 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1464 1465 splx(s); 1466 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1467 } 1468 1469 void 1470 be_mii_statchg(self) 1471 struct device *self; 1472 { 1473 struct be_softc *sc = (struct be_softc *)self; 1474 bus_space_tag_t t = sc->sc_bustag; 1475 bus_space_handle_t br = sc->sc_br; 1476 u_int instance; 1477 u_int32_t v; 1478 1479 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1480 #ifdef DIAGNOSTIC 1481 if (instance > 1) 1482 panic("be_mii_statchg: instance %d out of range", instance); 1483 #endif 1484 1485 /* Update duplex mode in TX configuration */ 1486 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1487 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1488 v |= BE_BR_TXCFG_FULLDPLX; 1489 else 1490 v &= ~BE_BR_TXCFG_FULLDPLX; 1491 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1492 1493 /* Change to appropriate gate in transceiver PAL */ 1494 be_pal_gate(sc, sc->sc_phys[instance]); 1495 } 1496 1497 /* 1498 * Get current media settings. 1499 */ 1500 void 1501 be_ifmedia_sts(ifp, ifmr) 1502 struct ifnet *ifp; 1503 struct ifmediareq *ifmr; 1504 { 1505 struct be_softc *sc = ifp->if_softc; 1506 1507 mii_pollstat(&sc->sc_mii); 1508 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1509 1510 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1511 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1512 return; 1513 } 1514 1515 /* 1516 * Set media options. 1517 */ 1518 int 1519 be_ifmedia_upd(ifp) 1520 struct ifnet *ifp; 1521 { 1522 struct be_softc *sc = ifp->if_softc; 1523 int error; 1524 1525 if ((error = mii_mediachg(&sc->sc_mii)) != 0) 1526 return (error); 1527 1528 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1529 } 1530 1531 /* 1532 * Service routine for our pseudo-MII internal transceiver. 1533 */ 1534 int 1535 be_intphy_service(sc, mii, cmd) 1536 struct be_softc *sc; 1537 struct mii_data *mii; 1538 int cmd; 1539 { 1540 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1541 int bmcr, bmsr; 1542 int error; 1543 1544 switch (cmd) { 1545 case MII_POLLSTAT: 1546 /* 1547 * If we're not polling our PHY instance, just return. 1548 */ 1549 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1550 return (0); 1551 1552 break; 1553 1554 case MII_MEDIACHG: 1555 1556 /* 1557 * If the media indicates a different PHY instance, 1558 * isolate ourselves. 1559 */ 1560 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1561 bmcr = be_mii_readreg((void *)sc, 1562 BE_PHY_INTERNAL, MII_BMCR); 1563 be_mii_writereg((void *)sc, 1564 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1565 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1566 sc->sc_intphy_curspeed = 0; 1567 return (0); 1568 } 1569 1570 1571 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1572 return (error); 1573 1574 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1575 1576 /* 1577 * Select the new mode and take out of isolation 1578 */ 1579 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1580 bmcr |= BMCR_S100; 1581 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1582 bmcr &= ~BMCR_S100; 1583 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1584 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1585 bmcr &= ~BMCR_S100; 1586 bmcr |= sc->sc_intphy_curspeed; 1587 } else { 1588 /* Keep isolated until link is up */ 1589 bmcr |= BMCR_ISO; 1590 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1591 } 1592 } 1593 1594 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1595 bmcr |= BMCR_FDX; 1596 else 1597 bmcr &= ~BMCR_FDX; 1598 1599 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1600 break; 1601 1602 case MII_TICK: 1603 /* 1604 * If we're not currently selected, just return. 1605 */ 1606 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1607 return (0); 1608 1609 /* Only used for automatic media selection */ 1610 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1611 return (0); 1612 1613 /* Is the interface even up? */ 1614 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1615 return (0); 1616 1617 /* 1618 * Check link status; if we don't have a link, try another 1619 * speed. We can't detect duplex mode, so half-duplex is 1620 * what we have to settle for. 1621 */ 1622 1623 /* Read twice in case the register is latched */ 1624 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) | 1625 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR); 1626 1627 if ((bmsr & BMSR_LINK) != 0) { 1628 /* We have a carrier */ 1629 bmcr = be_mii_readreg((void *)sc, 1630 BE_PHY_INTERNAL, MII_BMCR); 1631 1632 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1633 bmcr = be_mii_readreg((void *)sc, 1634 BE_PHY_INTERNAL, MII_BMCR); 1635 1636 sc->sc_mii_flags |= MIIF_HAVELINK; 1637 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1638 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1639 1640 bmcr &= ~BMCR_ISO; 1641 be_mii_writereg((void *)sc, 1642 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1643 1644 printf("%s: link up at %s Mbps\n", 1645 sc->sc_dev.dv_xname, 1646 (bmcr & BMCR_S100) ? "100" : "10"); 1647 } 1648 return (0); 1649 } 1650 1651 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1652 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1653 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1654 sc->sc_intphy_curspeed = 0; 1655 printf("%s: link down\n", sc->sc_dev.dv_xname); 1656 } 1657 1658 /* Only retry autonegotiation every 5 seconds. */ 1659 if (++sc->sc_mii_ticks < 5) 1660 return(0); 1661 1662 sc->sc_mii_ticks = 0; 1663 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1664 /* Just flip the fast speed bit */ 1665 bmcr ^= BMCR_S100; 1666 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1667 1668 break; 1669 1670 case MII_DOWN: 1671 /* Isolate this phy */ 1672 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1673 be_mii_writereg((void *)sc, 1674 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1675 return (0); 1676 } 1677 1678 /* Update the media status. */ 1679 be_intphy_status(sc); 1680 1681 /* Callback if something changed. */ 1682 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1683 (*mii->mii_statchg)((struct device *)sc); 1684 sc->sc_mii_active = mii->mii_media_active; 1685 } 1686 return (0); 1687 } 1688 1689 /* 1690 * Determine status of internal transceiver 1691 */ 1692 void 1693 be_intphy_status(sc) 1694 struct be_softc *sc; 1695 { 1696 struct mii_data *mii = &sc->sc_mii; 1697 int media_active, media_status; 1698 int bmcr, bmsr; 1699 1700 media_status = IFM_AVALID; 1701 media_active = 0; 1702 1703 /* 1704 * Internal transceiver; do the work here. 1705 */ 1706 bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1707 1708 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1709 case (BMCR_S100 | BMCR_FDX): 1710 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1711 break; 1712 case BMCR_S100: 1713 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1714 break; 1715 case BMCR_FDX: 1716 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1717 break; 1718 case 0: 1719 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1720 break; 1721 } 1722 1723 /* Read twice in case the register is latched */ 1724 bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1725 be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1726 if (bmsr & BMSR_LINK) 1727 media_status |= IFM_ACTIVE; 1728 1729 mii->mii_media_status = media_status; 1730 mii->mii_media_active = media_active; 1731 } 1732