1 /* $NetBSD: dbri.c,v 1.32 2011/01/11 00:49:50 macallan Exp $ */ 2 3 /* 4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de) 5 * Copyright (c) 1998, 1999 Brent Baccala (baccala@freesoft.org) 6 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill@netbsd.org> 7 * Copyright (c) 2005 Michael Lorenz <macallan@netbsd.org> 8 * All rights reserved. 9 * 10 * This driver is losely based on a Linux driver written by Rudolf Koenig and 11 * Brent Baccala who kindly gave their permission to use their code in a 12 * BSD-licensed driver. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.32 2011/01/11 00:49:50 macallan Exp $"); 38 39 #include "audio.h" 40 #if NAUDIO > 0 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/malloc.h> 47 #include <sys/proc.h> 48 #include <sys/kernel.h> 49 #include <sys/bus.h> 50 #include <sys/intr.h> 51 52 #include <dev/sbus/sbusvar.h> 53 #include <sparc/sparc/auxreg.h> 54 #include <machine/autoconf.h> 55 56 #include <sys/audioio.h> 57 #include <dev/audio_if.h> 58 #include <dev/auconv.h> 59 60 #include <dev/ic/cs4215reg.h> 61 #include <dev/ic/cs4215var.h> 62 #include <dev/sbus/dbrireg.h> 63 #include <dev/sbus/dbrivar.h> 64 65 #include "opt_sbus_dbri.h" 66 67 #define DBRI_ROM_NAME_PREFIX "SUNW,DBRI" 68 69 #ifdef DBRI_DEBUG 70 # define DPRINTF aprint_normal 71 #else 72 # define DPRINTF while (0) printf 73 #endif 74 75 static const char *dbri_supported[] = { 76 "e", 77 "s3", 78 "" 79 }; 80 81 enum ms { 82 CHImaster, 83 CHIslave 84 }; 85 86 enum io { 87 PIPEinput, 88 PIPEoutput 89 }; 90 91 /* 92 * Function prototypes 93 */ 94 95 /* softc stuff */ 96 static void dbri_attach_sbus(device_t, device_t, void *); 97 static int dbri_match_sbus(device_t, cfdata_t, void *); 98 99 static int dbri_config_interrupts(device_t); 100 101 /* interrupt handler */ 102 static int dbri_intr(void *); 103 static void dbri_softint(void *); 104 105 /* supporting subroutines */ 106 static int dbri_init(struct dbri_softc *); 107 static int dbri_reset(struct dbri_softc *); 108 static volatile uint32_t *dbri_command_lock(struct dbri_softc *); 109 static void dbri_command_send(struct dbri_softc *, volatile uint32_t *); 110 static void dbri_process_interrupt_buffer(struct dbri_softc *); 111 static void dbri_process_interrupt(struct dbri_softc *, int32_t); 112 113 /* mmcodec subroutines */ 114 static int mmcodec_init(struct dbri_softc *); 115 static void mmcodec_init_data(struct dbri_softc *); 116 static void mmcodec_pipe_init(struct dbri_softc *); 117 static void mmcodec_default(struct dbri_softc *); 118 static void mmcodec_setgain(struct dbri_softc *, int); 119 static int mmcodec_setcontrol(struct dbri_softc *); 120 121 /* chi subroutines */ 122 static void chi_reset(struct dbri_softc *, enum ms, int); 123 124 /* pipe subroutines */ 125 static void pipe_setup(struct dbri_softc *, int, int); 126 static void pipe_reset(struct dbri_softc *, int); 127 static void pipe_receive_fixed(struct dbri_softc *, int, 128 volatile uint32_t *); 129 static void pipe_transmit_fixed(struct dbri_softc *, int, uint32_t); 130 131 static void pipe_ts_link(struct dbri_softc *, int, enum io, int, int, int); 132 static int pipe_active(struct dbri_softc *, int); 133 134 /* audio(9) stuff */ 135 static int dbri_query_encoding(void *, struct audio_encoding *); 136 static int dbri_set_params(void *, int, int, struct audio_params *, 137 struct audio_params *,stream_filter_list_t *, stream_filter_list_t *); 138 static int dbri_round_blocksize(void *, int, int, const audio_params_t *); 139 static int dbri_halt_output(void *); 140 static int dbri_halt_input(void *); 141 static int dbri_getdev(void *, struct audio_device *); 142 static int dbri_set_port(void *, mixer_ctrl_t *); 143 static int dbri_get_port(void *, mixer_ctrl_t *); 144 static int dbri_query_devinfo(void *, mixer_devinfo_t *); 145 static size_t dbri_round_buffersize(void *, int, size_t); 146 static int dbri_get_props(void *); 147 static int dbri_open(void *, int); 148 static void dbri_close(void *); 149 150 static void setup_ring_xmit(struct dbri_softc *, int, int, int, int, 151 void (*)(void *), void *); 152 static void setup_ring_recv(struct dbri_softc *, int, int, int, int, 153 void (*)(void *), void *); 154 155 static int dbri_trigger_output(void *, void *, void *, int, 156 void (*)(void *), void *, const struct audio_params *); 157 static int dbri_trigger_input(void *, void *, void *, int, 158 void (*)(void *), void *, const struct audio_params *); 159 160 static void *dbri_malloc(void *, int, size_t, struct malloc_type *, int); 161 static void dbri_free(void *, void *, struct malloc_type *); 162 static paddr_t dbri_mappage(void *, void *, off_t, int); 163 static void dbri_set_power(struct dbri_softc *, int); 164 static void dbri_bring_up(struct dbri_softc *); 165 static bool dbri_suspend(device_t, const pmf_qual_t *); 166 static bool dbri_resume(device_t, const pmf_qual_t *); 167 168 /* stupid support routines */ 169 static uint32_t reverse_bytes(uint32_t, int); 170 171 struct audio_device dbri_device = { 172 "CS4215", 173 "", 174 "dbri" 175 }; 176 177 struct audio_hw_if dbri_hw_if = { 178 dbri_open, 179 dbri_close, 180 NULL, /* drain */ 181 dbri_query_encoding, 182 dbri_set_params, 183 dbri_round_blocksize, 184 NULL, /* commit_settings */ 185 NULL, /* init_output */ 186 NULL, /* init_input */ 187 NULL, /* start_output */ 188 NULL, /* start_input */ 189 dbri_halt_output, 190 dbri_halt_input, 191 NULL, /* speaker_ctl */ 192 dbri_getdev, 193 NULL, /* setfd */ 194 dbri_set_port, 195 dbri_get_port, 196 dbri_query_devinfo, 197 dbri_malloc, 198 dbri_free, 199 dbri_round_buffersize, 200 dbri_mappage, 201 dbri_get_props, 202 dbri_trigger_output, 203 dbri_trigger_input 204 }; 205 206 CFATTACH_DECL_NEW(dbri, sizeof(struct dbri_softc), 207 dbri_match_sbus, dbri_attach_sbus, NULL, NULL); 208 209 #define DBRI_NFORMATS 4 210 static const struct audio_format dbri_formats[DBRI_NFORMATS] = { 211 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_BE, 16, 16, 212 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 213 48000}}, 214 /* {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 215 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 216 48000}}, 217 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 218 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 219 48000}}, 220 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 221 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 222 48000}},*/ 223 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 224 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 225 48000}}, 226 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 227 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 228 48000}}, 229 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 230 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 231 48000}}, 232 }; 233 234 enum { 235 DBRI_OUTPUT_CLASS, 236 DBRI_VOL_OUTPUT, 237 DBRI_ENABLE_MONO, 238 DBRI_ENABLE_HEADPHONE, 239 DBRI_ENABLE_LINE, 240 DBRI_MONITOR_CLASS, 241 DBRI_VOL_MONITOR, 242 DBRI_INPUT_CLASS, 243 DBRI_INPUT_GAIN, 244 DBRI_INPUT_SELECT, 245 DBRI_RECORD_CLASS, 246 DBRI_ENUM_LAST 247 }; 248 249 /* 250 * Autoconfig routines 251 */ 252 static int 253 dbri_match_sbus(device_t parent, cfdata_t match, void *aux) 254 { 255 struct sbus_attach_args *sa = aux; 256 char *ver; 257 int i; 258 259 if (strncmp(DBRI_ROM_NAME_PREFIX, sa->sa_name, 9)) 260 return (0); 261 262 ver = &sa->sa_name[9]; 263 264 for (i = 0; dbri_supported[i][0] != '\0'; i++) 265 if (strcmp(dbri_supported[i], ver) == 0) 266 return (1); 267 268 return (0); 269 } 270 271 static void 272 dbri_attach_sbus(device_t parent, device_t self, void *aux) 273 { 274 struct dbri_softc *sc = device_private(self); 275 struct sbus_attach_args *sa = aux; 276 bus_space_handle_t ioh; 277 bus_size_t size; 278 int error, rseg, pwr, i; 279 char *ver = &sa->sa_name[9]; 280 281 sc->sc_dev = self; 282 sc->sc_iot = sa->sa_bustag; 283 sc->sc_dmat = sa->sa_dmatag; 284 sc->sc_powerstate = 1; 285 286 pwr = prom_getpropint(sa->sa_node,"pwr-on-auxio",0); 287 aprint_normal(": rev %s\n", ver); 288 289 if (pwr) { 290 /* 291 * we can control DBRI power via auxio and we're initially 292 * powered down 293 */ 294 295 sc->sc_have_powerctl = 1; 296 sc->sc_powerstate = 0; 297 dbri_set_power(sc, 1); 298 if (!pmf_device_register(self, dbri_suspend, dbri_resume)) { 299 aprint_error_dev(self, 300 "cannot set power mgmt handler\n"); 301 } 302 } else { 303 /* we can't control power so we're always up */ 304 sc->sc_have_powerctl = 0; 305 sc->sc_powerstate = 1; 306 } 307 308 for (i = 0; i < DBRI_NUM_DESCRIPTORS; i++) { 309 sc->sc_desc[i].softint = softint_establish(SOFTINT_SERIAL, 310 dbri_softint, &sc->sc_desc[i]); 311 } 312 313 if (sa->sa_npromvaddrs) 314 ioh = (bus_space_handle_t)sa->sa_promvaddrs[0]; 315 else { 316 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 317 sa->sa_offset, sa->sa_size, 318 BUS_SPACE_MAP_LINEAR, /*0,*/ &ioh) != 0) { 319 aprint_error("%s @ sbus: cannot map registers\n", 320 device_xname(self)); 321 return; 322 } 323 } 324 325 sc->sc_ioh = ioh; 326 327 size = sizeof(struct dbri_dma); 328 329 /* get a DMA handle */ 330 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 331 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 332 aprint_error_dev(self, "DMA map create error %d\n", 333 error); 334 return; 335 } 336 337 /* allocate DMA buffer */ 338 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &sc->sc_dmaseg, 339 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 340 aprint_error_dev(self, "DMA buffer alloc error %d\n", 341 error); 342 return; 343 } 344 345 /* map DMA buffer into CPU addressable space */ 346 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, rseg, size, 347 &sc->sc_membase, 348 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 349 aprint_error_dev(self, "DMA buffer map error %d\n", 350 error); 351 return; 352 } 353 354 /* load the buffer */ 355 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 356 sc->sc_membase, size, NULL, 357 BUS_DMA_NOWAIT)) != 0) { 358 aprint_error_dev(self, "DMA buffer map load error %d\n", 359 error); 360 bus_dmamem_unmap(sc->sc_dmat, sc->sc_membase, size); 361 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, rseg); 362 return; 363 } 364 365 /* map the registers into memory */ 366 367 /* kernel virtual address of DMA buffer */ 368 sc->sc_dma = (struct dbri_dma *)sc->sc_membase; 369 /* physical address of DMA buffer */ 370 sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 371 sc->sc_bufsiz = size; 372 373 bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_SCHED, dbri_intr, 374 sc); 375 376 sc->sc_locked = 0; 377 sc->sc_desc_used = 0; 378 sc->sc_refcount = 0; 379 sc->sc_playing = 0; 380 sc->sc_recording = 0; 381 sc->sc_init_done = 0; 382 config_finalize_register(self, &dbri_config_interrupts); 383 384 return; 385 } 386 387 /* 388 * lowlevel routine to switch power for the DBRI chip 389 */ 390 static void 391 dbri_set_power(struct dbri_softc *sc, int state) 392 { 393 int s; 394 395 if (sc->sc_have_powerctl == 0) 396 return; 397 if (sc->sc_powerstate == state) 398 return; 399 400 if (state) { 401 DPRINTF("%s: waiting to power up... ", 402 device_xname(sc->sc_dev)); 403 s = splhigh(); 404 *AUXIO4M_REG |= (AUXIO4M_MMX); 405 splx(s); 406 delay(10000); 407 DPRINTF("done (%02x)\n", *AUXIO4M_REG); 408 } else { 409 DPRINTF("%s: powering down\n", device_xname(sc->sc_dev)); 410 s = splhigh(); 411 *AUXIO4M_REG &= ~AUXIO4M_MMX; 412 splx(s); 413 DPRINTF("done (%02x})\n", *AUXIO4M_REG); 414 } 415 sc->sc_powerstate = state; 416 } 417 418 /* 419 * power up and re-initialize the chip 420 */ 421 static void 422 dbri_bring_up(struct dbri_softc *sc) 423 { 424 425 if (sc->sc_have_powerctl == 0) 426 return; 427 428 if (sc->sc_powerstate == 1) 429 return; 430 431 /* ok, we really need to do something */ 432 dbri_set_power(sc, 1); 433 434 /* 435 * re-initialize the chip but skip all the probing, don't overwrite 436 * any other settings either 437 */ 438 dbri_init(sc); 439 mmcodec_setgain(sc, 1); 440 mmcodec_pipe_init(sc); 441 mmcodec_init_data(sc); 442 mmcodec_setgain(sc, 0); 443 } 444 445 static int 446 dbri_config_interrupts(device_t dev) 447 { 448 struct dbri_softc *sc = device_private(dev); 449 450 if (sc->sc_init_done != 0) 451 return 0; 452 453 sc->sc_init_done = 1; 454 455 dbri_init(sc); 456 if (mmcodec_init(sc) == -1) { 457 printf("%s: no codec detected, aborting\n", 458 device_xname(dev)); 459 return 0; 460 } 461 462 /* Attach ourselves to the high level audio interface */ 463 audio_attach_mi(&dbri_hw_if, sc, sc->sc_dev); 464 465 /* power down until open() */ 466 dbri_set_power(sc, 0); 467 return 0; 468 } 469 470 static int 471 dbri_intr(void *hdl) 472 { 473 struct dbri_softc *sc = hdl; 474 bus_space_tag_t iot = sc->sc_iot; 475 bus_space_handle_t ioh = sc->sc_ioh; 476 int x; 477 478 /* clear interrupt */ 479 x = bus_space_read_4(iot, ioh, DBRI_REG1); 480 if (x & (DBRI_MRR | DBRI_MLE | DBRI_LBG | DBRI_MBE)) { 481 uint32_t tmp; 482 483 if (x & DBRI_MRR) 484 aprint_debug_dev(sc->sc_dev, 485 "multiple ack error on sbus\n"); 486 if (x & DBRI_MLE) 487 aprint_debug_dev(sc->sc_dev, 488 "multiple late error on sbus\n"); 489 if (x & DBRI_LBG) 490 aprint_debug_dev(sc->sc_dev, 491 "lost bus grant on sbus\n"); 492 if (x & DBRI_MBE) 493 aprint_debug_dev(sc->sc_dev, "burst error on sbus\n"); 494 495 /* 496 * Some of these errors disable the chip's circuitry. 497 * Re-enable the circuitry and keep on going. 498 */ 499 500 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 501 tmp &= ~(DBRI_DISABLE_MASTER); 502 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 503 } 504 505 #if 0 506 if (!x & 1) /* XXX: DBRI_INTR_REQ */ 507 return (1); 508 #endif 509 510 dbri_process_interrupt_buffer(sc); 511 512 return (1); 513 } 514 515 static void 516 dbri_softint(void *cookie) 517 { 518 struct dbri_desc *dd = cookie; 519 520 if (dd->callback != NULL) 521 dd->callback(dd->callback_args); 522 } 523 524 static int 525 dbri_init(struct dbri_softc *sc) 526 { 527 bus_space_tag_t iot = sc->sc_iot; 528 bus_space_handle_t ioh = sc->sc_ioh; 529 uint32_t reg; 530 volatile uint32_t *cmd; 531 bus_addr_t dmaaddr; 532 int n; 533 534 dbri_reset(sc); 535 536 cmd = dbri_command_lock(sc); 537 538 /* XXX: Initialize interrupt ring buffer */ 539 sc->sc_dma->intr[0] = (uint32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 540 sc->sc_irqp = 1; 541 542 /* Initialize pipes */ 543 for (n = 0; n < DBRI_PIPE_MAX; n++) 544 sc->sc_pipe[n].desc = sc->sc_pipe[n].next = -1; 545 546 for (n = 1; n < DBRI_INT_BLOCKS; n++) { 547 sc->sc_dma->intr[n] = 0; 548 } 549 550 /* Disable all SBus bursts */ 551 /* XXX 16 byte bursts cause errors, the rest works */ 552 reg = bus_space_read_4(iot, ioh, DBRI_REG0); 553 554 /*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/ 555 reg |= (DBRI_BURST_4 | DBRI_BURST_8); 556 bus_space_write_4(iot, ioh, DBRI_REG0, reg); 557 558 /* setup interrupt queue */ 559 dmaaddr = (uint32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 560 *(cmd++) = DBRI_CMD(DBRI_COMMAND_IIQ, 0, 0); 561 *(cmd++) = dmaaddr; 562 563 dbri_command_send(sc, cmd); 564 return (0); 565 } 566 567 static int 568 dbri_reset(struct dbri_softc *sc) 569 { 570 int bail = 0; 571 572 bus_space_tag_t iot = sc->sc_iot; 573 bus_space_handle_t ioh = sc->sc_ioh; 574 575 bus_space_write_4(iot, ioh, DBRI_REG0, DBRI_SOFT_RESET); 576 while ((bus_space_read_4(iot, ioh, DBRI_REG0) & DBRI_SOFT_RESET) && 577 (bail < 100000)) { 578 bail++; 579 delay(10); 580 } 581 if (bail == 100000) 582 aprint_error_dev(sc->sc_dev, "reset timed out\n"); 583 return (0); 584 } 585 586 static volatile uint32_t * 587 dbri_command_lock(struct dbri_softc *sc) 588 { 589 590 if (sc->sc_locked) 591 aprint_debug_dev(sc->sc_dev, "command buffer locked\n"); 592 593 sc->sc_locked++; 594 595 return (&sc->sc_dma->command[0]); 596 } 597 598 static void 599 dbri_command_send(struct dbri_softc *sc, volatile uint32_t *cmd) 600 { 601 bus_space_handle_t ioh = sc->sc_ioh; 602 bus_space_tag_t iot = sc->sc_iot; 603 int maxloops = 1000000; 604 int x; 605 606 x = splsched(); 607 608 sc->sc_locked--; 609 610 if (sc->sc_locked != 0) { 611 aprint_error_dev(sc->sc_dev, 612 "command buffer improperly locked\n"); 613 } else if ((cmd - &sc->sc_dma->command[0]) >= DBRI_NUM_COMMANDS - 1) { 614 aprint_error_dev(sc->sc_dev, "command buffer overflow\n"); 615 } else { 616 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 617 *(cmd++) = DBRI_CMD(DBRI_COMMAND_WAIT, 1, 0); 618 sc->sc_waitseen = 0; 619 bus_space_write_4(iot, ioh, DBRI_REG8, sc->sc_dmabase); 620 while ((--maxloops) > 0 && 621 (bus_space_read_4(iot, ioh, DBRI_REG0) 622 & DBRI_COMMAND_VALID)) { 623 bus_space_barrier(iot, ioh, DBRI_REG0, 4, 624 BUS_SPACE_BARRIER_READ); 625 delay(1000); 626 } 627 628 if (maxloops == 0) { 629 aprint_error_dev(sc->sc_dev, 630 "chip never completed command buffer\n"); 631 } else { 632 633 DPRINTF("%s: command completed\n", 634 device_xname(sc->sc_dev)); 635 636 while ((--maxloops) > 0 && (!sc->sc_waitseen)) 637 dbri_process_interrupt_buffer(sc); 638 if (maxloops == 0) { 639 aprint_error_dev(sc->sc_dev, "chip never acked WAIT\n"); 640 } 641 } 642 } 643 644 splx(x); 645 646 return; 647 } 648 649 static void 650 dbri_process_interrupt_buffer(struct dbri_softc *sc) 651 { 652 int32_t i; 653 654 while ((i = sc->sc_dma->intr[sc->sc_irqp]) != 0) { 655 sc->sc_dma->intr[sc->sc_irqp] = 0; 656 sc->sc_irqp++; 657 658 if (sc->sc_irqp == DBRI_INT_BLOCKS) 659 sc->sc_irqp = 1; 660 else if ((sc->sc_irqp & (DBRI_INT_BLOCKS - 1)) == 0) 661 sc->sc_irqp++; 662 663 dbri_process_interrupt(sc, i); 664 } 665 666 return; 667 } 668 669 static void 670 dbri_process_interrupt(struct dbri_softc *sc, int32_t i) 671 { 672 #if 0 673 const int liu_states[] = { 1, 0, 8, 3, 4, 5, 6, 7 }; 674 #endif 675 int val = DBRI_INTR_GETVAL(i); 676 int channel = DBRI_INTR_GETCHAN(i); 677 int command = DBRI_INTR_GETCMD(i); 678 int code = DBRI_INTR_GETCODE(i); 679 #if 0 680 int rval = DBRI_INTR_GETRVAL(i); 681 #endif 682 if (channel == DBRI_INTR_CMD && command == DBRI_COMMAND_WAIT) 683 sc->sc_waitseen++; 684 685 switch (code) { 686 case DBRI_INTR_XCMP: /* transmission complete */ 687 { 688 int td; 689 struct dbri_desc *dd; 690 691 td = sc->sc_pipe[channel].desc; 692 dd = &sc->sc_desc[td]; 693 694 if (dd->callback != NULL) 695 softint_schedule(dd->softint); 696 break; 697 } 698 case DBRI_INTR_FXDT: /* fixed data change */ 699 DPRINTF("dbri_intr: Fixed data change (%d: %x)\n", channel, 700 val); 701 #if 0 702 printf("reg: %08x\n", sc->sc_mm.status); 703 #endif 704 if (sc->sc_pipe[channel].sdp & DBRI_SDP_MSB) 705 val = reverse_bytes(val, sc->sc_pipe[channel].length); 706 if (sc->sc_pipe[channel].prec) 707 *(sc->sc_pipe[channel].prec) = val; 708 #ifndef DBRI_SPIN 709 DPRINTF("%s: wakeup %p\n", device_xname(sc->sc_dev), sc); 710 wakeup(sc); 711 #endif 712 break; 713 case DBRI_INTR_SBRI: 714 DPRINTF("dbri_intr: SBRI\n"); 715 break; 716 case DBRI_INTR_BRDY: 717 { 718 int td; 719 struct dbri_desc *dd; 720 721 td = sc->sc_pipe[channel].desc; 722 dd = &sc->sc_desc[td]; 723 724 if (dd->callback != NULL) 725 softint_schedule(dd->softint); 726 break; 727 } 728 case DBRI_INTR_UNDR: 729 { 730 volatile uint32_t *cmd; 731 int td = sc->sc_pipe[channel].desc; 732 733 DPRINTF("%s: DBRI_INTR_UNDR\n", device_xname(sc->sc_dev)); 734 735 sc->sc_dma->xmit[td].status = 0; 736 737 cmd = dbri_command_lock(sc); 738 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 739 sc->sc_pipe[channel].sdp | 740 DBRI_SDP_VALID_POINTER | 741 DBRI_SDP_CLEAR | 742 DBRI_SDP_2SAME); 743 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, td); 744 dbri_command_send(sc, cmd); 745 break; 746 } 747 case DBRI_INTR_CMDI: 748 DPRINTF("ok"); 749 break; 750 default: 751 752 aprint_error_dev(sc->sc_dev, "unknown interrupt code %d\n", 753 code); 754 break; 755 } 756 757 return; 758 } 759 760 /* 761 * mmcodec stuff 762 */ 763 764 static int 765 mmcodec_init(struct dbri_softc *sc) 766 { 767 bus_space_handle_t ioh = sc->sc_ioh; 768 bus_space_tag_t iot = sc->sc_iot; 769 uint32_t reg2; 770 int bail; 771 772 reg2 = bus_space_read_4(iot, ioh, DBRI_REG2); 773 DPRINTF("mmcodec_init: PIO reads %x\n", reg2); 774 775 if (reg2 & DBRI_PIO2) { 776 aprint_normal_dev(sc->sc_dev, " onboard CS4215 detected\n"); 777 sc->sc_mm.onboard = 1; 778 } 779 780 if (reg2 & DBRI_PIO0) { 781 aprint_normal_dev(sc->sc_dev, "speakerbox detected\n"); 782 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 783 sc->sc_mm.onboard = 0; 784 } 785 786 if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) { 787 aprint_normal_dev(sc->sc_dev, "using speakerbox\n"); 788 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 789 sc->sc_mm.onboard = 0; 790 } 791 792 if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) { 793 aprint_normal_dev(sc->sc_dev, "no mmcodec found\n"); 794 return -1; 795 } 796 797 sc->sc_version = 0xff; 798 799 mmcodec_pipe_init(sc); 800 mmcodec_default(sc); 801 802 sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8; 803 804 /* 805 * mmcodec_setcontrol() sometimes fails right after powerup 806 * so we just try again until we either get a useful response or run 807 * out of time 808 */ 809 bail = 0; 810 while (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) { 811 812 bail++; 813 if (bail > 100) { 814 DPRINTF("%s: cs4215 probe failed at offset %d\n", 815 device_xname(sc->sc_dev), sc->sc_mm.offset); 816 return (-1); 817 } 818 delay(10000); 819 } 820 821 aprint_normal_dev(sc->sc_dev, "cs4215 rev %c found at offset %d\n", 822 0x43 + (sc->sc_version & 0xf), sc->sc_mm.offset); 823 824 /* set some sane defaults for mmcodec_init_data */ 825 sc->sc_params.channels = 2; 826 sc->sc_params.precision = 16; 827 828 mmcodec_init_data(sc); 829 830 return (0); 831 } 832 833 static void 834 mmcodec_init_data(struct dbri_softc *sc) 835 { 836 bus_space_tag_t iot = sc->sc_iot; 837 bus_space_handle_t ioh = sc->sc_ioh; 838 uint32_t tmp; 839 int data_width; 840 841 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 842 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */ 843 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 844 845 /* switch CS4215 to data mode - set PIO3 to 1 */ 846 tmp = DBRI_PIO_ENABLE_ALL | DBRI_PIO1 | DBRI_PIO3; 847 848 /* XXX */ 849 tmp |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 850 851 bus_space_write_4(iot, ioh, DBRI_REG2, tmp); 852 chi_reset(sc, CHIslave, 128); 853 854 data_width = sc->sc_params.channels * sc->sc_params.precision; 855 856 if ((data_width != 32) && (data_width != 8)) 857 aprint_error("%s: data_width is %d\n", __func__, data_width); 858 859 pipe_ts_link(sc, 20, PIPEoutput, 16, 32, sc->sc_mm.offset + 32); 860 pipe_ts_link(sc, 4, PIPEoutput, 16, data_width, sc->sc_mm.offset); 861 pipe_ts_link(sc, 6, PIPEinput, 16, data_width, sc->sc_mm.offset); 862 pipe_ts_link(sc, 21, PIPEinput, 16, 32, sc->sc_mm.offset + 32); 863 864 pipe_receive_fixed(sc, 21, &sc->sc_mm.status); 865 866 mmcodec_setgain(sc, 0); 867 868 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 869 tmp |= DBRI_CHI_ACTIVATE; 870 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 871 872 return; 873 } 874 875 static void 876 mmcodec_pipe_init(struct dbri_softc *sc) 877 { 878 879 pipe_setup(sc, 4, DBRI_SDP_MEM | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 880 pipe_setup(sc, 20, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 881 pipe_setup(sc, 6, DBRI_SDP_MEM | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 882 pipe_setup(sc, 21, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 883 884 pipe_setup(sc, 17, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 885 pipe_setup(sc, 18, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 886 pipe_setup(sc, 19, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 887 888 sc->sc_mm.status = 0; 889 890 pipe_receive_fixed(sc, 18, &sc->sc_mm.status); 891 pipe_receive_fixed(sc, 19, &sc->sc_mm.version); 892 893 return; 894 } 895 896 static void 897 mmcodec_default(struct dbri_softc *sc) 898 { 899 struct cs4215_state *mm = &sc->sc_mm; 900 901 /* 902 * no action, memory resetting only 903 * 904 * data time slots 5-8 905 * speaker, line and headphone enable. set gain to half. 906 * input is line 907 */ 908 mm->d.bdata[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE; 909 mm->d.bdata[1] = sc->sc_ratt = 0x20 | CS4215_SE; 910 sc->sc_linp = 128; 911 sc->sc_rinp = 128; 912 sc->sc_monitor = 0; 913 sc->sc_input = 1; /* line */ 914 mm->d.bdata[2] = (CS4215_LG((sc->sc_linp >> 4)) & 0x0f) | 915 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 916 mm->d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4) & 0x0f)) | 917 CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f)); 918 919 920 /* 921 * control time slots 1-4 922 * 923 * 0: default I/O voltage scale 924 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 925 * 2: serial enable, CHI master, 128 bits per frame, clock 1 926 * 3: tests disabled 927 */ 928 mm->c.bcontrol[0] = CS4215_RSRVD_1 | CS4215_MLB; 929 mm->c.bcontrol[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 930 mm->c.bcontrol[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 931 mm->c.bcontrol[3] = 0; 932 933 return; 934 } 935 936 static void 937 mmcodec_setgain(struct dbri_softc *sc, int mute) 938 { 939 if (mute) { 940 /* disable all outputs, max. attenuation */ 941 sc->sc_mm.d.bdata[0] = sc->sc_latt | 63; 942 sc->sc_mm.d.bdata[1] = sc->sc_ratt | 63; 943 } else { 944 945 sc->sc_mm.d.bdata[0] = sc->sc_latt; 946 sc->sc_mm.d.bdata[1] = sc->sc_ratt; 947 } 948 949 /* input stuff */ 950 sc->sc_mm.d.bdata[2] = CS4215_LG((sc->sc_linp >> 4) & 0x0f) | 951 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 952 sc->sc_mm.d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4)) & 0x0f) | 953 (CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f))); 954 955 if (sc->sc_powerstate == 0) 956 return; 957 pipe_transmit_fixed(sc, 20, sc->sc_mm.d.ldata); 958 959 DPRINTF("mmcodec_setgain: %08x\n", sc->sc_mm.d.ldata); 960 /* give the chip some time to execute the command */ 961 delay(250); 962 963 return; 964 } 965 966 static int 967 mmcodec_setcontrol(struct dbri_softc *sc) 968 { 969 bus_space_tag_t iot = sc->sc_iot; 970 bus_space_handle_t ioh = sc->sc_ioh; 971 uint32_t val; 972 uint32_t tmp; 973 int bail = 0; 974 #if DBRI_SPIN 975 int i; 976 #endif 977 978 /* 979 * Temporarily mute outputs and wait 125 us to make sure that it 980 * happens. This avoids clicking noises. 981 */ 982 mmcodec_setgain(sc, 1); 983 delay(125); 984 985 bus_space_write_4(iot, ioh, DBRI_REG2, 0); 986 delay(125); 987 988 /* enable control mode */ 989 val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1; /* was PIO1 */ 990 991 /* XXX */ 992 val |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 993 994 bus_space_write_4(iot, ioh, DBRI_REG2, val); 995 996 delay(34); 997 998 /* 999 * in control mode, the cs4215 is the slave device, so the 1000 * DBRI must act as the CHI master. 1001 * 1002 * in data mode, the cs4215 must be the CHI master to insure 1003 * that the data stream is in sync with its codec 1004 */ 1005 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1006 tmp &= ~DBRI_COMMAND_CHI; 1007 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1008 1009 chi_reset(sc, CHImaster, 128); 1010 1011 /* control mode */ 1012 pipe_ts_link(sc, 17, PIPEoutput, 16, 32, sc->sc_mm.offset); 1013 pipe_ts_link(sc, 18, PIPEinput, 16, 8, sc->sc_mm.offset); 1014 pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48); 1015 1016 /* wait for the chip to echo back CLB as zero */ 1017 sc->sc_mm.c.bcontrol[0] &= ~CS4215_CLB; 1018 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1019 1020 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1021 tmp |= DBRI_CHI_ACTIVATE; 1022 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1023 1024 #if DBRI_SPIN 1025 i = 1024; 1026 while (((sc->sc_mm.status & 0xe4) != 0x20) && --i) { 1027 delay(125); 1028 } 1029 1030 if (i == 0) { 1031 DPRINTF("%s: cs4215 didn't respond to CLB (0x%02x)\n", 1032 device_xname(sc->sc_dev), sc->sc_mm.status); 1033 return (-1); 1034 } 1035 #else 1036 while (((sc->sc_mm.status & 0xe4) != 0x20) && (bail < 10)) { 1037 DPRINTF("%s: tsleep %p\n", device_xname(sc->sc_dev), sc); 1038 tsleep(sc, PCATCH | PZERO, "dbrifxdt", hz); 1039 bail++; 1040 } 1041 #endif 1042 if (bail >= 10) { 1043 DPRINTF("%s: switching to control mode timed out (%x %x)\n", 1044 device_xname(sc->sc_dev), sc->sc_mm.status, 1045 bus_space_read_4(iot, ioh, DBRI_REG2)); 1046 return -1; 1047 } 1048 1049 /* copy the version information before it becomes unreadable again */ 1050 sc->sc_version = sc->sc_mm.version; 1051 1052 /* terminate cs4215 control mode */ 1053 sc->sc_mm.c.bcontrol[0] |= CS4215_CLB; 1054 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1055 1056 /* two frames of control info @ 8kHz frame rate = 250us delay */ 1057 delay(250); 1058 1059 mmcodec_setgain(sc, 0); 1060 1061 return (0); 1062 1063 } 1064 1065 /* 1066 * CHI combo 1067 */ 1068 static void 1069 chi_reset(struct dbri_softc *sc, enum ms ms, int bpf) 1070 { 1071 volatile uint32_t *cmd; 1072 int val; 1073 int clockrate, divisor; 1074 1075 cmd = dbri_command_lock(sc); 1076 1077 /* set CHI anchor: pipe 16 */ 1078 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(16) | DBRI_PIPE(16); 1079 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1080 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1081 *(cmd++) = 0; 1082 1083 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(16) | DBRI_PIPE(16); 1084 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1085 *(cmd++) = 0; 1086 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1087 1088 sc->sc_pipe[16].sdp = 1; 1089 sc->sc_pipe[16].next = 16; 1090 sc->sc_chi_pipe_in = 16; 1091 sc->sc_chi_pipe_out = 16; 1092 1093 switch (ms) { 1094 case CHIslave: 1095 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, DBRI_CHI_CHICM(0)); 1096 break; 1097 case CHImaster: 1098 clockrate = bpf * 8; 1099 divisor = 12288 / clockrate; 1100 1101 if (divisor > 255 || divisor * clockrate != 12288) 1102 aprint_error_dev(sc->sc_dev, 1103 "illegal bits-per-frame %d\n", bpf); 1104 1105 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, 1106 DBRI_CHI_CHICM(divisor) | DBRI_CHI_FD | DBRI_CHI_BPF(bpf)); 1107 break; 1108 default: 1109 aprint_error_dev(sc->sc_dev, "unknown value for ms!\n"); 1110 break; 1111 } 1112 1113 sc->sc_chi_bpf = bpf; 1114 1115 /* CHI data mode */ 1116 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 1117 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDM, 0, 1118 DBRI_CDM_XCE | DBRI_CDM_XEN | DBRI_CDM_REN); 1119 1120 dbri_command_send(sc, cmd); 1121 1122 return; 1123 } 1124 1125 /* 1126 * pipe stuff 1127 */ 1128 static void 1129 pipe_setup(struct dbri_softc *sc, int pipe, int sdp) 1130 { 1131 DPRINTF("pipe setup: %d\n", pipe); 1132 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1133 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1134 pipe); 1135 return; 1136 } 1137 1138 if ((sdp & 0xf800) != sdp) 1139 aprint_error_dev(sc->sc_dev, "strange SDP value %d\n", 1140 sdp); 1141 1142 if (DBRI_SDP_MODE(sdp) == DBRI_SDP_FIXED && 1143 !(sdp & DBRI_SDP_TO_SER)) 1144 sdp |= DBRI_SDP_CHANGE; 1145 1146 sdp |= DBRI_PIPE(pipe); 1147 1148 sc->sc_pipe[pipe].sdp = sdp; 1149 sc->sc_pipe[pipe].desc = -1; 1150 1151 pipe_reset(sc, pipe); 1152 1153 return; 1154 } 1155 1156 static void 1157 pipe_reset(struct dbri_softc *sc, int pipe) 1158 { 1159 struct dbri_desc *dd; 1160 int sdp; 1161 int desc; 1162 volatile uint32_t *cmd; 1163 1164 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1165 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1166 pipe); 1167 return; 1168 } 1169 1170 sdp = sc->sc_pipe[pipe].sdp; 1171 if (sdp == 0) { 1172 aprint_error_dev(sc->sc_dev, "can not reset uninitialized pipe %d\n", 1173 pipe); 1174 return; 1175 } 1176 1177 cmd = dbri_command_lock(sc); 1178 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1179 sdp | DBRI_SDP_CLEAR | DBRI_SDP_VALID_POINTER); 1180 *(cmd++) = 0; 1181 dbri_command_send(sc, cmd); 1182 1183 desc = sc->sc_pipe[pipe].desc; 1184 1185 dd = &sc->sc_desc[desc]; 1186 1187 dd->busy = 0; 1188 1189 #if 0 1190 if (dd->callback) 1191 softint_schedule(dd->softint); 1192 #endif 1193 1194 sc->sc_pipe[pipe].desc = -1; 1195 1196 return; 1197 } 1198 1199 static void 1200 pipe_receive_fixed(struct dbri_softc *sc, int pipe, volatile uint32_t *prec) 1201 { 1202 1203 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1204 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1205 pipe); 1206 return; 1207 } 1208 1209 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1210 aprint_error_dev(sc->sc_dev, "non-fixed pipe %d\n", 1211 pipe); 1212 return; 1213 } 1214 1215 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER) { 1216 aprint_error_dev(sc->sc_dev, "can not receive on transmit pipe %d\b", 1217 pipe); 1218 return; 1219 } 1220 1221 sc->sc_pipe[pipe].prec = prec; 1222 1223 return; 1224 } 1225 1226 static void 1227 pipe_transmit_fixed(struct dbri_softc *sc, int pipe, uint32_t data) 1228 { 1229 volatile uint32_t *cmd; 1230 1231 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1232 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1233 pipe); 1234 return; 1235 } 1236 1237 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) == 0) { 1238 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1239 pipe); 1240 return; 1241 } 1242 1243 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1244 aprint_error_dev(sc->sc_dev, "non-fixed pipe %d\n", 1245 pipe); 1246 return; 1247 } 1248 1249 if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) { 1250 aprint_error_dev(sc->sc_dev, "called on receive pipe %d\n", 1251 pipe); 1252 return; 1253 } 1254 1255 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_MSB) 1256 data = reverse_bytes(data, sc->sc_pipe[pipe].length); 1257 1258 cmd = dbri_command_lock(sc); 1259 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SSP, 0, pipe); 1260 *(cmd++) = data; 1261 1262 dbri_command_send(sc, cmd); 1263 1264 return; 1265 } 1266 1267 static void 1268 setup_ring_xmit(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1269 void (*callback)(void *), void *callback_args) 1270 { 1271 volatile uint32_t *cmd; 1272 int x, i; 1273 int td; 1274 int td_first, td_last; 1275 bus_addr_t dmabuf, dmabase; 1276 struct dbri_desc *dd = &sc->sc_desc[which]; 1277 1278 switch (pipe) { 1279 case 4: 1280 /* output, offset 0 */ 1281 break; 1282 default: 1283 aprint_error("%s: illegal pipe number (%d)\n", 1284 __func__, pipe); 1285 return; 1286 } 1287 1288 td = 0; 1289 td_first = td_last = -1; 1290 1291 if (sc->sc_pipe[pipe].sdp == 0) { 1292 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1293 pipe); 1294 return; 1295 } 1296 1297 dmabuf = dd->dmabase; 1298 dmabase = sc->sc_dmabase; 1299 td = 0; 1300 1301 for (i = 0; i < (num - 1); i++) { 1302 1303 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) 1304 | TX_EOF | TX_BINT; 1305 sc->sc_dma->xmit[i].ba = dmabuf; 1306 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, i + 1); 1307 sc->sc_dma->xmit[i].status = 0; 1308 1309 td_last = td; 1310 dmabuf += blksz; 1311 } 1312 1313 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) | TX_EOF | TX_BINT; 1314 1315 sc->sc_dma->xmit[i].ba = dmabuf; 1316 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, 0); 1317 sc->sc_dma->xmit[i].status = 0; 1318 1319 dd->callback = callback; 1320 dd->callback_args = callback_args; 1321 1322 x = splsched(); 1323 1324 /* the pipe shouldn't be active */ 1325 if (pipe_active(sc, pipe)) { 1326 aprint_error("pipe active (CDP)\n"); 1327 /* pipe is already active */ 1328 #if 0 1329 td_last = sc->sc_pipe[pipe].desc; 1330 while (sc->sc_desc[td_last].next != -1) 1331 td_last = sc->sc_desc[td_last].next; 1332 1333 sc->sc_desc[td_last].next = td_first; 1334 sc->sc_dma->desc[td_last].nda = 1335 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1336 1337 cmd = dbri_command_lock(sc); 1338 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1339 dbri_command_send(sc, cmd); 1340 #endif 1341 } else { 1342 /* 1343 * pipe isn't active - issue an SDP command to start our 1344 * chain of TDs running 1345 */ 1346 sc->sc_pipe[pipe].desc = which; 1347 cmd = dbri_command_lock(sc); 1348 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1349 sc->sc_pipe[pipe].sdp | 1350 DBRI_SDP_VALID_POINTER | 1351 DBRI_SDP_EVERY | 1352 DBRI_SDP_CLEAR); 1353 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, 0); 1354 dbri_command_send(sc, cmd); 1355 DPRINTF("%s: starting DMA\n", __func__); 1356 } 1357 1358 splx(x); 1359 1360 return; 1361 } 1362 1363 static void 1364 setup_ring_recv(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1365 void (*callback)(void *), void *callback_args) 1366 { 1367 volatile uint32_t *cmd; 1368 int x, i; 1369 int td_first, td_last; 1370 bus_addr_t dmabuf, dmabase; 1371 struct dbri_desc *dd = &sc->sc_desc[which]; 1372 1373 switch (pipe) { 1374 case 6: 1375 break; 1376 default: 1377 aprint_error("%s: illegal pipe number (%d)\n", 1378 __func__, pipe); 1379 return; 1380 } 1381 1382 td_first = td_last = -1; 1383 1384 if (sc->sc_pipe[pipe].sdp == 0) { 1385 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1386 pipe); 1387 return; 1388 } 1389 1390 dmabuf = dd->dmabase; 1391 dmabase = sc->sc_dmabase; 1392 1393 for (i = 0; i < (num - 1); i++) { 1394 1395 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1396 sc->sc_dma->recv[i].ba = dmabuf; 1397 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, i + 1); 1398 sc->sc_dma->recv[i].status = RX_EOF; 1399 1400 td_last = i; 1401 dmabuf += blksz; 1402 } 1403 1404 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1405 1406 sc->sc_dma->recv[i].ba = dmabuf; 1407 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, 0); 1408 sc->sc_dma->recv[i].status = RX_EOF; 1409 1410 dd->callback = callback; 1411 dd->callback_args = callback_args; 1412 1413 x = splsched(); 1414 1415 /* the pipe shouldn't be active */ 1416 if (pipe_active(sc, pipe)) { 1417 aprint_error("pipe active (CDP)\n"); 1418 /* pipe is already active */ 1419 #if 0 1420 td_last = sc->sc_pipe[pipe].desc; 1421 while (sc->sc_desc[td_last].next != -1) 1422 td_last = sc->sc_desc[td_last].next; 1423 1424 sc->sc_desc[td_last].next = td_first; 1425 sc->sc_dma->desc[td_last].nda = 1426 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1427 1428 cmd = dbri_command_lock(sc); 1429 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1430 dbri_command_send(sc, cmd); 1431 #endif 1432 } else { 1433 /* 1434 * pipe isn't active - issue an SDP command to start our 1435 * chain of TDs running 1436 */ 1437 sc->sc_pipe[pipe].desc = which; 1438 cmd = dbri_command_lock(sc); 1439 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1440 sc->sc_pipe[pipe].sdp | 1441 DBRI_SDP_VALID_POINTER | 1442 DBRI_SDP_EVERY | 1443 DBRI_SDP_CLEAR); 1444 *(cmd++) = sc->sc_dmabase + dbri_dma_off(recv, 0); 1445 dbri_command_send(sc, cmd); 1446 DPRINTF("%s: starting DMA\n", __func__); 1447 } 1448 1449 splx(x); 1450 1451 return; 1452 } 1453 1454 static void 1455 pipe_ts_link(struct dbri_softc *sc, int pipe, enum io dir, int basepipe, 1456 int len, int cycle) 1457 { 1458 volatile uint32_t *cmd; 1459 int prevpipe, nextpipe; 1460 int val; 1461 1462 DPRINTF("%s: %d\n", __func__, pipe); 1463 if (pipe < 0 || pipe >= DBRI_PIPE_MAX || 1464 basepipe < 0 || basepipe >= DBRI_PIPE_MAX) { 1465 aprint_error_dev(sc->sc_dev, "illegal pipe numbers (%d, %d)\n", 1466 pipe, basepipe); 1467 return; 1468 } 1469 1470 if (sc->sc_pipe[pipe].sdp == 0 || sc->sc_pipe[basepipe].sdp == 0) { 1471 aprint_error_dev(sc->sc_dev, "uninitialized pipe (%d, %d)\n", 1472 pipe, basepipe); 1473 return; 1474 } 1475 1476 if (basepipe == 16 && dir == PIPEoutput && cycle == 0) 1477 cycle = sc->sc_chi_bpf; 1478 1479 if (basepipe == pipe) 1480 prevpipe = nextpipe = pipe; 1481 else { 1482 if (basepipe == 16) { 1483 if (dir == PIPEinput) { 1484 prevpipe = sc->sc_chi_pipe_in; 1485 } else { 1486 prevpipe = sc->sc_chi_pipe_out; 1487 } 1488 } else 1489 prevpipe = basepipe; 1490 1491 nextpipe = sc->sc_pipe[prevpipe].next; 1492 1493 while (sc->sc_pipe[nextpipe].cycle < cycle && 1494 sc->sc_pipe[nextpipe].next != basepipe) { 1495 prevpipe = nextpipe; 1496 nextpipe = sc->sc_pipe[nextpipe].next; 1497 } 1498 } 1499 1500 if (prevpipe == 16) { 1501 if (dir == PIPEinput) { 1502 sc->sc_chi_pipe_in = pipe; 1503 } else { 1504 sc->sc_chi_pipe_out = pipe; 1505 } 1506 } else 1507 sc->sc_pipe[prevpipe].next = pipe; 1508 1509 sc->sc_pipe[pipe].next = nextpipe; 1510 sc->sc_pipe[pipe].cycle = cycle; 1511 sc->sc_pipe[pipe].length = len; 1512 1513 cmd = dbri_command_lock(sc); 1514 1515 switch (dir) { 1516 case PIPEinput: 1517 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(prevpipe); 1518 val |= pipe; 1519 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1520 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1521 DBRI_TS_NEXT(nextpipe); 1522 *(cmd++) = 0; 1523 break; 1524 case PIPEoutput: 1525 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(prevpipe); 1526 val |= pipe; 1527 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1528 *(cmd++) = 0; 1529 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1530 DBRI_TS_NEXT(nextpipe); 1531 break; 1532 default: 1533 DPRINTF("%s: should not have happened!\n", 1534 device_xname(sc->sc_dev)); 1535 break; 1536 } 1537 1538 dbri_command_send(sc, cmd); 1539 1540 return; 1541 } 1542 1543 static int 1544 pipe_active(struct dbri_softc *sc, int pipe) 1545 { 1546 1547 return (sc->sc_pipe[pipe].desc != -1); 1548 } 1549 1550 /* 1551 * subroutines required to interface with audio(9) 1552 */ 1553 1554 static int 1555 dbri_query_encoding(void *hdl, struct audio_encoding *ae) 1556 { 1557 1558 switch (ae->index) { 1559 case 0: 1560 strcpy(ae->name, AudioEulinear); 1561 ae->encoding = AUDIO_ENCODING_ULINEAR; 1562 ae->precision = 8; 1563 ae->flags = 0; 1564 break; 1565 case 1: 1566 strcpy(ae->name, AudioEmulaw); 1567 ae->encoding = AUDIO_ENCODING_ULAW; 1568 ae->precision = 8; 1569 ae->flags = 0; 1570 break; 1571 case 2: 1572 strcpy(ae->name, AudioEalaw); 1573 ae->encoding = AUDIO_ENCODING_ALAW; 1574 ae->precision = 8; 1575 ae->flags = 0; 1576 break; 1577 case 3: 1578 strcpy(ae->name, AudioEslinear); 1579 ae->encoding = AUDIO_ENCODING_SLINEAR; 1580 ae->precision = 8; 1581 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1582 break; 1583 case 4: 1584 strcpy(ae->name, AudioEslinear_le); 1585 ae->encoding = AUDIO_ENCODING_SLINEAR_LE; 1586 ae->precision = 16; 1587 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1588 break; 1589 case 5: 1590 strcpy(ae->name, AudioEulinear_le); 1591 ae->encoding = AUDIO_ENCODING_ULINEAR_LE; 1592 ae->precision = 16; 1593 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1594 break; 1595 case 6: 1596 strcpy(ae->name, AudioEslinear_be); 1597 ae->encoding = AUDIO_ENCODING_SLINEAR_BE; 1598 ae->precision = 16; 1599 ae->flags = 0; 1600 break; 1601 case 7: 1602 strcpy(ae->name, AudioEulinear_be); 1603 ae->encoding = AUDIO_ENCODING_ULINEAR_BE; 1604 ae->precision = 16; 1605 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1606 break; 1607 case 8: 1608 strcpy(ae->name, AudioEslinear); 1609 ae->encoding = AUDIO_ENCODING_SLINEAR; 1610 ae->precision = 16; 1611 ae->flags = 0; 1612 break; 1613 default: 1614 return (EINVAL); 1615 } 1616 1617 return (0); 1618 } 1619 1620 static int 1621 dbri_set_params(void *hdl, int setmode, int usemode, 1622 struct audio_params *play, struct audio_params *rec, 1623 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 1624 { 1625 struct dbri_softc *sc = hdl; 1626 int rate; 1627 audio_params_t *p = NULL; 1628 stream_filter_list_t *fil; 1629 int mode; 1630 1631 /* 1632 * This device only has one clock, so make the sample rates match. 1633 */ 1634 if (play->sample_rate != rec->sample_rate && 1635 usemode == (AUMODE_PLAY | AUMODE_RECORD)) { 1636 if (setmode == AUMODE_PLAY) { 1637 rec->sample_rate = play->sample_rate; 1638 setmode |= AUMODE_RECORD; 1639 } else if (setmode == AUMODE_RECORD) { 1640 play->sample_rate = rec->sample_rate; 1641 setmode |= AUMODE_PLAY; 1642 } else 1643 return EINVAL; 1644 } 1645 1646 for (mode = AUMODE_RECORD; mode != -1; 1647 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 1648 if ((setmode & mode) == 0) 1649 continue; 1650 1651 p = mode == AUMODE_PLAY ? play : rec; 1652 if (p->sample_rate < 4000 || p->sample_rate > 50000) { 1653 DPRINTF("dbri_set_params: invalid rate %d\n", 1654 p->sample_rate); 1655 return EINVAL; 1656 } 1657 1658 fil = mode == AUMODE_PLAY ? pfil : rfil; 1659 DPRINTF("requested enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1660 p->sample_rate, p->precision, p->channels); 1661 if (auconv_set_converter(dbri_formats, DBRI_NFORMATS, 1662 mode, p, true, fil) < 0) { 1663 aprint_debug("dbri_set_params: auconv_set_converter failed\n"); 1664 return EINVAL; 1665 } 1666 if (fil->req_size > 0) 1667 p = &fil->filters[0].param; 1668 } 1669 1670 if (p == NULL) { 1671 DPRINTF("dbri_set_params: no parameters to set\n"); 1672 return 0; 1673 } 1674 1675 DPRINTF("native enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1676 p->sample_rate, p->precision, p->channels); 1677 1678 for (rate = 0; CS4215_FREQ[rate].freq; rate++) 1679 if (CS4215_FREQ[rate].freq == p->sample_rate) 1680 break; 1681 1682 if (CS4215_FREQ[rate].freq == 0) 1683 return (EINVAL); 1684 1685 /* set frequency */ 1686 sc->sc_mm.c.bcontrol[1] &= ~0x38; 1687 sc->sc_mm.c.bcontrol[1] |= CS4215_FREQ[rate].csval; 1688 sc->sc_mm.c.bcontrol[2] &= ~0x70; 1689 sc->sc_mm.c.bcontrol[2] |= CS4215_FREQ[rate].xtal; 1690 1691 switch (p->encoding) { 1692 case AUDIO_ENCODING_ULAW: 1693 sc->sc_mm.c.bcontrol[1] &= ~3; 1694 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ULAW; 1695 break; 1696 case AUDIO_ENCODING_ALAW: 1697 sc->sc_mm.c.bcontrol[1] &= ~3; 1698 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ALAW; 1699 break; 1700 case AUDIO_ENCODING_ULINEAR: 1701 sc->sc_mm.c.bcontrol[1] &= ~3; 1702 if (p->precision == 8) { 1703 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR8; 1704 } else { 1705 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1706 } 1707 break; 1708 case AUDIO_ENCODING_SLINEAR_BE: 1709 case AUDIO_ENCODING_SLINEAR: 1710 sc->sc_mm.c.bcontrol[1] &= ~3; 1711 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1712 break; 1713 } 1714 1715 switch (p->channels) { 1716 case 1: 1717 sc->sc_mm.c.bcontrol[1] &= ~CS4215_DFR_STEREO; 1718 break; 1719 case 2: 1720 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_STEREO; 1721 break; 1722 } 1723 1724 return (0); 1725 } 1726 1727 static int 1728 dbri_round_blocksize(void *hdl, int bs, int mode, 1729 const audio_params_t *param) 1730 { 1731 1732 /* DBRI DMA segment size, rounded down to 32bit alignment */ 1733 return 0x1ffc; 1734 } 1735 1736 static int 1737 dbri_halt_output(void *hdl) 1738 { 1739 struct dbri_softc *sc = hdl; 1740 1741 if (!sc->sc_playing) 1742 return 0; 1743 1744 sc->sc_playing = 0; 1745 pipe_reset(sc, 4); 1746 return (0); 1747 } 1748 1749 static int 1750 dbri_getdev(void *hdl, struct audio_device *ret) 1751 { 1752 1753 *ret = dbri_device; 1754 return (0); 1755 } 1756 1757 static int 1758 dbri_set_port(void *hdl, mixer_ctrl_t *mc) 1759 { 1760 struct dbri_softc *sc = hdl; 1761 int latt = sc->sc_latt, ratt = sc->sc_ratt; 1762 1763 switch (mc->dev) { 1764 case DBRI_VOL_OUTPUT: /* master volume */ 1765 latt = (latt & 0xc0) | (63 - 1766 min(mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> 2, 63)); 1767 ratt = (ratt & 0xc0) | (63 - 1768 min(mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] >> 2, 63)); 1769 break; 1770 case DBRI_ENABLE_MONO: /* built-in speaker */ 1771 if (mc->un.ord == 1) { 1772 ratt |= CS4215_SE; 1773 } else 1774 ratt &= ~CS4215_SE; 1775 break; 1776 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1777 if (mc->un.ord == 1) { 1778 latt |= CS4215_HE; 1779 } else 1780 latt &= ~CS4215_HE; 1781 break; 1782 case DBRI_ENABLE_LINE: /* line out */ 1783 if (mc->un.ord == 1) { 1784 latt |= CS4215_LE; 1785 } else 1786 latt &= ~CS4215_LE; 1787 break; 1788 case DBRI_VOL_MONITOR: 1789 if (mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] == 1790 sc->sc_monitor) 1791 return 0; 1792 sc->sc_monitor = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1793 break; 1794 case DBRI_INPUT_GAIN: 1795 sc->sc_linp = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1796 sc->sc_rinp = mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT]; 1797 break; 1798 case DBRI_INPUT_SELECT: 1799 if (mc->un.mask == sc->sc_input) 1800 return 0; 1801 sc->sc_input = mc->un.mask; 1802 break; 1803 } 1804 1805 sc->sc_latt = latt; 1806 sc->sc_ratt = ratt; 1807 1808 mmcodec_setgain(sc, 0); 1809 1810 return (0); 1811 } 1812 1813 static int 1814 dbri_get_port(void *hdl, mixer_ctrl_t *mc) 1815 { 1816 struct dbri_softc *sc = hdl; 1817 1818 switch (mc->dev) { 1819 case DBRI_VOL_OUTPUT: /* master volume */ 1820 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = 1821 (63 - (sc->sc_latt & 0x3f)) << 2; 1822 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = 1823 (63 - (sc->sc_ratt & 0x3f)) << 2; 1824 return (0); 1825 case DBRI_ENABLE_MONO: /* built-in speaker */ 1826 mc->un.ord = (sc->sc_ratt & CS4215_SE) ? 1 : 0; 1827 return 0; 1828 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1829 mc->un.ord = (sc->sc_latt & CS4215_HE) ? 1 : 0; 1830 return 0; 1831 case DBRI_ENABLE_LINE: /* line out */ 1832 mc->un.ord = (sc->sc_latt & CS4215_LE) ? 1 : 0; 1833 return 0; 1834 case DBRI_VOL_MONITOR: 1835 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_monitor; 1836 return 0; 1837 case DBRI_INPUT_GAIN: 1838 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_linp; 1839 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = sc->sc_rinp; 1840 return 0; 1841 case DBRI_INPUT_SELECT: 1842 mc->un.mask = sc->sc_input; 1843 return 0; 1844 } 1845 return (EINVAL); 1846 } 1847 1848 static int 1849 dbri_query_devinfo(void *hdl, mixer_devinfo_t *di) 1850 { 1851 1852 switch (di->index) { 1853 case DBRI_MONITOR_CLASS: 1854 di->mixer_class = DBRI_MONITOR_CLASS; 1855 strcpy(di->label.name, AudioCmonitor); 1856 di->type = AUDIO_MIXER_CLASS; 1857 di->next = di->prev = AUDIO_MIXER_LAST; 1858 return 0; 1859 case DBRI_OUTPUT_CLASS: 1860 di->mixer_class = DBRI_OUTPUT_CLASS; 1861 strcpy(di->label.name, AudioCoutputs); 1862 di->type = AUDIO_MIXER_CLASS; 1863 di->next = di->prev = AUDIO_MIXER_LAST; 1864 return 0; 1865 case DBRI_INPUT_CLASS: 1866 di->mixer_class = DBRI_INPUT_CLASS; 1867 strcpy(di->label.name, AudioCinputs); 1868 di->type = AUDIO_MIXER_CLASS; 1869 di->next = di->prev = AUDIO_MIXER_LAST; 1870 return 0; 1871 case DBRI_VOL_OUTPUT: /* master volume */ 1872 di->mixer_class = DBRI_OUTPUT_CLASS; 1873 di->next = di->prev = AUDIO_MIXER_LAST; 1874 strcpy(di->label.name, AudioNmaster); 1875 di->type = AUDIO_MIXER_VALUE; 1876 di->un.v.num_channels = 2; 1877 di->un.v.delta = 16; 1878 strcpy(di->un.v.units.name, AudioNvolume); 1879 return (0); 1880 case DBRI_INPUT_GAIN: /* input gain */ 1881 di->mixer_class = DBRI_INPUT_CLASS; 1882 di->next = di->prev = AUDIO_MIXER_LAST; 1883 strcpy(di->label.name, AudioNrecord); 1884 di->type = AUDIO_MIXER_VALUE; 1885 di->un.v.num_channels = 2; 1886 strcpy(di->un.v.units.name, AudioNvolume); 1887 return (0); 1888 case DBRI_VOL_MONITOR: /* monitor volume */ 1889 di->mixer_class = DBRI_MONITOR_CLASS; 1890 di->next = di->prev = AUDIO_MIXER_LAST; 1891 strcpy(di->label.name, AudioNmonitor); 1892 di->type = AUDIO_MIXER_VALUE; 1893 di->un.v.num_channels = 1; 1894 strcpy(di->un.v.units.name, AudioNvolume); 1895 return (0); 1896 case DBRI_ENABLE_MONO: /* built-in speaker */ 1897 di->mixer_class = DBRI_OUTPUT_CLASS; 1898 di->next = di->prev = AUDIO_MIXER_LAST; 1899 strcpy(di->label.name, AudioNmono); 1900 di->type = AUDIO_MIXER_ENUM; 1901 di->un.e.num_mem = 2; 1902 strcpy(di->un.e.member[0].label.name, AudioNoff); 1903 di->un.e.member[0].ord = 0; 1904 strcpy(di->un.e.member[1].label.name, AudioNon); 1905 di->un.e.member[1].ord = 1; 1906 return (0); 1907 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1908 di->mixer_class = DBRI_OUTPUT_CLASS; 1909 di->next = di->prev = AUDIO_MIXER_LAST; 1910 strcpy(di->label.name, AudioNheadphone); 1911 di->type = AUDIO_MIXER_ENUM; 1912 di->un.e.num_mem = 2; 1913 strcpy(di->un.e.member[0].label.name, AudioNoff); 1914 di->un.e.member[0].ord = 0; 1915 strcpy(di->un.e.member[1].label.name, AudioNon); 1916 di->un.e.member[1].ord = 1; 1917 return (0); 1918 case DBRI_ENABLE_LINE: /* line out */ 1919 di->mixer_class = DBRI_OUTPUT_CLASS; 1920 di->next = di->prev = AUDIO_MIXER_LAST; 1921 strcpy(di->label.name, AudioNline); 1922 di->type = AUDIO_MIXER_ENUM; 1923 di->un.e.num_mem = 2; 1924 strcpy(di->un.e.member[0].label.name, AudioNoff); 1925 di->un.e.member[0].ord = 0; 1926 strcpy(di->un.e.member[1].label.name, AudioNon); 1927 di->un.e.member[1].ord = 1; 1928 return (0); 1929 case DBRI_INPUT_SELECT: 1930 di->mixer_class = DBRI_INPUT_CLASS; 1931 strcpy(di->label.name, AudioNsource); 1932 di->type = AUDIO_MIXER_SET; 1933 di->prev = di->next = AUDIO_MIXER_LAST; 1934 di->un.s.num_mem = 2; 1935 strcpy(di->un.s.member[0].label.name, AudioNline); 1936 di->un.s.member[0].mask = 1 << 0; 1937 strcpy(di->un.s.member[1].label.name, AudioNmicrophone); 1938 di->un.s.member[1].mask = 1 << 1; 1939 return 0; 1940 } 1941 1942 return (ENXIO); 1943 } 1944 1945 static size_t 1946 dbri_round_buffersize(void *hdl, int dir, size_t bufsize) 1947 { 1948 #ifdef DBRI_BIG_BUFFER 1949 return 16*0x1ffc; /* use ~128KB buffer */ 1950 #else 1951 return bufsize; 1952 #endif 1953 } 1954 1955 static int 1956 dbri_get_props(void *hdl) 1957 { 1958 1959 return AUDIO_PROP_MMAP | AUDIO_PROP_FULLDUPLEX; 1960 } 1961 1962 static int 1963 dbri_trigger_output(void *hdl, void *start, void *end, int blksize, 1964 void (*intr)(void *), void *intrarg, 1965 const struct audio_params *param) 1966 { 1967 struct dbri_softc *sc = hdl; 1968 unsigned long count, num; 1969 1970 if (sc->sc_playing) 1971 return 0; 1972 1973 count = (unsigned long)(((char *)end - (char *)start)); 1974 num = count / blksize; 1975 1976 DPRINTF("trigger_output(%lx %lx) : %d %ld %ld\n", 1977 (unsigned long)intr, 1978 (unsigned long)intrarg, blksize, count, num); 1979 1980 sc->sc_params = *param; 1981 1982 if (sc->sc_recording == 0) { 1983 /* do not muck with the codec when it's already in use */ 1984 if (mmcodec_setcontrol(sc) != 0) 1985 return -1; 1986 mmcodec_init_data(sc); 1987 } 1988 1989 /* 1990 * always use DMA descriptor 0 for output 1991 * no need to allocate them dynamically since we only ever have 1992 * exactly one input stream and exactly one output stream 1993 */ 1994 setup_ring_xmit(sc, 4, 0, num, blksize, intr, intrarg); 1995 sc->sc_playing = 1; 1996 return 0; 1997 } 1998 1999 static int 2000 dbri_halt_input(void *cookie) 2001 { 2002 struct dbri_softc *sc = cookie; 2003 2004 if (!sc->sc_recording) 2005 return 0; 2006 2007 sc->sc_recording = 0; 2008 pipe_reset(sc, 6); 2009 return 0; 2010 } 2011 2012 static int 2013 dbri_trigger_input(void *hdl, void *start, void *end, int blksize, 2014 void (*intr)(void *), void *intrarg, 2015 const struct audio_params *param) 2016 { 2017 struct dbri_softc *sc = hdl; 2018 unsigned long count, num; 2019 2020 if (sc->sc_recording) 2021 return 0; 2022 2023 count = (unsigned long)(((char *)end - (char *)start)); 2024 num = count / blksize; 2025 2026 DPRINTF("trigger_input(%lx %lx) : %d %ld %ld\n", 2027 (unsigned long)intr, 2028 (unsigned long)intrarg, blksize, count, num); 2029 2030 sc->sc_params = *param; 2031 2032 if (sc->sc_playing == 0) { 2033 2034 /* 2035 * we don't support different parameters for playing and 2036 * recording anyway so don't bother whacking the codec if 2037 * it's already set up 2038 */ 2039 mmcodec_setcontrol(sc); 2040 mmcodec_init_data(sc); 2041 } 2042 2043 sc->sc_recording = 1; 2044 setup_ring_recv(sc, 6, 1, num, blksize, intr, intrarg); 2045 return 0; 2046 } 2047 2048 2049 static uint32_t 2050 reverse_bytes(uint32_t b, int len) 2051 { 2052 switch (len) { 2053 case 32: 2054 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 2055 case 16: 2056 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 2057 case 8: 2058 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 2059 case 4: 2060 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 2061 case 2: 2062 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 2063 case 1: 2064 case 0: 2065 break; 2066 default: 2067 DPRINTF("reverse_bytes: unsupported length\n"); 2068 }; 2069 2070 return (b); 2071 } 2072 2073 static void * 2074 dbri_malloc(void *v, int dir, size_t s, struct malloc_type *mt, int flags) 2075 { 2076 struct dbri_softc *sc = v; 2077 struct dbri_desc *dd = &sc->sc_desc[sc->sc_desc_used]; 2078 int rseg; 2079 2080 if (bus_dmamap_create(sc->sc_dmat, s, 1, s, 0, BUS_DMA_NOWAIT, 2081 &dd->dmamap) == 0) { 2082 if (bus_dmamem_alloc(sc->sc_dmat, s, 0, 0, &dd->dmaseg, 2083 1, &rseg, BUS_DMA_NOWAIT) == 0) { 2084 if (bus_dmamem_map(sc->sc_dmat, &dd->dmaseg, rseg, s, 2085 &dd->buf, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) == 0) { 2086 if (dd->buf != NULL) { 2087 if (bus_dmamap_load(sc->sc_dmat, 2088 dd->dmamap, dd->buf, s, NULL, 2089 BUS_DMA_NOWAIT) == 0) { 2090 dd->len = s; 2091 dd->busy = 0; 2092 dd->callback = NULL; 2093 dd->dmabase = 2094 dd->dmamap->dm_segs[0].ds_addr; 2095 DPRINTF("dbri_malloc: using buffer %d %08x\n", 2096 sc->sc_desc_used, (uint32_t)dd->buf); 2097 sc->sc_desc_used++; 2098 return dd->buf; 2099 } else 2100 aprint_error("dbri_malloc: load failed\n"); 2101 } else 2102 aprint_error("dbri_malloc: map returned NULL\n"); 2103 } else 2104 aprint_error("dbri_malloc: map failed\n"); 2105 bus_dmamem_free(sc->sc_dmat, &dd->dmaseg, rseg); 2106 } else 2107 aprint_error("dbri_malloc: malloc() failed\n"); 2108 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 2109 } else 2110 aprint_error("dbri_malloc: bus_dmamap_create() failed\n"); 2111 return NULL; 2112 } 2113 2114 static void 2115 dbri_free(void *v, void *p, struct malloc_type *mt) 2116 { 2117 struct dbri_softc *sc = v; 2118 struct dbri_desc *dd; 2119 int i; 2120 2121 for (i = 0; i < sc->sc_desc_used; i++) { 2122 dd = &sc->sc_desc[i]; 2123 if (dd->buf == p) 2124 break; 2125 } 2126 if (i >= sc->sc_desc_used) 2127 return; 2128 bus_dmamap_unload(sc->sc_dmat, dd->dmamap); 2129 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 2130 } 2131 2132 static paddr_t 2133 dbri_mappage(void *v, void *mem, off_t off, int prot) 2134 { 2135 struct dbri_softc *sc = v; 2136 int current; 2137 2138 if (off < 0) 2139 return -1; 2140 2141 current = 0; 2142 while ((current < sc->sc_desc_used) && 2143 (sc->sc_desc[current].buf != mem)) 2144 current++; 2145 2146 if (current < sc->sc_desc_used) { 2147 return bus_dmamem_mmap(sc->sc_dmat, 2148 &sc->sc_desc[current].dmaseg, 1, off, prot, BUS_DMA_WAITOK); 2149 } 2150 2151 return -1; 2152 } 2153 2154 static int 2155 dbri_open(void *cookie, int flags) 2156 { 2157 struct dbri_softc *sc = cookie; 2158 2159 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2160 2161 if (sc->sc_refcount == 0) 2162 dbri_bring_up(sc); 2163 2164 sc->sc_refcount++; 2165 2166 return 0; 2167 } 2168 2169 static void 2170 dbri_close(void *cookie) 2171 { 2172 struct dbri_softc *sc = cookie; 2173 2174 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2175 2176 sc->sc_refcount--; 2177 KASSERT(sc->sc_refcount >= 0); 2178 if (sc->sc_refcount > 0) 2179 return; 2180 2181 dbri_set_power(sc, 0); 2182 sc->sc_playing = 0; 2183 sc->sc_recording = 0; 2184 } 2185 2186 static bool 2187 dbri_suspend(device_t self, const pmf_qual_t *qual) 2188 { 2189 struct dbri_softc *sc = device_private(self); 2190 2191 dbri_set_power(sc, 0); 2192 return true; 2193 } 2194 2195 static bool 2196 dbri_resume(device_t self, const pmf_qual_t *qual) 2197 { 2198 struct dbri_softc *sc = device_private(self); 2199 2200 if (sc->sc_powerstate != 0) 2201 return true; 2202 aprint_verbose("resume: %d\n", sc->sc_refcount); 2203 if (sc->sc_playing) { 2204 volatile uint32_t *cmd; 2205 int s; 2206 2207 dbri_bring_up(sc); 2208 s = splsched(); 2209 cmd = dbri_command_lock(sc); 2210 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 2211 0, sc->sc_pipe[4].sdp | 2212 DBRI_SDP_VALID_POINTER | 2213 DBRI_SDP_EVERY | DBRI_SDP_CLEAR); 2214 *(cmd++) = sc->sc_dmabase + 2215 dbri_dma_off(xmit, 0); 2216 dbri_command_send(sc, cmd); 2217 splx(s); 2218 } 2219 return true; 2220 } 2221 2222 #endif /* NAUDIO > 0 */ 2223