1 /* $NetBSD: esp_sbus.c,v 1.20 2002/03/21 00:16:15 eeh Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: esp_sbus.c,v 1.20 2002/03/21 00:16:15 eeh Exp $"); 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 #include <sys/malloc.h> 48 49 #include <dev/scsipi/scsi_all.h> 50 #include <dev/scsipi/scsipi_all.h> 51 #include <dev/scsipi/scsiconf.h> 52 #include <dev/scsipi/scsi_message.h> 53 54 #include <machine/bus.h> 55 #include <machine/intr.h> 56 #include <machine/autoconf.h> 57 58 #include <dev/ic/lsi64854reg.h> 59 #include <dev/ic/lsi64854var.h> 60 61 #include <dev/ic/ncr53c9xreg.h> 62 #include <dev/ic/ncr53c9xvar.h> 63 64 #include <dev/sbus/sbusvar.h> 65 66 /* #define ESP_SBUS_DEBUG */ 67 68 struct esp_softc { 69 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 70 struct sbusdev sc_sd; /* sbus device */ 71 72 bus_space_tag_t sc_bustag; 73 bus_dma_tag_t sc_dmatag; 74 75 bus_space_handle_t sc_reg; /* the registers */ 76 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 77 78 int sc_pri; /* SBUS priority */ 79 }; 80 81 void espattach_sbus __P((struct device *, struct device *, void *)); 82 void espattach_dma __P((struct device *, struct device *, void *)); 83 int espmatch_sbus __P((struct device *, struct cfdata *, void *)); 84 85 86 /* Linkup to the rest of the kernel */ 87 struct cfattach esp_sbus_ca = { 88 sizeof(struct esp_softc), espmatch_sbus, espattach_sbus 89 }; 90 struct cfattach esp_dma_ca = { 91 sizeof(struct esp_softc), espmatch_sbus, espattach_dma 92 }; 93 94 /* 95 * Functions and the switch for the MI code. 96 */ 97 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 98 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 99 static u_char esp_rdreg1 __P((struct ncr53c9x_softc *, int)); 100 static void esp_wrreg1 __P((struct ncr53c9x_softc *, int, u_char)); 101 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 102 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 103 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 104 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 105 size_t *, int, size_t *)); 106 static void esp_dma_go __P((struct ncr53c9x_softc *)); 107 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 108 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 109 110 static struct ncr53c9x_glue esp_sbus_glue = { 111 esp_read_reg, 112 esp_write_reg, 113 esp_dma_isintr, 114 esp_dma_reset, 115 esp_dma_intr, 116 esp_dma_setup, 117 esp_dma_go, 118 esp_dma_stop, 119 esp_dma_isactive, 120 NULL, /* gl_clear_latched_intr */ 121 }; 122 123 static struct ncr53c9x_glue esp_sbus_glue1 = { 124 esp_rdreg1, 125 esp_wrreg1, 126 esp_dma_isintr, 127 esp_dma_reset, 128 esp_dma_intr, 129 esp_dma_setup, 130 esp_dma_go, 131 esp_dma_stop, 132 esp_dma_isactive, 133 NULL, /* gl_clear_latched_intr */ 134 }; 135 136 static void espattach __P((struct esp_softc *, struct ncr53c9x_glue *)); 137 138 int 139 espmatch_sbus(parent, cf, aux) 140 struct device *parent; 141 struct cfdata *cf; 142 void *aux; 143 { 144 int rv; 145 struct sbus_attach_args *sa = aux; 146 147 if (strcmp("SUNW,fas", sa->sa_name) == 0) 148 return 1; 149 150 rv = (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0 || 151 strcmp("ptscII", sa->sa_name) == 0); 152 return (rv); 153 } 154 155 void 156 espattach_sbus(parent, self, aux) 157 struct device *parent, *self; 158 void *aux; 159 { 160 struct esp_softc *esc = (void *)self; 161 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 162 struct sbus_attach_args *sa = aux; 163 struct lsi64854_softc *lsc; 164 int burst, sbusburst; 165 166 esc->sc_bustag = sa->sa_bustag; 167 esc->sc_dmatag = sa->sa_dmatag; 168 169 sc->sc_id = PROM_getpropint(sa->sa_node, "initiator-id", 7); 170 sc->sc_freq = PROM_getpropint(sa->sa_node, "clock-frequency", -1); 171 if (sc->sc_freq < 0) 172 sc->sc_freq = ((struct sbus_softc *) 173 sc->sc_dev.dv_parent)->sc_clockfreq; 174 175 #ifdef ESP_SBUS_DEBUG 176 printf("%s: espattach_sbus: sc_id %d, freq %d\n", 177 self->dv_xname, sc->sc_id, sc->sc_freq); 178 #endif 179 180 if (strcmp("SUNW,fas", sa->sa_name) == 0) { 181 182 /* 183 * fas has 2 register spaces: dma(lsi64854) and SCSI core (ncr53c9x) 184 */ 185 if (sa->sa_nreg != 2) { 186 printf("%s: %d register spaces\n", self->dv_xname, sa->sa_nreg); 187 return; 188 } 189 190 /* 191 * allocate space for dma, in SUNW,fas there are no separate 192 * dma device 193 */ 194 lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, M_NOWAIT); 195 196 if (lsc == NULL) { 197 printf("%s: out of memory (lsi64854_softc)\n", 198 self->dv_xname); 199 return; 200 } 201 esc->sc_dma = lsc; 202 203 lsc->sc_bustag = sa->sa_bustag; 204 lsc->sc_dmatag = sa->sa_dmatag; 205 206 bcopy(sc->sc_dev.dv_xname, lsc->sc_dev.dv_xname, 207 sizeof (lsc->sc_dev.dv_xname)); 208 209 /* Map dma registers */ 210 if (sa->sa_npromvaddrs) { 211 sbus_promaddr_to_handle(sa->sa_bustag, 212 sa->sa_promvaddrs[0], &lsc->sc_regs); 213 } else { 214 if (sbus_bus_map(sa->sa_bustag, 215 sa->sa_reg[0].sbr_slot, 216 sa->sa_reg[0].sbr_offset, 217 sa->sa_reg[0].sbr_size, 218 0, &lsc->sc_regs) != 0) { 219 printf("%s: cannot map dma registers\n", 220 self->dv_xname); 221 return; 222 } 223 } 224 225 /* 226 * XXX is this common(from bpp.c), the same in dma_sbus...etc. 227 * 228 * Get transfer burst size from PROM and plug it into the 229 * controller registers. This is needed on the Sun4m; do 230 * others need it too? 231 */ 232 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 233 if (sbusburst == 0) 234 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 235 236 burst = PROM_getpropint(sa->sa_node, "burst-sizes", -1); 237 238 #if ESP_SBUS_DEBUG 239 printf("espattach_sbus: burst 0x%x, sbus 0x%x\n", 240 burst, sbusburst); 241 #endif 242 243 if (burst == -1) 244 /* take SBus burst sizes */ 245 burst = sbusburst; 246 247 /* Clamp at parent's burst sizes */ 248 burst &= sbusburst; 249 lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 250 (burst & SBUS_BURST_16) ? 16 : 0; 251 252 lsc->sc_channel = L64854_CHANNEL_SCSI; 253 lsc->sc_client = sc; 254 255 lsi64854_attach(lsc); 256 257 /* 258 * map SCSI core registers 259 */ 260 if (sa->sa_npromvaddrs > 1) { 261 sbus_promaddr_to_handle(sa->sa_bustag, 262 sa->sa_promvaddrs[1], &esc->sc_reg); 263 } else { 264 if (sbus_bus_map(sa->sa_bustag, 265 sa->sa_reg[1].sbr_slot, 266 sa->sa_reg[1].sbr_offset, 267 sa->sa_reg[1].sbr_size, 268 0, &esc->sc_reg) != 0) { 269 printf("%s @ sbus: " 270 "cannot map scsi core registers\n", 271 self->dv_xname); 272 return; 273 } 274 } 275 276 if (sa->sa_nintr == 0) { 277 printf("\n%s: no interrupt property\n", self->dv_xname); 278 return; 279 } 280 281 esc->sc_pri = sa->sa_pri; 282 283 /* add me to the sbus structures */ 284 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 285 sbus_establish(&esc->sc_sd, &sc->sc_dev); 286 287 espattach(esc, &esp_sbus_glue); 288 289 return; 290 } 291 292 /* 293 * Find the DMA by poking around the dma device structures 294 * 295 * What happens here is that if the dma driver has not been 296 * configured, then this returns a NULL pointer. Then when the 297 * dma actually gets configured, it does the opposing test, and 298 * if the sc->sc_esp field in it's softc is NULL, then tries to 299 * find the matching esp driver. 300 */ 301 esc->sc_dma = (struct lsi64854_softc *) 302 getdevunit("dma", sc->sc_dev.dv_unit); 303 304 /* 305 * and a back pointer to us, for DMA 306 */ 307 if (esc->sc_dma) 308 esc->sc_dma->sc_client = sc; 309 else { 310 printf("\n"); 311 panic("espattach: no dma found"); 312 } 313 314 /* 315 * The `ESC' DMA chip must be reset before we can access 316 * the esp registers. 317 */ 318 if (esc->sc_dma->sc_rev == DMAREV_ESC) 319 DMA_RESET(esc->sc_dma); 320 321 /* 322 * Map my registers in, if they aren't already in virtual 323 * address space. 324 */ 325 if (sa->sa_npromvaddrs) { 326 sbus_promaddr_to_handle(sa->sa_bustag, 327 sa->sa_promvaddrs[0], &esc->sc_reg); 328 } else { 329 if (sbus_bus_map(sa->sa_bustag, 330 sa->sa_slot, sa->sa_offset, sa->sa_size, 331 0, &esc->sc_reg) != 0) { 332 printf("%s @ sbus: cannot map registers\n", 333 self->dv_xname); 334 return; 335 } 336 } 337 338 if (sa->sa_nintr == 0) { 339 /* 340 * No interrupt properties: we quit; this might 341 * happen on e.g. a Sparc X terminal. 342 */ 343 printf("\n%s: no interrupt property\n", self->dv_xname); 344 return; 345 } 346 347 esc->sc_pri = sa->sa_pri; 348 349 /* add me to the sbus structures */ 350 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 351 sbus_establish(&esc->sc_sd, &sc->sc_dev); 352 353 if (strcmp("ptscII", sa->sa_name) == 0) { 354 espattach(esc, &esp_sbus_glue1); 355 } else { 356 espattach(esc, &esp_sbus_glue); 357 } 358 } 359 360 void 361 espattach_dma(parent, self, aux) 362 struct device *parent, *self; 363 void *aux; 364 { 365 struct esp_softc *esc = (void *)self; 366 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 367 struct sbus_attach_args *sa = aux; 368 369 if (strcmp("ptscII", sa->sa_name) == 0) { 370 return; 371 } 372 373 esc->sc_bustag = sa->sa_bustag; 374 esc->sc_dmatag = sa->sa_dmatag; 375 376 sc->sc_id = PROM_getpropint(sa->sa_node, "initiator-id", 7); 377 sc->sc_freq = PROM_getpropint(sa->sa_node, "clock-frequency", -1); 378 379 esc->sc_dma = (struct lsi64854_softc *)parent; 380 esc->sc_dma->sc_client = sc; 381 382 /* 383 * Map my registers in, if they aren't already in virtual 384 * address space. 385 */ 386 if (sa->sa_npromvaddrs) { 387 sbus_promaddr_to_handle(sa->sa_bustag, 388 sa->sa_promvaddrs[0], &esc->sc_reg); 389 } else { 390 if (sbus_bus_map(sa->sa_bustag, 391 sa->sa_slot, sa->sa_offset, sa->sa_size, 392 0, &esc->sc_reg) != 0) { 393 printf("%s @ dma: cannot map registers\n", 394 self->dv_xname); 395 return; 396 } 397 } 398 399 if (sa->sa_nintr == 0) { 400 /* 401 * No interrupt properties: we quit; this might 402 * happen on e.g. a Sparc X terminal. 403 */ 404 printf("\n%s: no interrupt property\n", self->dv_xname); 405 return; 406 } 407 408 esc->sc_pri = sa->sa_pri; 409 410 /* Assume SBus is grandparent */ 411 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 412 sbus_establish(&esc->sc_sd, parent); 413 414 espattach(esc, &esp_sbus_glue); 415 } 416 417 418 /* 419 * Attach this instance, and then all the sub-devices 420 */ 421 void 422 espattach(esc, gluep) 423 struct esp_softc *esc; 424 struct ncr53c9x_glue *gluep; 425 { 426 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 427 void *icookie; 428 unsigned int uid = 0; 429 430 /* 431 * Set up glue for MI code early; we use some of it here. 432 */ 433 sc->sc_glue = gluep; 434 435 /* gimme Mhz */ 436 sc->sc_freq /= 1000000; 437 438 /* 439 * XXX More of this should be in ncr53c9x_attach(), but 440 * XXX should we really poke around the chip that much in 441 * XXX the MI code? Think about this more... 442 */ 443 444 /* 445 * It is necessary to try to load the 2nd config register here, 446 * to find out what rev the esp chip is, else the ncr53c9x_reset 447 * will not set up the defaults correctly. 448 */ 449 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 450 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 451 sc->sc_cfg3 = NCRCFG3_CDB; 452 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 453 454 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 455 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 456 sc->sc_rev = NCR_VARIANT_ESP100; 457 } else { 458 sc->sc_cfg2 = NCRCFG2_SCSI2; 459 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 460 sc->sc_cfg3 = 0; 461 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 462 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 463 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 464 if (NCR_READ_REG(sc, NCR_CFG3) != 465 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 466 sc->sc_rev = NCR_VARIANT_ESP100A; 467 } else { 468 /* NCRCFG2_FE enables > 64K transfers */ 469 sc->sc_cfg2 |= NCRCFG2_FE; 470 sc->sc_cfg3 = 0; 471 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 472 sc->sc_rev = NCR_VARIANT_ESP200; 473 474 /* XXX spec says it's valid after power up or chip reset */ 475 uid = NCR_READ_REG(sc, NCR_UID); 476 if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */ 477 sc->sc_rev = NCR_VARIANT_FAS366; 478 } 479 } 480 481 #ifdef ESP_SBUS_DEBUG 482 printf("espattach: revision %d, uid 0x%x\n", sc->sc_rev, uid); 483 #endif 484 485 /* 486 * XXX minsync and maxxfer _should_ be set up in MI code, 487 * XXX but it appears to have some dependency on what sort 488 * XXX of DMA we're hooked up to, etc. 489 */ 490 491 /* 492 * This is the value used to start sync negotiations 493 * Note that the NCR register "SYNCTP" is programmed 494 * in "clocks per byte", and has a minimum value of 4. 495 * The SCSI period used in negotiation is one-fourth 496 * of the time (in nanoseconds) needed to transfer one byte. 497 * Since the chip's clock is given in MHz, we have the following 498 * formula: 4 * period = (1000 / freq) * 4 499 */ 500 sc->sc_minsync = 1000 / sc->sc_freq; 501 502 /* 503 * Alas, we must now modify the value a bit, because it's 504 * only valid when can switch on FASTCLK and FASTSCSI bits 505 * in config register 3... 506 */ 507 switch (sc->sc_rev) { 508 case NCR_VARIANT_ESP100: 509 sc->sc_maxxfer = 64 * 1024; 510 sc->sc_minsync = 0; /* No synch on old chip? */ 511 break; 512 513 case NCR_VARIANT_ESP100A: 514 sc->sc_maxxfer = 64 * 1024; 515 /* Min clocks/byte is 5 */ 516 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 517 break; 518 519 case NCR_VARIANT_ESP200: 520 case NCR_VARIANT_FAS366: 521 sc->sc_maxxfer = 16 * 1024 * 1024; 522 /* XXX - do actually set FAST* bits */ 523 break; 524 } 525 526 /* Establish interrupt channel */ 527 icookie = bus_intr_establish(esc->sc_bustag, esc->sc_pri, IPL_BIO, 0, 528 ncr53c9x_intr, sc); 529 530 /* register interrupt stats */ 531 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 532 sc->sc_dev.dv_xname, "intr"); 533 534 /* Turn on target selection using the `dma' method */ 535 if (sc->sc_rev != NCR_VARIANT_FAS366) 536 sc->sc_features |= NCR_F_DMASELECT; 537 538 /* Do the common parts of attachment. */ 539 sc->sc_adapter.adapt_minphys = minphys; 540 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 541 ncr53c9x_attach(sc); 542 543 } 544 545 /* 546 * Glue functions. 547 */ 548 549 #ifdef ESP_SBUS_DEBUG 550 int esp_sbus_debug = 0; 551 552 static struct { 553 char *r_name; 554 int r_flag; 555 } esp__read_regnames [] = { 556 { "TCL", 0}, /* 0/00 */ 557 { "TCM", 0}, /* 1/04 */ 558 { "FIFO", 0}, /* 2/08 */ 559 { "CMD", 0}, /* 3/0c */ 560 { "STAT", 0}, /* 4/10 */ 561 { "INTR", 0}, /* 5/14 */ 562 { "STEP", 0}, /* 6/18 */ 563 { "FFLAGS", 1}, /* 7/1c */ 564 { "CFG1", 1}, /* 8/20 */ 565 { "STAT2", 0}, /* 9/24 */ 566 { "CFG4", 1}, /* a/28 */ 567 { "CFG2", 1}, /* b/2c */ 568 { "CFG3", 1}, /* c/30 */ 569 { "-none", 1}, /* d/34 */ 570 { "TCH", 1}, /* e/38 */ 571 { "TCX", 1}, /* f/3c */ 572 }; 573 574 static struct { 575 char *r_name; 576 int r_flag; 577 } esp__write_regnames[] = { 578 { "TCL", 1}, /* 0/00 */ 579 { "TCM", 1}, /* 1/04 */ 580 { "FIFO", 0}, /* 2/08 */ 581 { "CMD", 0}, /* 3/0c */ 582 { "SELID", 1}, /* 4/10 */ 583 { "TIMEOUT", 1}, /* 5/14 */ 584 { "SYNCTP", 1}, /* 6/18 */ 585 { "SYNCOFF", 1}, /* 7/1c */ 586 { "CFG1", 1}, /* 8/20 */ 587 { "CCF", 1}, /* 9/24 */ 588 { "TEST", 1}, /* a/28 */ 589 { "CFG2", 1}, /* b/2c */ 590 { "CFG3", 1}, /* c/30 */ 591 { "-none", 1}, /* d/34 */ 592 { "TCH", 1}, /* e/38 */ 593 { "TCX", 1}, /* f/3c */ 594 }; 595 #endif 596 597 u_char 598 esp_read_reg(sc, reg) 599 struct ncr53c9x_softc *sc; 600 int reg; 601 { 602 struct esp_softc *esc = (struct esp_softc *)sc; 603 u_char v; 604 605 v = bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4); 606 #ifdef ESP_SBUS_DEBUG 607 if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag) 608 printf("RD:%x <%s> %x\n", reg * 4, 609 ((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v); 610 #endif 611 return v; 612 } 613 614 void 615 esp_write_reg(sc, reg, v) 616 struct ncr53c9x_softc *sc; 617 int reg; 618 u_char v; 619 { 620 struct esp_softc *esc = (struct esp_softc *)sc; 621 622 #ifdef ESP_SBUS_DEBUG 623 if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag) 624 printf("WR:%x <%s> %x\n", reg * 4, 625 ((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v); 626 #endif 627 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 628 } 629 630 u_char 631 esp_rdreg1(sc, reg) 632 struct ncr53c9x_softc *sc; 633 int reg; 634 { 635 struct esp_softc *esc = (struct esp_softc *)sc; 636 637 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg)); 638 } 639 640 void 641 esp_wrreg1(sc, reg, v) 642 struct ncr53c9x_softc *sc; 643 int reg; 644 u_char v; 645 { 646 struct esp_softc *esc = (struct esp_softc *)sc; 647 648 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v); 649 } 650 651 int 652 esp_dma_isintr(sc) 653 struct ncr53c9x_softc *sc; 654 { 655 struct esp_softc *esc = (struct esp_softc *)sc; 656 657 return (DMA_ISINTR(esc->sc_dma)); 658 } 659 660 void 661 esp_dma_reset(sc) 662 struct ncr53c9x_softc *sc; 663 { 664 struct esp_softc *esc = (struct esp_softc *)sc; 665 666 DMA_RESET(esc->sc_dma); 667 } 668 669 int 670 esp_dma_intr(sc) 671 struct ncr53c9x_softc *sc; 672 { 673 struct esp_softc *esc = (struct esp_softc *)sc; 674 675 return (DMA_INTR(esc->sc_dma)); 676 } 677 678 int 679 esp_dma_setup(sc, addr, len, datain, dmasize) 680 struct ncr53c9x_softc *sc; 681 caddr_t *addr; 682 size_t *len; 683 int datain; 684 size_t *dmasize; 685 { 686 struct esp_softc *esc = (struct esp_softc *)sc; 687 688 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 689 } 690 691 void 692 esp_dma_go(sc) 693 struct ncr53c9x_softc *sc; 694 { 695 struct esp_softc *esc = (struct esp_softc *)sc; 696 697 DMA_GO(esc->sc_dma); 698 } 699 700 void 701 esp_dma_stop(sc) 702 struct ncr53c9x_softc *sc; 703 { 704 struct esp_softc *esc = (struct esp_softc *)sc; 705 u_int32_t csr; 706 707 csr = L64854_GCSR(esc->sc_dma); 708 csr &= ~D_EN_DMA; 709 L64854_SCSR(esc->sc_dma, csr); 710 } 711 712 int 713 esp_dma_isactive(sc) 714 struct ncr53c9x_softc *sc; 715 { 716 struct esp_softc *esc = (struct esp_softc *)sc; 717 718 return (DMA_ISACTIVE(esc->sc_dma)); 719 } 720 721 #include "opt_ddb.h" 722 #ifdef DDB 723 #include <machine/db_machdep.h> 724 #include <ddb/db_output.h> 725 726 void db_esp __P((db_expr_t, int, db_expr_t, char*)); 727 728 void 729 db_esp(addr, have_addr, count, modif) 730 db_expr_t addr; 731 int have_addr; 732 db_expr_t count; 733 char *modif; 734 { 735 struct ncr53c9x_softc *sc; 736 struct ncr53c9x_ecb *ecb; 737 struct ncr53c9x_linfo *li; 738 int u, t, i; 739 740 for (u=0; u<10; u++) { 741 sc = (struct ncr53c9x_softc *) 742 getdevunit("esp", u); 743 if (!sc) continue; 744 745 db_printf("esp%d: nexus %p phase %x prev %x dp %p dleft %lx ify %x\n", 746 u, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 747 sc->sc_dp, sc->sc_dleft, sc->sc_msgify); 748 db_printf("\tmsgout %x msgpriq %x msgin %x:%x:%x:%x:%x\n", 749 sc->sc_msgout, sc->sc_msgpriq, sc->sc_imess[0], 750 sc->sc_imess[1], sc->sc_imess[2], sc->sc_imess[3], 751 sc->sc_imess[0]); 752 db_printf("ready: "); 753 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 754 db_printf("ecb %p ", ecb); 755 if (ecb == ecb->chain.tqe_next) { 756 db_printf("\nWARNING: tailq loop on ecb %p", ecb); 757 break; 758 } 759 } 760 db_printf("\n"); 761 762 for (t=0; t<NCR_NTARG; t++) { 763 LIST_FOREACH(li, &sc->sc_tinfo[t].luns, link) { 764 db_printf("t%d lun %d untagged %p busy %d used %x\n", 765 t, (int)li->lun, li->untagged, li->busy, 766 li->used); 767 for (i=0; i<256; i++) 768 if ((ecb = li->queued[i])) { 769 db_printf("ecb %p tag %x\n", ecb, i); 770 } 771 } 772 } 773 } 774 } 775 #endif 776 777