1*d83e7ec9Smacallan /* $NetBSD: p9100reg.h,v 1.6 2012/09/21 01:07:44 macallan Exp $ */ 29efeaffaSmacallan 39efeaffaSmacallan /*- 49efeaffaSmacallan * Copyright (c) 1998 The NetBSD Foundation, Inc. 59efeaffaSmacallan * All rights reserved. 69efeaffaSmacallan * 79efeaffaSmacallan * This code is derived from software contributed to The NetBSD Foundation 89efeaffaSmacallan * by Matt Thomas. 99efeaffaSmacallan * 109efeaffaSmacallan * Redistribution and use in source and binary forms, with or without 119efeaffaSmacallan * modification, are permitted provided that the following conditions 129efeaffaSmacallan * are met: 139efeaffaSmacallan * 1. Redistributions of source code must retain the above copyright 149efeaffaSmacallan * notice, this list of conditions and the following disclaimer. 159efeaffaSmacallan * 2. Redistributions in binary form must reproduce the above copyright 169efeaffaSmacallan * notice, this list of conditions and the following disclaimer in the 179efeaffaSmacallan * documentation and/or other materials provided with the distribution. 189efeaffaSmacallan * 199efeaffaSmacallan * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 209efeaffaSmacallan * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 219efeaffaSmacallan * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 229efeaffaSmacallan * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 239efeaffaSmacallan * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 249efeaffaSmacallan * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 259efeaffaSmacallan * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 269efeaffaSmacallan * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 279efeaffaSmacallan * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 289efeaffaSmacallan * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 299efeaffaSmacallan * POSSIBILITY OF SUCH DAMAGE. 309efeaffaSmacallan */ 319efeaffaSmacallan 329efeaffaSmacallan 339efeaffaSmacallan #ifndef P9100_REG_H 349efeaffaSmacallan #define P9100_REG_H 359efeaffaSmacallan 369efeaffaSmacallan /* The Tadpole 3GX Technical Reference Manual lies. The ramdac registers 379efeaffaSmacallan * are map in 4 byte increments, not 8. 389efeaffaSmacallan */ 399efeaffaSmacallan #define SCRN_RPNT_CTL_1 0x0138 /* Screen Respaint Timing Control 1 */ 409efeaffaSmacallan #define VIDEO_ENABLED 0x00000020 419efeaffaSmacallan #define PWRUP_CNFG 0x0194 /* Power Up Configuration */ 429efeaffaSmacallan #define DAC_CMAP_WRIDX 0x0200 /* IBM RGB528 Palette Address (Write) */ 439efeaffaSmacallan #define DAC_CMAP_DATA 0x0204 /* IBM RGB528 Palette Data */ 449efeaffaSmacallan #define DAC_PXL_MASK 0x0208 /* IBM RGB528 Pixel Mask */ 459efeaffaSmacallan #define DAC_CMAP_RDIDX 0x020c /* IBM RGB528 Palette Address (Read) */ 469efeaffaSmacallan #define DAC_INDX_LO 0x0210 /* IBM RGB528 Index Low */ 479efeaffaSmacallan #define DAC_INDX_HI 0x0214 /* IBM RGB528 Index High */ 489efeaffaSmacallan #define DAC_INDX_DATA 0x0218 /* IBM RGB528 Index Data (Indexed Registers) */ 499efeaffaSmacallan #define DAC_INDX_CTL 0x021c /* IBM RGB528 Index Control */ 500ea32fbaSmacallan #define DAC_INDX_AUTOINCR 0x01 510ea32fbaSmacallan 528700623aSmacallan #define DAC_VERSION 0x01 53991219d6Smacallan #define DAC_MISC_CLK 0x02 54991219d6Smacallan #define DAC_POWER_MGT 0x05 558700623aSmacallan #define DAC_POWER_SCLK_DISABLE 0x10 568700623aSmacallan #define DAC_POWER_DDOT_DISABLE 0x08 578700623aSmacallan #define DAC_POWER_SYNC_DISABLE 0x04 588700623aSmacallan /* Disable internal DAC clock */ 598700623aSmacallan #define DAC_POWER_ICLK_DISABLE 0x02 608700623aSmacallan /* Disable internal DAC power */ 618700623aSmacallan #define DAC_POWER_IPWR_DISABLE 0x01 62991219d6Smacallan #define DAC_OPERATION 0x06 63991219d6Smacallan #define DAC_SYNC_ON_GREEN 0x08 64991219d6Smacallan #define DAC_PALETTE_CTRL 0x07 65991219d6Smacallan #define DAC_PIXEL_FMT 0x0a 66991219d6Smacallan #define DAC_8BIT_CTRL 0x0b 67991219d6Smacallan #define DAC8_DIRECT_COLOR 0x01 68991219d6Smacallan #define DAC_16BIT_CTRL 0x0c 69991219d6Smacallan #define DAC16_INDIRECT_COLOR 0x00 70991219d6Smacallan #define DAC16_DYNAMIC_COLOR 0x40 71991219d6Smacallan #define DAC16_DIRECT_COLOR 0xc0 72991219d6Smacallan #define DAC16_BYPASS_POLARITY 0x20 73991219d6Smacallan #define DAC16_BIT_FILL_LINEAR 0x04 74991219d6Smacallan #define DAC16_555 0x00 75991219d6Smacallan #define DAC16_565 0x02 76991219d6Smacallan #define DAC16_CONTIGUOUS 0x01 77991219d6Smacallan #define DAC_24BIT_CTRL 0x0d 78991219d6Smacallan #define DAC24_DIRECT_COLOR 0x01 79991219d6Smacallan #define DAC_32BIT_CTRL 0x0e 80991219d6Smacallan #define DAC32_BYPASS_POLARITY 0x04 81991219d6Smacallan #define DAC32_INDIRECT_COLOR 0x00 82991219d6Smacallan #define DAC32_DYNAMIC_COLOR 0x01 83991219d6Smacallan #define DAC32_DIRECT_COLOR 0x03 84991219d6Smacallan #define DAC_VCO_DIV 0x16 85991219d6Smacallan #define DAC_PLL0 0x20 86991219d6Smacallan #define DAC_MISC_1 0x70 87991219d6Smacallan #define DAC_MISC_2 0x71 88991219d6Smacallan #define DAC_MISC_3 0x72 898700623aSmacallan 900ea32fbaSmacallan #define DAC_CURSOR_CTL 0x30 910ea32fbaSmacallan #define DAC_CURSOR_OFF 0x00 920ea32fbaSmacallan #define DAC_CURSOR_WIN 0x02 930ea32fbaSmacallan #define DAC_CURSOR_X11 0x03 940ea32fbaSmacallan #define DAC_CURSOR_64 0x04 /* clear for 32x32 cursor */ 950ea32fbaSmacallan #define DAC_CURSOR_X 0x31 /* 8-low, 8-high */ 960ea32fbaSmacallan #define DAC_CURSOR_Y 0x33 /* 8-low, 8-high */ 970ea32fbaSmacallan #define DAC_CURSOR_HOT_X 0x35 /* hotspot */ 980ea32fbaSmacallan #define DAC_CURSOR_HOT_Y 0x36 990ea32fbaSmacallan #define DAC_CURSOR_COL_1 0x40 /* red. green and blue */ 1000ea32fbaSmacallan #define DAC_CURSOR_COL_2 0x43 1010ea32fbaSmacallan #define DAC_CURSOR_COL_3 0x46 1020ea32fbaSmacallan #define DAC_PIX_PLL 0x8e 1030ea32fbaSmacallan #define DAC_CURSOR_DATA 0x100 1049efeaffaSmacallan 105991219d6Smacallan /* main registers */ 106991219d6Smacallan #define SYS_CONF 0x0004 /* System Configuration Register */ 107991219d6Smacallan #define BUFFER_WRITE_1 0x0200 /* writes got o buffer 1 */ 108991219d6Smacallan #define BUFFER_WRITE_0 0x0000 /* writes go to buffer 0 */ 109991219d6Smacallan #define BUFFER_READ_1 0x0400 /* read from buffer 1 */ 110991219d6Smacallan #define BUFFER_READ_0 0x0000 111991219d6Smacallan #define MEM_SWAP_BITS 0x0800 /* swap bits when accessing VRAM */ 112991219d6Smacallan #define MEM_SWAP_BYTES 0x1000 /* swap bytes when accessing VRAM */ 113991219d6Smacallan #define MEM_SWAP_HWORDS 0x2000 /* swap halfwords when accessing VRAM */ 114991219d6Smacallan #define SHIFT_0 14 115991219d6Smacallan #define SHIFT_1 17 116991219d6Smacallan #define SHIFT_2 20 117991219d6Smacallan #define SHIFT_3 29 118991219d6Smacallan #define PIXEL_SHIFT 26 119991219d6Smacallan #define SWAP_SHIFT 11 120991219d6Smacallan /* this is what the 3GX manual says */ 121991219d6Smacallan #define SC_8BIT 2 122991219d6Smacallan #define SC_16BIT 3 123991219d6Smacallan #define SC_24BIT 7 124991219d6Smacallan #define SC_32BIT 5 125991219d6Smacallan 126991219d6Smacallan /* video controller registers */ 127991219d6Smacallan #define VID_HCOUNTER 0x104 128991219d6Smacallan #define VID_HTOTAL 0x108 129991219d6Smacallan #define VID_HSRE 0x10c /* hsync raising edge */ 130991219d6Smacallan #define VID_HBRE 0x110 /* hblank raising edge */ 131991219d6Smacallan #define VID_HBFE 0x114 /* hblank falling edge */ 132991219d6Smacallan #define VID_HCNTPRLD 0x118 /* hcounter preload */ 133991219d6Smacallan #define VID_VCOUNTER 0x11c /* vcounter */ 134991219d6Smacallan #define VID_VLENGTH 0x120 /* lines, including blanks */ 135991219d6Smacallan #define VID_VSRE 0x124 /* vsync raising edge */ 136991219d6Smacallan #define VID_VBRE 0x128 /* vblank raising edge */ 137991219d6Smacallan #define VID_VBFE 0x12c /* vblank falling edge */ 138991219d6Smacallan #define VID_VCNTPRLD 0x130 /* vcounter preload */ 139991219d6Smacallan #define VID_SRADDR 0x134 /* screen repaint address */ 140991219d6Smacallan #define VID_SRTC 0x138 /* screen repaint timing control */ 141991219d6Smacallan #define VID_QSFCNTR 0x13c /* QSF counter */ 142991219d6Smacallan 143991219d6Smacallan #define VID_MEM_CONFIG 0x184 /* memory config */ 144991219d6Smacallan #define VID_RFPERIOD 0x188 /* refresh period */ 145991219d6Smacallan #define VID_RFCOUNT 0x18c /* refresh counter */ 146991219d6Smacallan #define VID_RLMAX 0x190 /* RAS low max */ 147991219d6Smacallan #define VID_RLCUR 0x194 /* RAS low current */ 148991219d6Smacallan #define VID_DACSYNC 0x198 /* read after last DAC access */ 149991219d6Smacallan 1509efeaffaSmacallan #define ENGINE_STATUS 0x2000 /* drawing engine status register */ 1519efeaffaSmacallan #define BLITTER_BUSY 0x80000000 1529efeaffaSmacallan #define ENGINE_BUSY 0x40000000 1539efeaffaSmacallan #define COMMAND_BLIT 0x2004 1549efeaffaSmacallan #define COMMAND_QUAD 0x2008 155*d83e7ec9Smacallan #define COMMAND_PIXEL8 0x200c 1560ea32fbaSmacallan /* pixel data for monochrome colour expansion */ 1570ea32fbaSmacallan #define PIXEL_1 0x2080 1589efeaffaSmacallan /* apparently bits 2-6 control how many pixels we write - n+1 */ 1599efeaffaSmacallan 1609efeaffaSmacallan /* drawing engine registers */ 1619efeaffaSmacallan #define COORD_INDEX 0x218c 1629efeaffaSmacallan #define WINDOW_OFFSET 0x2190 1639efeaffaSmacallan 1649efeaffaSmacallan #define FOREGROUND_COLOR 0x2200 1659efeaffaSmacallan #define BACKGROUND_COLOR 0x2204 1669efeaffaSmacallan #define PLANE_MASK 0x2208 1679efeaffaSmacallan #define DRAW_MODE 0x220c 1689efeaffaSmacallan #define PATTERN_ORIGIN_X 0x2210 1699efeaffaSmacallan #define PATTERN_ORIGIN_Y 0x2214 1709efeaffaSmacallan #define RASTER_OP 0x2218 1719efeaffaSmacallan #define ROP_NO_SOLID 0x02000 /* if set use pattern instead of color for quad operations */ 1729efeaffaSmacallan #define ROP_2BIT_PATTERN 0x04000 /* 4-colour pattern instead of mono */ 1739efeaffaSmacallan #define ROP_PIX1_TRANS 0x08000 /* transparent background in mono */ 1749efeaffaSmacallan #define ROP_OVERSIZE 0x10000 1759efeaffaSmacallan #define ROP_PATTERN 0x20000 /* the manual says pattern enable */ 1769efeaffaSmacallan #define ROP_TRANS 0x20000 /* but XFree86 says trans */ 1779efeaffaSmacallan #define ROP_SRC 0xCC 1789efeaffaSmacallan #define ROP_PAT 0xF0 1799efeaffaSmacallan #define ROP_DST 0xAA 1809efeaffaSmacallan #define ROP_SET 0xff 1819efeaffaSmacallan 1829efeaffaSmacallan #define PIXEL_8 0x221c 1839efeaffaSmacallan #define WINDOW_MIN 0x2220 1849efeaffaSmacallan #define WINDOW_MAX 0x2224 1859efeaffaSmacallan 1869efeaffaSmacallan #define PATTERN0 0x2280 1879efeaffaSmacallan #define PATTERN1 0x2284 1889efeaffaSmacallan #define PATTERN2 0x2288 1899efeaffaSmacallan #define PATTERN3 0x228c 1909efeaffaSmacallan #define USER0 0x2290 1919efeaffaSmacallan #define USER1 0x2294 1929efeaffaSmacallan #define USER2 0x2298 1939efeaffaSmacallan #define USER3 0x229c 1949efeaffaSmacallan #define BYTE_CLIP_MIN 0x22a0 1959efeaffaSmacallan #define BYTE_CLIP_MAX 0x22a4 1969efeaffaSmacallan 1979efeaffaSmacallan /* coordinate registers */ 1989efeaffaSmacallan #define ABS_X0 0x3008 1999efeaffaSmacallan #define ABS_Y0 0x3010 2009efeaffaSmacallan #define ABS_XY0 0x3018 2019efeaffaSmacallan #define REL_X0 0x3028 2029efeaffaSmacallan #define REL_Y0 0x3030 2039efeaffaSmacallan #define REL_XY0 0x3038 2049efeaffaSmacallan 2059efeaffaSmacallan #define ABS_X1 0x3048 2069efeaffaSmacallan #define ABS_Y1 0x3050 2079efeaffaSmacallan #define ABS_XY1 0x3058 2089efeaffaSmacallan #define REL_X1 0x3068 2099efeaffaSmacallan #define REL_Y1 0x3070 2109efeaffaSmacallan #define REL_XY1 0x3078 2119efeaffaSmacallan 2129efeaffaSmacallan #define ABS_X2 0x3088 2139efeaffaSmacallan #define ABS_Y2 0x3090 2149efeaffaSmacallan #define ABS_XY2 0x3098 2159efeaffaSmacallan #define REL_X2 0x30a8 2169efeaffaSmacallan #define REL_Y2 0x30b0 2179efeaffaSmacallan #define REL_XY2 0x30b8 2189efeaffaSmacallan 2199efeaffaSmacallan #define ABS_X3 0x30c8 2209efeaffaSmacallan #define ABS_Y3 0x30d0 2219efeaffaSmacallan #define ABS_XY3 0x30d8 2229efeaffaSmacallan #define REL_X3 0x30e8 2239efeaffaSmacallan #define REL_Y3 0x30f0 2249efeaffaSmacallan #define REL_XY3 0x30f8 2259efeaffaSmacallan 2269efeaffaSmacallan /* meta-coordinates */ 2279efeaffaSmacallan #define POINT_RTW_X 0x3208 2289efeaffaSmacallan #define POINT_RTW_Y 0x3210 2299efeaffaSmacallan #define POINT_RTW_XY 0x3218 2309efeaffaSmacallan #define POINT_RTP_X 0x3228 2319efeaffaSmacallan #define POINT_RTP_Y 0x3220 2329efeaffaSmacallan #define POINT_RTP_XY 0x3238 2339efeaffaSmacallan 2349efeaffaSmacallan #define LINE_RTW_X 0x3248 2359efeaffaSmacallan #define LINE_RTW_Y 0x3250 2369efeaffaSmacallan #define LINE_RTW_XY 0x3258 2379efeaffaSmacallan #define LINE_RTP_X 0x3268 2389efeaffaSmacallan #define LINE_RTP_Y 0x3260 2399efeaffaSmacallan #define LINE_RTP_XY 0x3278 2409efeaffaSmacallan 2419efeaffaSmacallan #define TRIANGLE_RTW_X 0x3288 2429efeaffaSmacallan #define TRIANGLE_RTW_Y 0x3290 2439efeaffaSmacallan #define TRIANGLE_RTW_XY 0x3298 2449efeaffaSmacallan #define TRIANGLE_RTP_X 0x32a8 2459efeaffaSmacallan #define TRIANGLE_RTP_Y 0x32a0 2469efeaffaSmacallan #define TRIANGLE_RTP_XY 0x32b8 2479efeaffaSmacallan 2489efeaffaSmacallan #define QUAD_RTW_X 0x32c8 2499efeaffaSmacallan #define QUAD_RTW_Y 0x32d0 2509efeaffaSmacallan #define QUAD_RTW_XY 0x32d8 2519efeaffaSmacallan #define QUAD_RTP_X 0x32e8 2529efeaffaSmacallan #define QUAD_RTP_Y 0x32e0 2539efeaffaSmacallan #define QUAD_RTP_XY 0x32f8 2549efeaffaSmacallan 2559efeaffaSmacallan #define RECT_RTW_X 0x3308 2569efeaffaSmacallan #define RECT_RTW_Y 0x3310 2579efeaffaSmacallan #define RECT_RTW_XY 0x3318 2589efeaffaSmacallan #define RECT_RTP_X 0x3328 2599efeaffaSmacallan #define RECT_RTP_Y 0x3320 2609efeaffaSmacallan #define RECT_RTP_XY 0x3338 2619efeaffaSmacallan 2629efeaffaSmacallan #endif 263