1*579b9cbdStsutsui /* $NetBSD: qereg.h,v 1.7 2009/09/19 11:53:42 tsutsui Exp $ */ 25e8fcd94Spk 35e8fcd94Spk /*- 45e8fcd94Spk * Copyright (c) 1999 The NetBSD Foundation, Inc. 55e8fcd94Spk * All rights reserved. 65e8fcd94Spk * 75e8fcd94Spk * This code is derived from software contributed to The NetBSD Foundation 85e8fcd94Spk * by Paul Kranenburg. 95e8fcd94Spk * 105e8fcd94Spk * Redistribution and use in source and binary forms, with or without 115e8fcd94Spk * modification, are permitted provided that the following conditions 125e8fcd94Spk * are met: 135e8fcd94Spk * 1. Redistributions of source code must retain the above copyright 145e8fcd94Spk * notice, this list of conditions and the following disclaimer. 155e8fcd94Spk * 2. Redistributions in binary form must reproduce the above copyright 165e8fcd94Spk * notice, this list of conditions and the following disclaimer in the 175e8fcd94Spk * documentation and/or other materials provided with the distribution. 185e8fcd94Spk * 195e8fcd94Spk * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 205e8fcd94Spk * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 215e8fcd94Spk * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 225e8fcd94Spk * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 235e8fcd94Spk * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 245e8fcd94Spk * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 255e8fcd94Spk * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 265e8fcd94Spk * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 275e8fcd94Spk * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 285e8fcd94Spk * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 295e8fcd94Spk * POSSIBILITY OF SUCH DAMAGE. 305e8fcd94Spk */ 315e8fcd94Spk 325e8fcd94Spk /* 335e8fcd94Spk * Copyright (c) 1998 Jason L. Wright. 345e8fcd94Spk * All rights reserved. 355e8fcd94Spk * 365e8fcd94Spk * Redistribution and use in source and binary forms, with or without 375e8fcd94Spk * modification, are permitted provided that the following conditions 385e8fcd94Spk * are met: 395e8fcd94Spk * 1. Redistributions of source code must retain the above copyright 405e8fcd94Spk * notice, this list of conditions and the following disclaimer. 415e8fcd94Spk * 2. Redistributions in binary form must reproduce the above copyright 425e8fcd94Spk * notice, this list of conditions and the following disclaimer in the 435e8fcd94Spk * documentation and/or other materials provided with the distribution. 445e8fcd94Spk * 3. The name of the authors may not be used to endorse or promote products 455e8fcd94Spk * derived from this software without specific prior written permission. 465e8fcd94Spk * 475e8fcd94Spk * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 485e8fcd94Spk * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 495e8fcd94Spk * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 505e8fcd94Spk * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 515e8fcd94Spk * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 525e8fcd94Spk * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 535e8fcd94Spk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 545e8fcd94Spk * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 555e8fcd94Spk * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 565e8fcd94Spk * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 575e8fcd94Spk */ 585e8fcd94Spk 595e8fcd94Spk /* 605e8fcd94Spk * QE Channel registers 61f9f72ecfSmycroft */ 62f9f72ecfSmycroft #if 0 635e8fcd94Spk struct qe_cregs { 64*579b9cbdStsutsui uint32_t ctrl; /* control */ 65*579b9cbdStsutsui uint32_t stat; /* status */ 66*579b9cbdStsutsui uint32_t rxds; /* rx descriptor ring ptr */ 67*579b9cbdStsutsui uint32_t txds; /* tx descriptor ring ptr */ 68*579b9cbdStsutsui uint32_t rimask; /* rx interrupt mask */ 69*579b9cbdStsutsui uint32_t timask; /* tx interrupt mask */ 70*579b9cbdStsutsui uint32_t qmask; /* qec error interrupt mask */ 71*579b9cbdStsutsui uint32_t mmask; /* mace error interrupt mask */ 72*579b9cbdStsutsui uint32_t rxwbufptr; /* local memory rx write ptr */ 73*579b9cbdStsutsui uint32_t rxrbufptr; /* local memory rx read ptr */ 74*579b9cbdStsutsui uint32_t txwbufptr; /* local memory tx write ptr */ 75*579b9cbdStsutsui uint32_t txrbufptr; /* local memory tx read ptr */ 76*579b9cbdStsutsui uint32_t ccnt; /* collision counter */ 77*579b9cbdStsutsui uint32_t pipg; /* inter-frame gap */ 785e8fcd94Spk }; 79f9f72ecfSmycroft #endif 80f9f72ecfSmycroft /* register indices: */ 815e8fcd94Spk #define QE_CRI_CTRL (0*4) 825e8fcd94Spk #define QE_CRI_STAT (1*4) 835e8fcd94Spk #define QE_CRI_RXDS (2*4) 845e8fcd94Spk #define QE_CRI_TXDS (3*4) 855e8fcd94Spk #define QE_CRI_RIMASK (4*4) 865e8fcd94Spk #define QE_CRI_TIMASK (5*4) 875e8fcd94Spk #define QE_CRI_QMASK (6*4) 885e8fcd94Spk #define QE_CRI_MMASK (7*4) 895e8fcd94Spk #define QE_CRI_RXWBUF (8*4) 905e8fcd94Spk #define QE_CRI_RXRBUF (9*4) 915e8fcd94Spk #define QE_CRI_TXWBUF (10*4) 925e8fcd94Spk #define QE_CRI_TXRBUF (11*4) 935e8fcd94Spk #define QE_CRI_CCNT (12*4) 945e8fcd94Spk #define QE_CRI_PIPG (13*4) 955e8fcd94Spk 965e8fcd94Spk /* qe_cregs.ctrl: control. */ 975e8fcd94Spk #define QE_CR_CTRL_RXOFF 0x00000004 /* disable receiver */ 985e8fcd94Spk #define QE_CR_CTRL_RESET 0x00000002 /* reset this channel */ 991ffa7b76Swiz #define QE_CR_CTRL_TWAKEUP 0x00000001 /* tx DMA wakeup */ 1005e8fcd94Spk 1015e8fcd94Spk /* qe_cregs.stat: status. */ 1025e8fcd94Spk #define QE_CR_STAT_EDEFER 0x10000000 /* excessive defers */ 1035e8fcd94Spk #define QE_CR_STAT_CLOSS 0x08000000 /* loss of carrier */ 1045e8fcd94Spk #define QE_CR_STAT_ERETRIES 0x04000000 /* >16 retries */ 1055e8fcd94Spk #define QE_CR_STAT_LCOLL 0x02000000 /* late tx collision */ 1065e8fcd94Spk #define QE_CR_STAT_FUFLOW 0x01000000 /* fifo underflow */ 1075e8fcd94Spk #define QE_CR_STAT_JERROR 0x00800000 /* jabber error */ 1085e8fcd94Spk #define QE_CR_STAT_BERROR 0x00400000 /* babble error */ 1095e8fcd94Spk #define QE_CR_STAT_TXIRQ 0x00200000 /* tx interrupt */ 1105e8fcd94Spk #define QE_CR_STAT_TCCOFLOW 0x00100000 /* tx collision cntr expired */ 1115e8fcd94Spk #define QE_CR_STAT_TXDERROR 0x00080000 /* tx descriptor is bad */ 1125e8fcd94Spk #define QE_CR_STAT_TXLERR 0x00040000 /* tx late error */ 1135e8fcd94Spk #define QE_CR_STAT_TXPERR 0x00020000 /* tx parity error */ 1145e8fcd94Spk #define QE_CR_STAT_TXSERR 0x00010000 /* tx sbus error ack */ 1155e8fcd94Spk #define QE_CR_STAT_RCCOFLOW 0x00001000 /* rx collision cntr expired */ 1165e8fcd94Spk #define QE_CR_STAT_RUOFLOW 0x00000800 /* rx runt counter expired */ 1175e8fcd94Spk #define QE_CR_STAT_MCOFLOW 0x00000400 /* rx missed counter expired */ 1185e8fcd94Spk #define QE_CR_STAT_RXFOFLOW 0x00000200 /* rx fifo over flow */ 1195e8fcd94Spk #define QE_CR_STAT_RLCOLL 0x00000100 /* rx late collision */ 1205e8fcd94Spk #define QE_CR_STAT_FCOFLOW 0x00000080 /* rx frame counter expired */ 1215e8fcd94Spk #define QE_CR_STAT_CECOFLOW 0x00000040 /* rx crc error cntr expired */ 1225e8fcd94Spk #define QE_CR_STAT_RXIRQ 0x00000020 /* rx interrupt */ 1235e8fcd94Spk #define QE_CR_STAT_RXDROP 0x00000010 /* rx dropped packet */ 1245e8fcd94Spk #define QE_CR_STAT_RXSMALL 0x00000008 /* rx buffer too small */ 1255e8fcd94Spk #define QE_CR_STAT_RXLERR 0x00000004 /* rx late error */ 1265e8fcd94Spk #define QE_CR_STAT_RXPERR 0x00000002 /* rx parity error */ 1275e8fcd94Spk #define QE_CR_STAT_RXSERR 0x00000001 /* rx sbus error ack */ 1285e8fcd94Spk #define QE_CR_STAT_BITS "\177\020" \ 1295e8fcd94Spk "b\0RXSERR\0b\1RXPERR\0b\2RXLERR\0" \ 1305e8fcd94Spk "b\3RXSMALL\0b\4RXDROP\0b\5RXIRQ\0" \ 1315e8fcd94Spk "b\6CECOFLOW\0b\7FCOFLOW\0b\10RLCOLL\0" \ 1325e8fcd94Spk "b\11RXFOFLOW\0b\12MCOFLOW\0b\13RUOFLOW\0" \ 13352db3a15Spk "b\14RCCOFLOW\0b\20TXSERR\0b\21TXPERR\0" \ 13452db3a15Spk "b\22TXLERR\0b\23TXDERROR\0b\24TCCOFLOW\0" \ 13552db3a15Spk "b\25TXIRQ\0b\26BERROR\0b\27JERROR\0" \ 13652db3a15Spk "b\30FUFLOW\0b\31LCOLL\0b\32ERETRIES\0" \ 137a80733a6Sjdolecek "b\33CLOSS\0b\34EDEFER\0\0" 1385e8fcd94Spk 1395e8fcd94Spk /* 1405e8fcd94Spk * Errors: all status bits except for TX/RX IRQ 1415e8fcd94Spk */ 1425e8fcd94Spk #define QE_CR_STAT_ALLERRORS \ 1435e8fcd94Spk ( QE_CR_STAT_EDEFER | QE_CR_STAT_CLOSS | QE_CR_STAT_ERETRIES \ 1445e8fcd94Spk | QE_CR_STAT_LCOLL | QE_CR_STAT_FUFLOW | QE_CR_STAT_JERROR \ 1455e8fcd94Spk | QE_CR_STAT_BERROR | QE_CR_STAT_TCCOFLOW | QE_CR_STAT_TXDERROR \ 1465e8fcd94Spk | QE_CR_STAT_TXLERR | QE_CR_STAT_TXPERR | QE_CR_STAT_TXSERR \ 1475e8fcd94Spk | QE_CR_STAT_RCCOFLOW | QE_CR_STAT_RUOFLOW | QE_CR_STAT_MCOFLOW \ 1485e8fcd94Spk | QE_CR_STAT_RXFOFLOW | QE_CR_STAT_RLCOLL | QE_CR_STAT_FCOFLOW \ 1495e8fcd94Spk | QE_CR_STAT_CECOFLOW | QE_CR_STAT_RXDROP | QE_CR_STAT_RXSMALL \ 1505e8fcd94Spk | QE_CR_STAT_RXLERR | QE_CR_STAT_RXPERR | QE_CR_STAT_RXSERR) 1515e8fcd94Spk 1525e8fcd94Spk /* qe_cregs.qmask: qec error interrupt mask. */ 1535e8fcd94Spk #define QE_CR_QMASK_COFLOW 0x00100000 /* collision cntr overflow */ 1545e8fcd94Spk #define QE_CR_QMASK_TXDERROR 0x00080000 /* tx descriptor error */ 1555e8fcd94Spk #define QE_CR_QMASK_TXLERR 0x00040000 /* tx late error */ 1565e8fcd94Spk #define QE_CR_QMASK_TXPERR 0x00020000 /* tx parity error */ 1575e8fcd94Spk #define QE_CR_QMASK_TXSERR 0x00010000 /* tx sbus error ack */ 1585e8fcd94Spk #define QE_CR_QMASK_RXDROP 0x00000010 /* rx packet dropped */ 1595e8fcd94Spk #define QE_CR_QMASK_RXSMALL 0x00000008 /* rx buffer too small */ 1605e8fcd94Spk #define QE_CR_QMASK_RXLERR 0x00000004 /* rx late error */ 1615e8fcd94Spk #define QE_CR_QMASK_RXPERR 0x00000002 /* rx parity error */ 1625e8fcd94Spk #define QE_CR_QMASK_RXSERR 0x00000001 /* rx sbus error ack */ 1635e8fcd94Spk 1645e8fcd94Spk /* qe_cregs.mmask: MACE error interrupt mask. */ 1655e8fcd94Spk #define QE_CR_MMASK_EDEFER 0x10000000 /* excess defer */ 1665e8fcd94Spk #define QE_CR_MMASK_CLOSS 0x08000000 /* carrier loss */ 1675e8fcd94Spk #define QE_CR_MMASK_ERETRY 0x04000000 /* excess retry */ 1685e8fcd94Spk #define QE_CR_MMASK_LCOLL 0x02000000 /* late collision error */ 1695e8fcd94Spk #define QE_CR_MMASK_UFLOW 0x01000000 /* underflow */ 1705e8fcd94Spk #define QE_CR_MMASK_JABBER 0x00800000 /* jabber error */ 1715e8fcd94Spk #define QE_CR_MMASK_BABBLE 0x00400000 /* babble error */ 1725e8fcd94Spk #define QE_CR_MMASK_OFLOW 0x00000800 /* overflow */ 1735e8fcd94Spk #define QE_CR_MMASK_RXCOLL 0x00000400 /* rx coll-cntr overflow */ 1745e8fcd94Spk #define QE_CR_MMASK_RPKT 0x00000200 /* runt pkt overflow */ 1755e8fcd94Spk #define QE_CR_MMASK_MPKT 0x00000100 /* missed pkt overflow */ 1765e8fcd94Spk 1775e8fcd94Spk /* qe_cregs.pipg: inter-frame gap. */ 1785e8fcd94Spk #define QE_CR_PIPG_TENAB 0x00000020 /* enable throttle */ 1795e8fcd94Spk #define QE_CR_PIPG_MMODE 0x00000010 /* manual mode */ 1805e8fcd94Spk #define QE_CR_PIPG_WMASK 0x0000000f /* sbus wait mask */ 1815e8fcd94Spk 1825e8fcd94Spk /* 1835e8fcd94Spk * MACE registers 184f9f72ecfSmycroft */ 185f9f72ecfSmycroft #if 0 1865e8fcd94Spk struct qe_mregs { 187*579b9cbdStsutsui uint8_t rcvfifo; /* [0] receive fifo */ 188*579b9cbdStsutsui uint8_t xmtfifo; /* [1] transmit fifo */ 189*579b9cbdStsutsui uint8_t xmtfc; /* [2] transmit frame control */ 190*579b9cbdStsutsui uint8_t xmtfs; /* [3] transmit frame status */ 191*579b9cbdStsutsui uint8_t xmtrc; /* [4] tx retry count */ 192*579b9cbdStsutsui uint8_t rcvfc; /* [5] receive frame control */ 193*579b9cbdStsutsui uint8_t rcvfs; /* [6] receive frame status */ 194*579b9cbdStsutsui uint8_t fifofc; /* [7] fifo frame count */ 195*579b9cbdStsutsui uint8_t ir; /* [8] interrupt register */ 196*579b9cbdStsutsui uint8_t imr; /* [9] interrupt mask register */ 197*579b9cbdStsutsui uint8_t pr; /* [10] poll register */ 198*579b9cbdStsutsui uint8_t biucc; /* [11] biu config control */ 199*579b9cbdStsutsui uint8_t fifocc; /* [12] fifo config control */ 200*579b9cbdStsutsui uint8_t maccc; /* [13] mac config control */ 201*579b9cbdStsutsui uint8_t plscc; /* [14] pls config control */ 202*579b9cbdStsutsui uint8_t phycc; /* [15] phy config control */ 203*579b9cbdStsutsui uint8_t chipid1; /* [16] chipid, low byte */ 204*579b9cbdStsutsui uint8_t chipid2; /* [17] chipid, high byte */ 205*579b9cbdStsutsui uint8_t iac; /* [18] internal address config */ 206*579b9cbdStsutsui uint8_t _reserved0; /* [19] reserved */ 207*579b9cbdStsutsui uint8_t ladrf; /* [20] logical address filter */ 208*579b9cbdStsutsui uint8_t padr; /* [21] physical address */ 209*579b9cbdStsutsui uint8_t _reserved1; /* [22] reserved */ 210*579b9cbdStsutsui uint8_t _reserved2; /* [23] reserved */ 211*579b9cbdStsutsui uint8_t mpc; /* [24] missed packet count */ 212*579b9cbdStsutsui uint8_t _reserved3; /* [25] reserved */ 213*579b9cbdStsutsui uint8_t rntpc; /* [26] runt packet count */ 214*579b9cbdStsutsui uint8_t rcvcc; /* [27] receive collision count */ 215*579b9cbdStsutsui uint8_t _reserved4; /* [28] reserved */ 216*579b9cbdStsutsui uint8_t utr; /* [29] user test register */ 217*579b9cbdStsutsui uint8_t rtr1; /* [30] reserved test register 1 */ 218*579b9cbdStsutsui uint8_t rtr2; /* [31] reserved test register 2 */ 2195e8fcd94Spk }; 220f9f72ecfSmycroft #endif 221f9f72ecfSmycroft /* register indices: */ 222f9f72ecfSmycroft #define QE_MRI_RCVFIFO 0 /* receive fifo */ 223f9f72ecfSmycroft #define QE_MRI_XMTFIFO 1 /* transmit fifo */ 224f9f72ecfSmycroft #define QE_MRI_XMTFC 2 /* transmit frame control */ 225f9f72ecfSmycroft #define QE_MRI_XMTFS 3 /* transmit frame status */ 226f9f72ecfSmycroft #define QE_MRI_XMTRC 4 /* tx retry count */ 227f9f72ecfSmycroft #define QE_MRI_RCVFC 5 /* receive frame control */ 228f9f72ecfSmycroft #define QE_MRI_RCVFS 6 /* receive frame status */ 229f9f72ecfSmycroft #define QE_MRI_FIFOFC 7 /* fifo frame count */ 230f9f72ecfSmycroft #define QE_MRI_IR 8 /* interrupt register */ 231f9f72ecfSmycroft #define QE_MRI_IMR 9 /* interrupt mask register */ 232f9f72ecfSmycroft #define QE_MRI_PR 10 /* poll register */ 233f9f72ecfSmycroft #define QE_MRI_BIUCC 11 /* biu config control */ 234f9f72ecfSmycroft #define QE_MRI_FIFOCC 12 /* fifo config control */ 235f9f72ecfSmycroft #define QE_MRI_MACCC 13 /* mac config control */ 236f9f72ecfSmycroft #define QE_MRI_PLSCC 14 /* pls config control */ 237f9f72ecfSmycroft #define QE_MRI_PHYCC 15 /* phy config control */ 238f9f72ecfSmycroft #define QE_MRI_CHIPID1 16 /* chipid, low byte */ 239f9f72ecfSmycroft #define QE_MRI_CHIPID2 17 /* chipid, high byte */ 240f9f72ecfSmycroft #define QE_MRI_IAC 18 /* internal address config */ 241f9f72ecfSmycroft #define QE_MRI_LADRF 20 /* logical address filter */ 242f9f72ecfSmycroft #define QE_MRI_PADR 21 /* physical address */ 243f9f72ecfSmycroft #define QE_MRI_MPC 24 /* missed packet count */ 244f9f72ecfSmycroft #define QE_MRI_RNTPC 26 /* runt packet count */ 245f9f72ecfSmycroft #define QE_MRI_RCVCC 27 /* receive collision count */ 246f9f72ecfSmycroft #define QE_MRI_UTR 29 /* user test register */ 247f9f72ecfSmycroft #define QE_MRI_RTR1 30 /* reserved test register 1 */ 248f9f72ecfSmycroft #define QE_MRI_RTR2 31 /* reserved test register 2 */ 2495e8fcd94Spk 2505e8fcd94Spk /* qe_mregs.xmtfc: transmit frame control. */ 2515e8fcd94Spk #define QE_MR_XMTFC_DRETRY 0x80 /* disable retries */ 2525e8fcd94Spk #define QE_MR_XMTFC_DXMTFCS 0x08 /* disable tx fcs */ 2535e8fcd94Spk #define QE_MR_XMTFC_APADXMT 0x01 /* enable auto padding */ 2545e8fcd94Spk 2555e8fcd94Spk /* qe_mregs.xmtfs: transmit frame status. */ 2565e8fcd94Spk #define QE_MR_XMTFS_XMTSV 0x80 /* tx valid */ 2575e8fcd94Spk #define QE_MR_XMTFS_UFLO 0x40 /* tx underflow */ 2585e8fcd94Spk #define QE_MR_XMTFS_LCOL 0x20 /* tx late collision */ 2595e8fcd94Spk #define QE_MR_XMTFS_MORE 0x10 /* tx > 1 retries */ 2605e8fcd94Spk #define QE_MR_XMTFS_ONE 0x08 /* tx 1 retry */ 2615e8fcd94Spk #define QE_MR_XMTFS_DEFER 0x04 /* tx pkt deferred */ 2625e8fcd94Spk #define QE_MR_XMTFS_LCAR 0x02 /* tx carrier lost */ 2635e8fcd94Spk #define QE_MR_XMTFS_RTRY 0x01 /* tx retry error */ 2645e8fcd94Spk 2655e8fcd94Spk /* qe_mregs.xmtrc: transmit retry count. */ 2665e8fcd94Spk #define QE_MR_XMTRC_EXDEF 0x80 /* tx excess defers */ 2675e8fcd94Spk #define QE_MR_XMTRC_XMTRC 0x0f /* tx retry count mask */ 2685e8fcd94Spk 2695e8fcd94Spk /* qe_mregs.rcvfc: receive frame control. */ 2705e8fcd94Spk #define QE_MR_RCVFC_LLRCV 0x08 /* rx low latency */ 2715e8fcd94Spk #define QE_MR_RCVFC_MR 0x04 /* rx addr match/reject */ 2725e8fcd94Spk #define QE_MR_RCVFC_ASTRPRCV 0x01 /* rx auto strip */ 2735e8fcd94Spk 2745e8fcd94Spk /* qe_mregs.rcvfs: receive frame status. */ 2755e8fcd94Spk #define QE_MR_RCVFS_OFLO 0x80 /* rx overflow */ 2765e8fcd94Spk #define QE_MR_RCVFS_CLSN 0x40 /* rx late collision */ 2775e8fcd94Spk #define QE_MR_RCVFS_FRAM 0x20 /* rx framing error */ 2785e8fcd94Spk #define QE_MR_RCVFS_FCS 0x10 /* rx fcs error */ 2795e8fcd94Spk #define QE_MR_RCVFS_RCVCNT 0x0f /* rx msg byte count mask */ 2805e8fcd94Spk 2815e8fcd94Spk /* qe_mregs.fifofc: fifo frame count. */ 2825e8fcd94Spk #define QE_MR_FIFOFC_RCVFC 0xf0 /* rx fifo frame count */ 2835e8fcd94Spk #define QE_MR_FIFOFC_XMTFC 0x0f /* tx fifo frame count */ 2845e8fcd94Spk 2855e8fcd94Spk /* qe_mregs.ir: interrupt register. */ 2865e8fcd94Spk #define QE_MR_IR_JAB 0x80 /* jabber error */ 2875e8fcd94Spk #define QE_MR_IR_BABL 0x40 /* babble error */ 2885e8fcd94Spk #define QE_MR_IR_CERR 0x20 /* collision error */ 2895e8fcd94Spk #define QE_MR_IR_RCVCCO 0x10 /* collision cnt overflow */ 2905e8fcd94Spk #define QE_MR_IR_RNTPCO 0x08 /* runt pkt cnt overflow */ 2915e8fcd94Spk #define QE_MR_IR_MPCO 0x04 /* miss pkt cnt overflow */ 2925e8fcd94Spk #define QE_MR_IR_RCVINT 0x02 /* packet received */ 2935e8fcd94Spk #define QE_MR_IR_XMTINT 0x01 /* packet transmitted */ 2945e8fcd94Spk 2955e8fcd94Spk /* qe_mregs.imr: interrupt mask register. */ 2965e8fcd94Spk #define QE_MR_IMR_JABM 0x80 /* jabber errors */ 2975e8fcd94Spk #define QE_MR_IMR_BABLM 0x40 /* babble errors */ 2985e8fcd94Spk #define QE_MR_IMR_CERRM 0x20 /* collision errors */ 2995e8fcd94Spk #define QE_MR_IMR_RCVCCOM 0x10 /* rx collision count oflow */ 3005e8fcd94Spk #define QE_MR_IMR_RNTPCOM 0x08 /* runt pkt cnt ovrflw */ 3015e8fcd94Spk #define QE_MR_IMR_MPCOM 0x04 /* miss pkt cnt ovrflw */ 3025e8fcd94Spk #define QE_MR_IMR_RCVINTM 0x02 /* rx interrupts */ 3035e8fcd94Spk #define QE_MR_IMR_XMTINTM 0x01 /* tx interrupts */ 3045e8fcd94Spk 3055e8fcd94Spk /* qe_mregs.pr: poll register. */ 3065e8fcd94Spk #define QE_MR_PR_XMTSV 0x80 /* tx status is valid */ 3075e8fcd94Spk #define QE_MR_PR_TDTREQ 0x40 /* tx data xfer request */ 3085e8fcd94Spk #define QE_MR_PR_RDTREQ 0x20 /* rx data xfer request */ 3095e8fcd94Spk 3105e8fcd94Spk /* qe_mregs.biucc: biu config control. */ 3115e8fcd94Spk #define QE_MR_BIUCC_BSWAP 0x40 /* byte swap */ 3125e8fcd94Spk #define QE_MR_BIUCC_4TS 0x00 /* 4byte xmit start point */ 3135e8fcd94Spk #define QE_MR_BIUCC_16TS 0x10 /* 16byte xmit start point */ 3145e8fcd94Spk #define QE_MR_BIUCC_64TS 0x20 /* 64byte xmit start point */ 3155e8fcd94Spk #define QE_MR_BIUCC_112TS 0x30 /* 112byte xmit start point */ 3165e8fcd94Spk #define QE_MR_BIUCC_SWRST 0x01 /* sw-reset mace */ 3175e8fcd94Spk 3185e8fcd94Spk /* qe_mregs.fifocc: fifo config control. */ 3195e8fcd94Spk #define QE_MR_FIFOCC_TXF8 0x00 /* tx fifo 8 write cycles */ 3205e8fcd94Spk #define QE_MR_FIFOCC_TXF32 0x80 /* tx fifo 32 write cycles */ 3215e8fcd94Spk #define QE_MR_FIFOCC_TXF16 0x40 /* tx fifo 16 write cycles */ 3225e8fcd94Spk #define QE_MR_FIFOCC_RXF64 0x20 /* rx fifo 64 write cycles */ 3235e8fcd94Spk #define QE_MR_FIFOCC_RXF32 0x10 /* rx fifo 32 write cycles */ 3245e8fcd94Spk #define QE_MR_FIFOCC_RXF16 0x00 /* rx fifo 16 write cycles */ 3255e8fcd94Spk #define QE_MR_FIFOCC_TFWU 0x08 /* tx fifo watermark update */ 3265e8fcd94Spk #define QE_MR_FIFOCC_RFWU 0x04 /* rx fifo watermark update */ 3275e8fcd94Spk #define QE_MR_FIFOCC_XMTBRST 0x02 /* tx burst enable */ 3285e8fcd94Spk #define QE_MR_FIFOCC_RCVBRST 0x01 /* rx burst enable */ 3295e8fcd94Spk 3305e8fcd94Spk /* qe_mregs.maccc: mac config control. */ 3315e8fcd94Spk #define QE_MR_MACCC_PROM 0x80 /* promiscuous mode enable */ 3325e8fcd94Spk #define QE_MR_MACCC_DXMT2PD 0x40 /* tx 2part deferral enable */ 3335e8fcd94Spk #define QE_MR_MACCC_EMBA 0x20 /* modified backoff enable */ 3345e8fcd94Spk #define QE_MR_MACCC_DRCVPA 0x08 /* rx physical addr disable */ 3355e8fcd94Spk #define QE_MR_MACCC_DRCVBC 0x04 /* rx broadcast disable */ 3365e8fcd94Spk #define QE_MR_MACCC_ENXMT 0x02 /* enable transmitter */ 3375e8fcd94Spk #define QE_MR_MACCC_ENRCV 0x01 /* enable receiver */ 3385e8fcd94Spk 3395e8fcd94Spk /* qe_mregs.plscc: pls config control. */ 3405e8fcd94Spk #define QE_MR_PLSCC_XMTSEL 0x08 /* tx mode select */ 3415e8fcd94Spk #define QE_MR_PLSCC_PORTMASK 0x06 /* port selection bits */ 3425e8fcd94Spk #define QE_MR_PLSCC_GPSI 0x06 /* use gpsi connector */ 3435e8fcd94Spk #define QE_MR_PLSCC_DAI 0x04 /* use dai connector */ 3445e8fcd94Spk #define QE_MR_PLSCC_TP 0x02 /* use twistedpair connector */ 3455e8fcd94Spk #define QE_MR_PLSCC_AUI 0x00 /* use aui connector */ 3465e8fcd94Spk #define QE_MR_PLSCC_ENPLSIO 0x01 /* pls i/o enable */ 3475e8fcd94Spk 3485e8fcd94Spk /* qe_mregs.phycc: phy config control. */ 3495e8fcd94Spk #define QE_MR_PHYCC_LNKFL 0x80 /* link fail */ 3505e8fcd94Spk #define QE_MR_PHYCC_DLNKTST 0x40 /* disable link test logic */ 3515e8fcd94Spk #define QE_MR_PHYCC_REVPOL 0x20 /* rx polarity */ 3525e8fcd94Spk #define QE_MR_PHYCC_DAPC 0x10 /* autopolaritycorrect disab */ 3535e8fcd94Spk #define QE_MR_PHYCC_LRT 0x08 /* select low threshold */ 3545e8fcd94Spk #define QE_MR_PHYCC_ASEL 0x04 /* connector port auto-sel */ 3555e8fcd94Spk #define QE_MR_PHYCC_RWAKE 0x02 /* remote wakeup */ 3565e8fcd94Spk #define QE_MR_PHYCC_AWAKE 0x01 /* auto wakeup */ 3575e8fcd94Spk 3585e8fcd94Spk /* qe_mregs.iac: internal address config. */ 3595e8fcd94Spk #define QE_MR_IAC_ADDRCHG 0x80 /* start address change */ 3605e8fcd94Spk #define QE_MR_IAC_PHYADDR 0x04 /* physical address reset */ 3615e8fcd94Spk #define QE_MR_IAC_LOGADDR 0x02 /* logical address reset */ 3625e8fcd94Spk 3635e8fcd94Spk /* qe_mregs.utr: user test register. */ 3645e8fcd94Spk #define QE_MR_UTR_RTRE 0x80 /* enable resv test register */ 3655e8fcd94Spk #define QE_MR_UTR_RTRD 0x40 /* disab resv test register */ 3665e8fcd94Spk #define QE_MR_UTR_RPA 0x20 /* accept runt packets */ 3675e8fcd94Spk #define QE_MR_UTR_FCOLL 0x10 /* force collision status */ 3685e8fcd94Spk #define QE_MR_UTR_RCVSFCSE 0x08 /* enable fcs on rx */ 3695e8fcd94Spk #define QE_MR_UTR_INTLOOPM 0x06 /* Internal loopback w/mandec */ 3705e8fcd94Spk #define QE_MR_UTR_INTLOOP 0x04 /* Internal loopback */ 3715e8fcd94Spk #define QE_MR_UTR_EXTLOOP 0x02 /* external loopback */ 3725e8fcd94Spk #define QE_MR_UTR_NOLOOP 0x00 /* no loopback */ 3735e8fcd94Spk 3745e8fcd94Spk /* Buffer and Ring sizes: fixed ring size */ 3755e8fcd94Spk #define QE_TX_RING_MAXSIZE 256 /* maximum tx ring size */ 3765e8fcd94Spk #define QE_RX_RING_MAXSIZE 256 /* maximum rx ring size */ 3775e8fcd94Spk #define QE_TX_RING_SIZE 16 3785e8fcd94Spk #define QE_RX_RING_SIZE 16 3795e8fcd94Spk #define QE_PKT_BUF_SZ 2048 3805e8fcd94Spk 3815e8fcd94Spk #define MC_POLY_LE 0xedb88320 /* mcast crc, little endian */ 382