1 /* $NetBSD: stp4020reg.h,v 1.1 1998/11/22 22:14:35 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 40 #ifndef _STP4020_REG_H 41 #define _STP4020_REG_H 42 43 /* 44 * STP4020: SBus/PCMCIA bridge supporting two Type-3 PCMCIA cards. 45 * Programming information source: 46 * - http://www.sun.com/microelectronics/datasheets/stp4020/ 47 * - SunOS 5.5 header file 48 */ 49 50 /* 51 * General chip attibutes. 52 */ 53 #define STP4020_NSOCK 2 /* number of PCCARD sockets per STP4020 */ 54 #define STP4020_NWIN 3 /* number of windows per socket */ 55 56 /* 57 * Socket control registers. 58 * 59 * Each PCMCIA socket has two interface control registers and two interface 60 * status registers associated with it. 61 */ 62 63 /* 64 * Socket Interface Control register 0 65 */ 66 #define STP4020_ICR0_rsvd1 0xc000 /* reserved bits */ 67 #define STP4020_ICR0_PROMEN 0x2000 /* FCode PROM enable */ 68 /* Status change interrupts can be routed to one of two SBus interrupt levels:*/ 69 #define STP4020_ICR0_SCILVL 0x1000 /* card status change interrupt level */ 70 #define STP4020_ICR0_SCILVL_SB0 0x0000 /* interrupt on *SB_INT[0] */ 71 #define STP4020_ICR0_SCILVL_SB1 0x1000 /* interrupt on *SB_INT[1] */ 72 /* Interrupt enable bits: */ 73 #define STP4020_ICR0_CDIE 0x0800 /* card detect interrupt enable */ 74 #define STP4020_ICR0_BVD2IE 0x0400 /* battery voltage detect 2 int en. */ 75 #define STP4020_ICR0_BVD1IE 0x0200 /* battery voltage detect 1 int en. */ 76 #define STP4020_ICR0_RDYIE 0x0100 /* ready/busy interrupt enable */ 77 #define STP4020_ICR0_WPIE 0x0080 /* write protect interrupt enable */ 78 #define STP4020_ICR0_CTOIE 0x0040 /* PC card timeout interrupt enable */ 79 #define STP4020_ICR0_rsvd2 0x0020 /* */ 80 #define STP4020_ICR0_IOIE 0x0010 /* I/O (*IRQ) interrupt enable */ 81 /* PC card I/O interrupts can also be routed to one of two SBus intr levels: */ 82 #define STP4020_ICR0_IOILVL 0x0008 /* I/O (*IRQ) interrupt level (SBus) */ 83 #define STP4020_ICR0_IOILVL_SB0 0x0000 /* interrupt on *SB_INT[0] */ 84 #define STP4020_ICR0_IOILVL_SB1 0x0008 /* interrupt on *SB_INT[1] */ 85 86 #define STP4020_ICR0_SPKREN 0x0004 /* *SPKR_OUT enable */ 87 #define STP4020_ICR0_RESET 0x0002 /* PC card reset */ 88 #define STP4020_ICR0_IFTYPE 0x0001 /* PC card interface type */ 89 #define STP4020_ICR0_IFTYPE_MEM 0x0000 /* MEMORY only */ 90 #define STP4020_ICR0_IFTYPE_IO 0x0001 /* MEMORY and I/O */ 91 #define STP4020_ICR0_BITS "\177\010" \ 92 "b\0IFTYPE\0b\1RESET\0b\2SPKREN\0" \ 93 "b\3IOILVL\0b\4IOIE\0b\6CTOIE\0" \ 94 "b\7WPIE\0b\10RDYIE\0b\11BVD1IE\0b\12BVD2IE\0"\ 95 "b\13CDIE\0b\14SCILV\0b\15PROMEN\0\0" 96 97 /* Shorthand for all status change interrupts enables */ 98 #define STP4020_ICR0_ALL_STATUS_IE ( \ 99 STP4020_ICR0_CDIE | \ 100 STP4020_ICR0_BVD2IE | \ 101 STP4020_ICR0_BVD1IE | \ 102 STP4020_ICR0_RDYIE | \ 103 STP4020_ICR0_WPIE | \ 104 STP4020_ICR0_CTOIE \ 105 ) 106 107 /* 108 * Socket Interface Control register 1 109 */ 110 #define STP4020_ICR1_LPBKEN 0x8000 /* PC card data loopback enable */ 111 #define STP4020_ICR1_CD1DB 0x4000 /* card detect 1 diagnostic bit */ 112 #define STP4020_ICR1_BVD2DB 0x2000 /* battery voltage detect 2 diag bit */ 113 #define STP4020_ICR1_BVD1DB 0x1000 /* battery voltage detect 1 diag bit */ 114 #define STP4020_ICR1_RDYDB 0x0800 /* ready/busy diagnostic bit */ 115 #define STP4020_ICR1_WPDB 0x0400 /* write protect diagnostic bit */ 116 #define STP4020_ICR1_WAITDB 0x0200 /* *WAIT diagnostic bit */ 117 #define STP4020_ICR1_DIAGEN 0x0100 /* diagnostic enable bit */ 118 #define STP4020_ICR1_rsvd1 0x0080 /* reserved */ 119 #define STP4020_ICR1_APWREN 0x0040 /* PC card auto power switch enable */ 120 121 /* 122 * The Vpp controls are two-bit fields which specify which voltage 123 * should be switched onto Vpp for this socket. 124 * 125 * Both of the "no connect" states are equal. 126 */ 127 #define STP4020_ICR1_VPP2EN 0x0030 /* Vpp2 power enable */ 128 #define STP4020_ICR1_VPP2_OFF 0x0000 /* no connect */ 129 #define STP4020_ICR1_VPP2_VCC 0x0010 /* Vcc switched onto Vpp2 */ 130 #define STP4020_ICR1_VPP2_VPP 0x0020 /* Vpp switched onto Vpp2 */ 131 #define STP4020_ICR1_VPP2_ZIP 0x0030 /* no connect */ 132 133 #define STP4020_ICR1_VPP1EN 0x000c /* Vpp1 power enable */ 134 #define STP4020_ICR1_VPP1_OFF 0x0000 /* no connect */ 135 #define STP4020_ICR1_VPP1_VCC 0x0004 /* Vcc switched onto Vpp1 */ 136 #define STP4020_ICR1_VPP1_VPP 0x0008 /* Vpp switched onto Vpp1 */ 137 #define STP4020_ICR1_VPP1_ZIP 0x000c /* no connect */ 138 139 #define STP4020_ICR1_MSTPWR 0x0002 /* PC card master power enable */ 140 #define STP4020_ICR1_PCIFOE 0x0001 /* PC card interface output enable */ 141 142 #define STP4020_ICR1_BITS "\177\010" \ 143 "b\0PCIFOE\0b\1MSTPWR\0f\2\2VPP1EN\0" \ 144 "f\4\2VPP2EN\0b\6APWREN\0b\10DIAGEN\0" \ 145 "b\11WAITDB\0b\12WPDB\0b\13RDYDB\0" \ 146 "b\14BVD1D\0b\15BVD2D\0\16CD1DB\0b\17LPBKEN\0" 147 148 /* 149 * Socket Interface Status register 0 150 * 151 * Some signals in this register change meaning depending on whether 152 * the socket is configured as MEMORY-ONLY or MEMORY & I/O: 153 * mo: valid only if the socket is in memory-only mode 154 * io: valid only if the socket is in memory and I/O mode. 155 * 156 * Pending interrupts are cleared by writing the corresponding status 157 * bit set in the upper half of this register. 158 */ 159 #define STP4020_ISR0_ZERO 0x8000 /* always reads back as zero (mo) */ 160 #define STP4020_ISR0_IOINT 0x8000 /* PC card I/O intr (*IRQ) posted (io)*/ 161 #define STP4020_ISR0_SCINT 0x4000 /* status change interrupt posted */ 162 #define STP4020_ISR0_CDCHG 0x2000 /* card detect status change */ 163 #define STP4020_ISR0_BVD2CHG 0x1000 /* battery voltage detect 2 status change */ 164 #define STP4020_ISR0_BVD1CHG 0x0800 /* battery voltage detect 1 status change */ 165 #define STP4020_ISR0_RDYCHG 0x0400 /* ready/busy status change */ 166 #define STP4020_ISR0_WPCHG 0x0200 /* write protect status change */ 167 #define STP4020_ISR0_PCTO 0x0100 /* PC card access timeout */ 168 #define STP4020_ISR0_ALL_STATUS_IRQ 0x7f00 169 170 #define STP4020_ISR0_LIVE 0x00ff /* live status bit mask */ 171 #define STP4020_ISR0_CD2ST 0x0080 /* card detect 2 live status */ 172 #define STP4020_ISR0_CD1ST 0x0040 /* card detect 1 live status */ 173 #define STP4020_ISR0_BVD2ST 0x0020 /* battery voltage detect 2 live status (mo) */ 174 #define STP4020_ISR0_SPKR 0x0020 /* SPKR signal live status (io)*/ 175 #define STP4020_ISR0_BVD1ST 0x0010 /* battery voltage detect 1 live status (mo) */ 176 #define STP4020_ISR0_STSCHG 0x0010 /* I/O *STSCHG signal live status (io)*/ 177 #define STP4020_ISR0_RDYST 0x0008 /* ready/busy live status (mo) */ 178 #define STP4020_ISR0_IOREQ 0x0008 /* I/O *REQ signal live status (io) */ 179 #define STP4020_ISR0_WPST 0x0004 /* write protect live status (mo) */ 180 #define STP4020_ISR0_IOIS16 0x0004 /* IOIS16 signal live status (io) */ 181 #define STP4020_ISR0_WAITST 0x0002 /* wait signal live status */ 182 #define STP4020_ISR0_PWRON 0x0001 /* PC card power status */ 183 184 #define STP4020_ISR0_IOBITS "\177\010" \ 185 "b\0PWRON\0b\1WAITST\0b\2IOIS16\0b\3IOREQ\0" \ 186 "b\4STSCHG\0b\5SPKR\0b\6CD1ST\0b\7CD2ST\0" \ 187 "b\10PCTO\0b\11WPCHG\0b\12RDYCHG\0" \ 188 "b\13BVD1CHG\0b\14BVD2CHG\0b\15CDCHG\0" \ 189 "b\16SCINT\0b\17IOINT\0\0" 190 #define STP4020_ISR0_MOBITS "\177\010" \ 191 "b\0PWRON\0b\1WAITST\0b\2WPST\0b\3RDYST\0" \ 192 "b\4BVD1ST\0b\5BVD2ST\0b\6CD1ST\0b\7CD2ST\0" \ 193 "b\10PCTO\0b\11WPCHG\0b\12RDYCHG\0" \ 194 "b\13BVD1CHG\0b\14BVD2CHG\0b\15CDCHG\0" \ 195 "b\16SCINT\0\0" 196 197 /* 198 * Socket Interface Status register 1 199 */ 200 #define STP4020_ISR1_rsvd 0xffc0 /* reserved */ 201 #define STP4020_ISR1_PCTYPE_M 0x0030 /* PC card type(s) supported bit mask */ 202 #define STP4020_ISR1_PCTYPE_S 4 /* PC card type(s) supported bit shift */ 203 #define STP4020_ISR1_REV_M 0x000f /* ASIC revision level bit mask */ 204 #define STP4020_ISR1_REV_S 0 /* ASIC revision level bit shift */ 205 #define STP4020_ISR1_BITS "\177\010" \ 206 "f\0\4REV\0f\4\2PCTYPE\0\0" \ 207 208 209 /* 210 * Socket window control/status register definitions. 211 * 212 * According to SunOS 5.5: 213 * "Each PCMCIA socket has three windows associated with it; each of 214 * these windows can be programmed to map in either the AM, CM or IO 215 * space on the PC card. Each window can also be programmed with a 216 * starting or base address relative to the PC card's address zero. 217 * Each window is a fixed 1Mb in size. 218 * 219 * Each window has two window control registers associated with it to 220 * control the window's PCMCIA bus timing parameters, PC card address 221 * space that that window maps, and the base address in the 222 * selected PC card's address space." 223 */ 224 #define STP4020_WINDOW_SIZE (1024*1024) /* 1MB */ 225 #define STP4020_WINDOW_SHIFT 20 /* for 1MB */ 226 227 /* 228 * PC card Window Control register 0 229 */ 230 #define STP4020_WCR0_rsvd 0x8000 /* reserved */ 231 #define STP4020_WCR0_CMDLNG_M 0x7c00 /* command strobe length bit mask */ 232 #define STP4020_WCR0_CMDLNG_S 10 /* command strobe length bit shift */ 233 #define STP4020_WCR0_CMDDLY_M 0x0300 /* command strobe delay bit mask */ 234 #define STP4020_WCR0_CMDDLY_S 8 /* command strobe delay bit shift */ 235 #define STP4020_MEM_SPEED_MIN 100 236 #define STP4020_MEM_SPEED_MAX 1370 237 /* 238 * The ASPSEL (Address Space Select) bits control which of the three PC card 239 * address spaces this window maps in. 240 */ 241 #define STP4020_WCR0_ASPSEL_M 0x00c0 /* address space select bit mask */ 242 #define STP4020_WCR0_ASPSEL_AM 0x0000 /* attribute memory */ 243 #define STP4020_WCR0_ASPSEL_CM 0x0040 /* common memory */ 244 #define STP4020_WCR0_ASPSEL_IO 0x0080 /* I/O */ 245 /* 246 * The base address controls which 1MB range in the 64MB card address space 247 * this window maps to. 248 */ 249 #define STP4020_WCR0_BASE_M 0x0003f /* base address bit mask */ 250 #define STP4020_WCR0_BASE_S 0 /* base address bit shift */ 251 252 #define STP4020_ADDR2PAGE(x) ((x) >> 20) 253 254 /* 255 * PC card Window Control register 1 256 */ 257 #define STP4020_WCR1_rsvd 0xffe0 /* reserved */ 258 #define STP4020_WCR1_RECDLY_M 0x0018 /* recovery delay bit mask */ 259 #define STP4020_WCR1_RECDLY_S 3 /* recovery delay bit shift */ 260 #define STP4020_WCR1_WAITDLY_M 0x0006 /* *WAIT signal delay bit mask */ 261 #define STP4020_WCR1_WAITDLY_S 1 /* *WAIT signal delay bit shift */ 262 #define STP4020_WCR1_WAITREQ_M 0x0001 /* *WAIT signal is required bit mask */ 263 #define STP4020_WCR1_WAITREQ_S 0 /* *WAIT signal is required bit shift */ 264 265 #if for_reference_only 266 /* 267 * STP4020 CSR structures 268 * 269 * There is one stp4020_regs_t structure per instance, and it refers to 270 * the complete Stp4020 register set. 271 * 272 * For each socket, there is one stp4020_socket_csr_t structure, which 273 * refers to all the registers for that socket. That structure is 274 * made up of the window register structures as well as the registers 275 * that control overall socket operation. 276 * 277 * For each window, there is one stp4020_window_ctl_t structure, which 278 * refers to all the registers for that window. 279 */ 280 281 /* 282 * per-window CSR structure 283 */ 284 typedef struct stp4020_window_ctl_t { 285 volatile ushort_t ctl0; /* window control register 0 */ 286 volatile ushort_t ctl1; /* window control register 1 */ 287 } stp4020_window_ctl_t; 288 289 /* 290 * per-socket CSR structure 291 */ 292 typedef struct stp4020_socket_csr_t { 293 volatile struct stp4020_window_ctl_t window[STP4020_NWIN]; 294 volatile ushort_t ctl0; /* socket control register 0 */ 295 volatile ushort_t ctl1; /* socket control register 1 */ 296 volatile ushort_t stat0; /* socket status register 0 */ 297 volatile ushort_t stat1; /* socket status register 1 */ 298 volatile uchar_t filler[12]; /* filler space */ 299 } stp4020_socket_csr_t; 300 301 /* 302 * per-instance CSR structure 303 */ 304 typedef struct stp4020_regs_t { 305 struct stp4020_socket_csr_t socket[STP4020_NSOCK]; /* socket CSRs */ 306 } stp4020_regs_t; 307 #endif /* reference */ 308 309 /* Size of control and status register banks */ 310 #define STP4020_SOCKREGS_SIZE 32 311 #define STP4020_WINREGS_SIZE 4 312 313 /* Relative socket control & status register offsets */ 314 #define STP4020_ICR0_IDX 12 315 #define STP4020_ICR1_IDX 14 316 #define STP4020_ISR0_IDX 16 317 #define STP4020_ISR1_IDX 18 318 319 /* Relative Window control register offsets */ 320 #define STP4020_WCR0_IDX 0 321 #define STP4020_WCR1_IDX 2 322 323 /* Socket control and status register offsets */ 324 #define STP4020_ICR0_REG(s) ((32 * (s)) + STP4020_ICR0_IDX) 325 #define STP4020_ICR1_REG(s) ((32 * (s)) + STP4020_ICR1_IDX) 326 #define STP4020_ISR0_REG(s) ((32 * (s)) + STP4020_ISR0_IDX) 327 #define STP4020_ISR1_REG(s) ((32 * (s)) + STP4020_ISR1_IDX) 328 329 /* Window control and status registers; one set per socket */ 330 #define STP4020_WCR0_REG(s,w) ((32 * (s)) + (4 * (w)) + STP4020_WCR0_IDX) 331 #define STP4020_WCR1_REG(s,w) ((32 * (s)) + (4 * (w)) + STP4020_WCR1_IDX) 332 333 #endif /* _STP4020_REG_H */ 334