1 /* $NetBSD: m41t81reg.h,v 1.4 2005/12/11 12:23:56 christos Exp $ */ 2 3 /* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _DEV_SMBUS_M41T81REG_H_ 39 #define _DEV_SMBUS_M41T81REG_H_ 40 41 /* The M41T81 appears at a fixed addresses on the SMBus */ 42 #define M41T81_SLAVEADDR 0x68 43 44 #define M41T81_PARTSEC 0x00 /* Partial seconds (0.01s resolution) - BCD */ 45 #define M41T81_SEC 0x01 /* Seconds - BCD */ 46 #define M41T81_SEC_ST 0x80 /* Stop Bit */ 47 #define M41T81_MIN 0x02 /* Minutes - BCD */ 48 #define M41T81_HOUR 0x03 /* Century/Hours - BCD */ 49 #define M41T81_HOUR_MASK 0x3f /* Mask for hours */ 50 #define M41T81_HOUR_CB 0x40 /* Century Bit */ 51 #define M41T81_HOUR_CEB 0x80 /* Century Enable Bit */ 52 #define M41T81_DAY 0x04 /* Day of Week */ 53 #define M41T81_DATE 0x05 /* Date: Day of Month - BCD */ 54 #define M41T81_MON 0x06 /* Month - BCD */ 55 #define M41T81_YEAR 0x07 /* Year - BCD */ 56 #define M41T81_CTL 0x08 /* Control */ 57 #define M41T81_CTL_CAL 0x1f /* Calibration mask */ 58 #define M41T81_CTL_S 0x20 /* Sign Bit */ 59 #define M41T81_CTL_FT 0x40 /* Frequency Test Bit */ 60 #define M41T81_CTL_OUT 0x80 /* Output Level */ 61 #define M41T81_WDOG 0x09 /* Watchdog */ 62 #define M41T81_WDOG_RB 0x03 /* Watchdog Resolution */ 63 #define M41T81_WDOG_RB_1_16 0x00 /* 1/16th second */ 64 #define M41T81_WDOG_RB_1_4 0x01 /* 1/4th second */ 65 #define M41T81_WDOG_RB_1 0x02 /* 1 second */ 66 #define M41T81_WDOG_RB_4 0x03 /* 4 seconds */ 67 #define M41T81_WDOG_BMB_SHIFT 2 /* Watchdog Multiplier */ 68 #define M41T81_WDOG_BMB_MASK 0x7c 69 #define M41T81_ALM_MON 0x0a /* Alarm Month - BCD */ 70 #define M41T81_ALM_MON_ABE 0x20 /* Alarm in Battery Back-up Mode Enable Bit */ 71 #define M41T81_ALM_MON_SQWE 0x40 /* Square Wave Enable */ 72 #define M41T81_ALM_MON_AFE 0x80 /* Alarm Flag Enable Flag */ 73 #define M41T81_ALM_DATE 0x0b /* Alarm Date - BCD */ 74 #define M41T81_ALM_DATE_RPT5 0x40 /* Alarm Repeat Mode Bit 5 */ 75 #define M41T81_ALM_DATE_RPT4 0x80 /* Alarm Repeat Mode Bit 4 */ 76 #define M41T81_ALM_HOUR 0x0c /* Alarm Hour - BCD */ 77 #define M41T81_ALM_HOUR_HT 0x40 /* Half Update Bit */ 78 #define M41T81_ALM_HOUR_RPT3 0x80 /* Alarm Repeat Mode Bit 3 */ 79 #define M41T81_ALM_MIN 0x0d /* Alarm Minutes - BCD */ 80 #define M41T81_ALM_MIN_RPT2 0x80 /* Alarm Repeat Mode Bit 2 */ 81 #define M41T81_ALM_SEC 0x0e /* Alarm Seconds - BCD */ 82 #define M41T81_ALM_SEC_RPT1 0x80 /* Alarm Repeat Mode Bit 1 */ 83 #define M41T81_FLAGS 0x0f 84 #define M41T81_SQW 0x13 /* Square Wave Frequency */ 85 #define M41T81_SQW_RS_SHIFT 4 /* SQW Frequency */ 86 #define M41T81_SQW_RS_MASK 0x0f /* For a non-zero value 'v', 87 the square wave frequency 88 is 2^(16-v) Hz */ 89 90 #endif /* _DEV_SMBUS_M41T81REG_H_ */ 91