1 /* $NetBSD: spiflash.c,v 1.10 2009/01/13 13:35:54 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 5 * Copyright (c) 2006 Garrett D'Amore. 6 * All rights reserved. 7 * 8 * Portions of this code were written by Garrett D'Amore for the 9 * Champaign-Urbana Community Wireless Network Project. 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer in the documentation and/or other materials provided 19 * with the distribution. 20 * 3. All advertising materials mentioning features or use of this 21 * software must display the following acknowledgements: 22 * This product includes software developed by the Urbana-Champaign 23 * Independent Media Center. 24 * This product includes software developed by Garrett D'Amore. 25 * 4. Urbana-Champaign Independent Media Center's name and Garrett 26 * D'Amore's name may not be used to endorse or promote products 27 * derived from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 30 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 31 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 32 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 34 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 36 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 37 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 38 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 40 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 41 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: spiflash.c,v 1.10 2009/01/13 13:35:54 yamt Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/conf.h> 49 #include <sys/proc.h> 50 #include <sys/systm.h> 51 #include <sys/device.h> 52 #include <sys/kernel.h> 53 #include <sys/file.h> 54 #include <sys/ioctl.h> 55 #include <sys/disk.h> 56 #include <sys/disklabel.h> 57 #include <sys/buf.h> 58 #include <sys/bufq.h> 59 #include <sys/uio.h> 60 #include <sys/kthread.h> 61 #include <sys/malloc.h> 62 #include <sys/errno.h> 63 64 #include <dev/spi/spivar.h> 65 #include <dev/spi/spiflash.h> 66 67 /* 68 * This is an MI block driver for SPI flash devices. It could probably be 69 * converted to some more generic framework, if someone wanted to create one 70 * for NOR flashes. Note that some flashes have the ability to handle 71 * interrupts. 72 */ 73 74 struct spiflash_softc { 75 struct disk sc_dk; 76 77 struct spiflash_hw_if sc_hw; 78 void *sc_cookie; 79 80 const char *sc_name; 81 struct spi_handle *sc_handle; 82 int sc_device_size; 83 int sc_write_size; 84 int sc_erase_size; 85 int sc_read_size; 86 int sc_device_blks; 87 88 struct bufq_state *sc_waitq; 89 struct bufq_state *sc_workq; 90 struct bufq_state *sc_doneq; 91 lwp_t *sc_thread; 92 }; 93 94 #define sc_getname sc_hw.sf_getname 95 #define sc_gethandle sc_hw.sf_gethandle 96 #define sc_getsize sc_hw.sf_getsize 97 #define sc_getflags sc_hw.sf_getflags 98 #define sc_erase sc_hw.sf_erase 99 #define sc_write sc_hw.sf_write 100 #define sc_read sc_hw.sf_read 101 #define sc_getstatus sc_hw.sf_getstatus 102 #define sc_setstatus sc_hw.sf_setstatus 103 104 struct spiflash_attach_args { 105 const struct spiflash_hw_if *hw; 106 void *cookie; 107 }; 108 109 #define STATIC 110 STATIC int spiflash_match(device_t , cfdata_t , void *); 111 STATIC void spiflash_attach(device_t , device_t , void *); 112 STATIC int spiflash_print(void *, const char *); 113 STATIC int spiflash_common_erase(spiflash_handle_t, size_t, size_t); 114 STATIC int spiflash_common_write(spiflash_handle_t, size_t, size_t, 115 const uint8_t *); 116 STATIC int spiflash_common_read(spiflash_handle_t, size_t, size_t, uint8_t *); 117 STATIC void spiflash_process_done(spiflash_handle_t, int); 118 STATIC void spiflash_process_read(spiflash_handle_t); 119 STATIC void spiflash_process_write(spiflash_handle_t); 120 STATIC void spiflash_thread(void *); 121 STATIC int spiflash_nsectors(spiflash_handle_t, struct buf *); 122 STATIC int spiflash_nsectors(spiflash_handle_t, struct buf *); 123 STATIC int spiflash_sector(spiflash_handle_t, struct buf *); 124 125 CFATTACH_DECL_NEW(spiflash, sizeof(struct spiflash_softc), 126 spiflash_match, spiflash_attach, NULL, NULL); 127 128 #ifdef SPIFLASH_DEBUG 129 #define DPRINTF(x) do { printf x; } while (0/*CONSTCOND*/) 130 #else 131 #define DPRINTF(x) do { } while (0/*CONSTCOND*/) 132 #endif 133 134 extern struct cfdriver spiflash_cd; 135 136 dev_type_open(spiflash_open); 137 dev_type_close(spiflash_close); 138 dev_type_read(spiflash_read); 139 dev_type_write(spiflash_write); 140 dev_type_ioctl(spiflash_ioctl); 141 dev_type_strategy(spiflash_strategy); 142 143 const struct bdevsw spiflash_bdevsw = { 144 .d_open = spiflash_open, 145 .d_close = spiflash_close, 146 .d_strategy = spiflash_strategy, 147 .d_ioctl = spiflash_ioctl, 148 .d_dump = nodump, 149 .d_psize = nosize, 150 .d_flag = D_DISK, 151 }; 152 153 const struct cdevsw spiflash_cdevsw = { 154 .d_open = spiflash_open, 155 .d_close = spiflash_close, 156 .d_read = spiflash_read, 157 .d_write = spiflash_write, 158 .d_ioctl = spiflash_ioctl, 159 .d_stop = nostop, 160 .d_tty = notty, 161 .d_poll = nopoll, 162 .d_mmap = nommap, 163 .d_kqfilter = nokqfilter, 164 .d_flag = D_DISK, 165 }; 166 167 static struct dkdriver spiflash_dkdriver = { spiflash_strategy, NULL }; 168 169 spiflash_handle_t 170 spiflash_attach_mi(const struct spiflash_hw_if *hw, void *cookie, 171 device_t dev) 172 { 173 struct spiflash_attach_args sfa; 174 sfa.hw = hw; 175 sfa.cookie = cookie; 176 177 return (spiflash_handle_t)config_found(dev, &sfa, spiflash_print); 178 } 179 180 int 181 spiflash_print(void *aux, const char *pnp) 182 { 183 if (pnp != NULL) 184 printf("spiflash at %s\n", pnp); 185 186 return UNCONF; 187 } 188 189 int 190 spiflash_match(device_t parent, cfdata_t cf, void *aux) 191 { 192 193 return 1; 194 } 195 196 void 197 spiflash_attach(device_t parent, device_t self, void *aux) 198 { 199 struct spiflash_softc *sc = device_private(self); 200 struct spiflash_attach_args *sfa = aux; 201 void *cookie = sfa->cookie; 202 203 sc->sc_hw = *sfa->hw; 204 sc->sc_cookie = cookie; 205 sc->sc_name = sc->sc_getname(cookie); 206 sc->sc_handle = sc->sc_gethandle(cookie); 207 sc->sc_device_size = sc->sc_getsize(cookie, SPIFLASH_SIZE_DEVICE); 208 sc->sc_erase_size = sc->sc_getsize(cookie, SPIFLASH_SIZE_ERASE); 209 sc->sc_write_size = sc->sc_getsize(cookie, SPIFLASH_SIZE_WRITE); 210 sc->sc_read_size = sc->sc_getsize(cookie, SPIFLASH_SIZE_READ); 211 sc->sc_device_blks = sc->sc_device_size / DEV_BSIZE; 212 213 if (sc->sc_read == NULL) 214 sc->sc_read = spiflash_common_read; 215 if (sc->sc_write == NULL) 216 sc->sc_write = spiflash_common_write; 217 if (sc->sc_erase == NULL) 218 sc->sc_erase = spiflash_common_erase; 219 220 aprint_naive(": SPI flash\n"); 221 aprint_normal(": %s SPI flash\n", sc->sc_name); 222 /* XXX: note that this has to change for boot-sectored flash */ 223 aprint_normal_dev(self, "%d KB, %d sectors of %d KB each\n", 224 sc->sc_device_size / 1024, 225 sc->sc_device_size / sc->sc_erase_size, 226 sc->sc_erase_size / 1024); 227 228 /* first-come first-served strategy works best for us */ 229 bufq_alloc(&sc->sc_waitq, "fcfs", BUFQ_SORT_RAWBLOCK); 230 bufq_alloc(&sc->sc_workq, "fcfs", BUFQ_SORT_RAWBLOCK); 231 bufq_alloc(&sc->sc_doneq, "fcfs", BUFQ_SORT_RAWBLOCK); 232 233 sc->sc_dk.dk_driver = &spiflash_dkdriver; 234 sc->sc_dk.dk_name = device_xname(self); 235 236 disk_attach(&sc->sc_dk); 237 238 /* arrange to allocate the kthread */ 239 kthread_create(PRI_NONE, 0, NULL, spiflash_thread, sc, 240 &sc->sc_thread, "spiflash"); 241 } 242 243 int 244 spiflash_open(dev_t dev, int flags, int mode, struct lwp *l) 245 { 246 spiflash_handle_t sc; 247 248 sc = device_lookup_private(&spiflash_cd, DISKUNIT(dev)); 249 if (sc == NULL) 250 return ENXIO; 251 252 /* 253 * XXX: We need to handle partitions here. The problem is 254 * that it isn't entirely clear to me how to deal with this. 255 * There are devices that could be used "in the raw" with a 256 * NetBSD label, but then you get into devices that have other 257 * kinds of data on them -- some have VxWorks data, some have 258 * RedBoot data, and some have other contraints -- for example 259 * some devices might have a portion that is read-only, 260 * whereas others might have a portion that is read-write. 261 * 262 * For now we just permit access to the entire device. 263 */ 264 return 0; 265 } 266 267 int 268 spiflash_close(dev_t dev, int flags, int mode, struct lwp *l) 269 { 270 spiflash_handle_t sc; 271 272 sc = device_lookup_private(&spiflash_cd, DISKUNIT(dev)); 273 if (sc == NULL) 274 return ENXIO; 275 276 return 0; 277 } 278 279 int 280 spiflash_read(dev_t dev, struct uio *uio, int ioflag) 281 { 282 283 return physio(spiflash_strategy, NULL, dev, B_READ, minphys, uio); 284 } 285 286 int 287 spiflash_write(dev_t dev, struct uio *uio, int ioflag) 288 { 289 290 return physio(spiflash_strategy, NULL, dev, B_WRITE, minphys, uio); 291 } 292 293 int 294 spiflash_ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 295 { 296 spiflash_handle_t sc; 297 298 sc = device_lookup_private(&spiflash_cd, DISKUNIT(dev)); 299 if (sc == NULL) 300 return ENXIO; 301 302 return EINVAL; 303 } 304 305 void 306 spiflash_strategy(struct buf *bp) 307 { 308 spiflash_handle_t sc; 309 int s; 310 311 sc = device_lookup_private(&spiflash_cd, DISKUNIT(bp->b_dev)); 312 if (sc == NULL) { 313 bp->b_error = ENXIO; 314 biodone(bp); 315 return; 316 } 317 318 if (((bp->b_bcount % sc->sc_write_size) != 0) || 319 (bp->b_blkno < 0)) { 320 bp->b_error = EINVAL; 321 biodone(bp); 322 return; 323 } 324 325 /* no work? */ 326 if (bp->b_bcount == 0) { 327 biodone(bp); 328 return; 329 } 330 331 if (bounds_check_with_mediasize(bp, DEV_BSIZE, 332 sc->sc_device_blks) <= 0) { 333 biodone(bp); 334 return; 335 } 336 337 bp->b_resid = bp->b_bcount; 338 339 /* all ready, hand off to thread for async processing */ 340 s = splbio(); 341 bufq_put(sc->sc_waitq, bp); 342 wakeup(&sc->sc_thread); 343 splx(s); 344 } 345 346 void 347 spiflash_process_done(spiflash_handle_t sc, int err) 348 { 349 struct buf *bp; 350 int cnt = 0; 351 int flag = 0; 352 353 while ((bp = bufq_get(sc->sc_doneq)) != NULL) { 354 flag = bp->b_flags & B_READ; 355 if ((bp->b_error = err) == 0) 356 bp->b_resid = 0; 357 cnt += bp->b_bcount - bp->b_resid; 358 biodone(bp); 359 } 360 disk_unbusy(&sc->sc_dk, cnt, flag); 361 } 362 363 void 364 spiflash_process_read(spiflash_handle_t sc) 365 { 366 struct buf *bp; 367 int err = 0; 368 369 disk_busy(&sc->sc_dk); 370 while ((bp = bufq_get(sc->sc_workq)) != NULL) { 371 size_t addr = bp->b_blkno * DEV_BSIZE; 372 uint8_t *data = bp->b_data; 373 int cnt = bp->b_resid; 374 375 bufq_put(sc->sc_doneq, bp); 376 377 DPRINTF(("read from addr %x, cnt %d\n", (unsigned)addr, cnt)); 378 379 if ((err = sc->sc_read(sc, addr, cnt, data)) != 0) { 380 /* error occurred, fail all pending workq bufs */ 381 bufq_move(sc->sc_doneq, sc->sc_workq); 382 break; 383 } 384 385 bp->b_resid -= cnt; 386 data += cnt; 387 addr += cnt; 388 } 389 spiflash_process_done(sc, err); 390 } 391 392 void 393 spiflash_process_write(spiflash_handle_t sc) 394 { 395 int len; 396 size_t base; 397 daddr_t blkno; 398 uint8_t *save; 399 int err = 0, neederase = 0; 400 struct buf *bp; 401 402 /* 403 * due to other considerations, we are guaranteed that 404 * we will only have multiple buffers if they are all in 405 * the same erase sector. Therefore we never need to look 406 * beyond the first block to determine how much data we need 407 * to save. 408 */ 409 410 bp = bufq_peek(sc->sc_workq); 411 len = spiflash_nsectors(sc, bp) * sc->sc_erase_size; 412 blkno = bp->b_blkno; 413 base = (blkno * DEV_BSIZE) & ~ (sc->sc_erase_size - 1); 414 415 /* get ourself a scratch buffer */ 416 save = malloc(len, M_DEVBUF, M_WAITOK); 417 418 disk_busy(&sc->sc_dk); 419 /* read in as much of the data as we need */ 420 DPRINTF(("reading in %d bytes\n", len)); 421 if ((err = sc->sc_read(sc, base, len, save)) != 0) { 422 bufq_move(sc->sc_doneq, sc->sc_workq); 423 spiflash_process_done(sc, err); 424 return; 425 } 426 427 /* 428 * now coalesce the writes into the save area, but also 429 * check to see if we need to do an erase 430 */ 431 while ((bp = bufq_get(sc->sc_workq)) != NULL) { 432 uint8_t *data, *dst; 433 int resid = bp->b_resid; 434 435 DPRINTF(("coalesce write, blkno %x, count %d, resid %d\n", 436 (unsigned)bp->b_blkno, bp->b_bcount, resid)); 437 438 data = bp->b_data; 439 dst = save + (bp->b_blkno - blkno) * DEV_BSIZE; 440 441 /* 442 * NOR flash bits. We can clear a bit, but we cannot 443 * set a bit, without erasing. This should help reduce 444 * unnecessary erases. 445 */ 446 while (resid) { 447 if ((*data) & ~(*dst)) 448 neederase = 1; 449 *dst++ = *data++; 450 resid--; 451 } 452 453 bufq_put(sc->sc_doneq, bp); 454 } 455 456 /* 457 * do the erase, if we need to. 458 */ 459 if (neederase) { 460 DPRINTF(("erasing from %x - %x\n", base, base + len)); 461 if ((err = sc->sc_erase(sc, base, len)) != 0) { 462 spiflash_process_done(sc, err); 463 return; 464 } 465 } 466 467 /* 468 * now write our save area, and finish up. 469 */ 470 DPRINTF(("flashing %d bytes to %x from %x\n", len, 471 base, (unsigned)save)); 472 err = sc->sc_write(sc, base, len, save); 473 spiflash_process_done(sc, err); 474 } 475 476 477 int 478 spiflash_nsectors(spiflash_handle_t sc, struct buf *bp) 479 { 480 unsigned addr, sector; 481 482 addr = bp->b_blkno * DEV_BSIZE; 483 sector = addr / sc->sc_erase_size; 484 485 addr += bp->b_bcount; 486 addr--; 487 return (((addr / sc->sc_erase_size) - sector) + 1); 488 } 489 490 int 491 spiflash_sector(spiflash_handle_t sc, struct buf *bp) 492 { 493 unsigned addr, sector; 494 495 addr = bp->b_blkno * DEV_BSIZE; 496 sector = addr / sc->sc_erase_size; 497 498 /* if it spans multiple blocks, error it */ 499 addr += bp->b_bcount; 500 addr--; 501 if (sector != (addr / sc->sc_erase_size)) 502 return -1; 503 504 return sector; 505 } 506 507 void 508 spiflash_thread(void *arg) 509 { 510 spiflash_handle_t sc = arg; 511 struct buf *bp; 512 int s; 513 int sector; 514 515 s = splbio(); 516 for (;;) { 517 if ((bp = bufq_get(sc->sc_waitq)) == NULL) { 518 tsleep(&sc->sc_thread, PRIBIO, "spiflash_thread", 0); 519 continue; 520 } 521 522 bufq_put(sc->sc_workq, bp); 523 524 if (bp->b_flags & B_READ) { 525 /* just do the read */ 526 spiflash_process_read(sc); 527 continue; 528 } 529 530 /* 531 * Because writing a flash filesystem is particularly 532 * painful, involving erase, modify, write, we prefer 533 * to coalesce writes to the same sector together. 534 */ 535 536 sector = spiflash_sector(sc, bp); 537 538 /* 539 * if the write spans multiple sectors, skip 540 * coalescing. (It would be nice if we could break 541 * these up. minphys is honored for read/write, but 542 * not necessarily for bread.) 543 */ 544 if (sector < 0) 545 goto dowrite; 546 547 while ((bp = bufq_peek(sc->sc_waitq)) != NULL) { 548 /* can't deal with read requests! */ 549 if (bp->b_flags & B_READ) 550 break; 551 552 /* is it for the same sector? */ 553 if (spiflash_sector(sc, bp) != sector) 554 break; 555 556 bp = bufq_get(sc->sc_waitq); 557 bufq_put(sc->sc_workq, bp); 558 } 559 560 dowrite: 561 spiflash_process_write(sc); 562 } 563 } 564 /* 565 * SPI flash common implementation. 566 */ 567 568 /* 569 * Most devices take on the order of 1 second for each block that they 570 * delete. 571 */ 572 int 573 spiflash_common_erase(spiflash_handle_t sc, size_t start, size_t size) 574 { 575 int rv; 576 577 if ((start % sc->sc_erase_size) || (size % sc->sc_erase_size)) 578 return EINVAL; 579 580 /* the second test is to test against wrap */ 581 if ((start > sc->sc_device_size) || 582 ((start + size) > sc->sc_device_size)) 583 return EINVAL; 584 585 /* 586 * XXX: check protection status? Requires master table mapping 587 * sectors to status bits, and so forth. 588 */ 589 590 while (size) { 591 if ((rv = spiflash_write_enable(sc)) != 0) { 592 spiflash_write_disable(sc); 593 return rv; 594 } 595 if ((rv = spiflash_cmd(sc, SPIFLASH_CMD_ERASE, 3, start, 0, 596 NULL, NULL)) != 0) { 597 spiflash_write_disable(sc); 598 return rv; 599 } 600 601 /* 602 * The devices I have all say typical for sector erase 603 * is ~1sec. We check ten times that often. (There 604 * is no way to interrupt on this.) 605 */ 606 if ((rv = spiflash_wait(sc, hz / 10)) != 0) 607 return rv; 608 609 start += sc->sc_erase_size; 610 size -= sc->sc_erase_size; 611 612 /* NB: according to the docs I have, the write enable 613 * is automatically cleared upon completion of an erase 614 * command, so there is no need to explicitly disable it. 615 */ 616 } 617 618 return 0; 619 } 620 621 int 622 spiflash_common_write(spiflash_handle_t sc, size_t start, size_t size, 623 const uint8_t *data) 624 { 625 int rv; 626 627 if ((start % sc->sc_write_size) || (size % sc->sc_write_size)) 628 return EINVAL; 629 630 while (size) { 631 int cnt; 632 633 if ((rv = spiflash_write_enable(sc)) != 0) { 634 spiflash_write_disable(sc); 635 return rv; 636 } 637 638 cnt = min(size, sc->sc_write_size); 639 if ((rv = spiflash_cmd(sc, SPIFLASH_CMD_PROGRAM, 3, start, 640 cnt, data, NULL)) != 0) { 641 spiflash_write_disable(sc); 642 return rv; 643 } 644 645 /* 646 * It seems that most devices can write bits fairly 647 * quickly. For example, one part I have access to 648 * takes ~5msec to process the entire 256 byte page. 649 * Probably this should be modified to cope with 650 * device-specific timing, and maybe also take into 651 * account systems with higher values of HZ (which 652 * could benefit from sleeping.) 653 */ 654 if ((rv = spiflash_wait(sc, 0)) != 0) 655 return rv; 656 657 data += cnt; 658 start += cnt; 659 size -= cnt; 660 } 661 662 return 0; 663 } 664 665 int 666 spiflash_common_read(spiflash_handle_t sc, size_t start, size_t size, 667 uint8_t *data) 668 { 669 int rv; 670 671 while (size) { 672 int cnt; 673 674 if (sc->sc_read_size > 0) 675 cnt = min(size, sc->sc_read_size); 676 else 677 cnt = size; 678 679 if ((rv = spiflash_cmd(sc, SPIFLASH_CMD_READ, 3, start, 680 cnt, NULL, data)) != 0) { 681 return rv; 682 } 683 684 start += cnt; 685 size -= cnt; 686 } 687 688 return 0; 689 } 690 691 /* read status register */ 692 int 693 spiflash_read_status(spiflash_handle_t sc, uint8_t *sr) 694 { 695 696 return spiflash_cmd(sc, SPIFLASH_CMD_RDSR, 0, 0, 1, NULL, sr); 697 } 698 699 int 700 spiflash_write_enable(spiflash_handle_t sc) 701 { 702 703 return spiflash_cmd(sc, SPIFLASH_CMD_WREN, 0, 0, 0, NULL, NULL); 704 } 705 706 int 707 spiflash_write_disable(spiflash_handle_t sc) 708 { 709 710 return spiflash_cmd(sc, SPIFLASH_CMD_WRDI, 0, 0, 0, NULL, NULL); 711 } 712 713 int 714 spiflash_cmd(spiflash_handle_t sc, uint8_t cmd, 715 size_t addrlen, uint32_t addr, 716 size_t cnt, const uint8_t *wdata, uint8_t *rdata) 717 { 718 struct spi_transfer trans; 719 struct spi_chunk chunk1, chunk2; 720 char buf[4]; 721 int i; 722 723 buf[0] = cmd; 724 725 if (addrlen > 3) 726 return EINVAL; 727 728 for (i = addrlen; i > 0; i--) { 729 buf[i] = addr & 0xff; 730 addr >>= 8; 731 } 732 spi_transfer_init(&trans); 733 spi_chunk_init(&chunk1, addrlen + 1, buf, NULL); 734 spi_transfer_add(&trans, &chunk1); 735 if (cnt) { 736 spi_chunk_init(&chunk2, cnt, wdata, rdata); 737 spi_transfer_add(&trans, &chunk2); 738 } 739 740 spi_transfer(sc->sc_handle, &trans); 741 spi_wait(&trans); 742 743 if (trans.st_flags & SPI_F_ERROR) 744 return trans.st_errno; 745 return 0; 746 } 747 748 int 749 spiflash_wait(spiflash_handle_t sc, int tmo) 750 { 751 int rv; 752 uint8_t sr; 753 754 for (;;) { 755 if ((rv = spiflash_read_status(sc, &sr)) != 0) 756 return rv; 757 758 if ((sr & SPIFLASH_SR_BUSY) == 0) 759 break; 760 /* 761 * The devices I have all say typical for sector 762 * erase is ~1sec. We check time times that often. 763 * (There is no way to interrupt on this.) 764 */ 765 if (tmo) 766 tsleep(&sr, PWAIT, "spiflash_wait", tmo); 767 } 768 return 0; 769 } 770