1 /* $NetBSD: pxg.c,v 1.10 2002/03/17 19:41:02 atatat Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Driver for DEC PixelStamp graphics accelerators with onboard SRAM and 41 * Intel i860 co-processor (PMAG-D, E and F). 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: pxg.c,v 1.10 2002/03/17 19:41:02 atatat Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/device.h> 50 #include <sys/malloc.h> 51 #include <sys/callout.h> 52 #include <sys/proc.h> 53 54 #if defined(pmax) 55 #include <mips/cpuregs.h> 56 #elif defined(alpha) 57 #include <alpha/alpha_cpu.h> 58 #endif 59 60 #include <machine/autoconf.h> 61 #include <machine/cpu.h> 62 #include <machine/bus.h> 63 64 #include <dev/cons.h> 65 66 #include <dev/wscons/wsconsio.h> 67 #include <dev/wscons/wsdisplayvar.h> 68 69 #include <dev/ic/bt459reg.h> 70 71 #include <dev/tc/tcvar.h> 72 #include <dev/tc/sticreg.h> 73 #include <dev/tc/sticio.h> 74 #include <dev/tc/sticvar.h> 75 #include <dev/tc/pxgvar.h> 76 77 #define PXG_STIC_POLL_OFFSET 0x000000 /* STIC DMA poll space */ 78 #define PXG_STAMP_OFFSET 0x0c0000 /* pixelstamp space on STIC */ 79 #define PXG_STIC_OFFSET 0x180000 /* STIC registers */ 80 #define PXG_SRAM_OFFSET 0x200000 /* 128 or 256kB of SRAM */ 81 #define PXG_HOST_INTR_OFFSET 0x280000 /* i860 host interrupt */ 82 #define PXG_COPROC_INTR_OFFSET 0x2c0000 /* i860 coprocessor interrupt */ 83 #define PXG_VDAC_OFFSET 0x300000 /* VDAC registers (bt459) */ 84 #define PXG_VDAC_RESET_OFFSET 0x340000 /* VDAC reset register */ 85 #define PXG_ROM_OFFSET 0x380000 /* ROM code */ 86 #define PXG_I860_START_OFFSET 0x380000 /* i860 start register */ 87 #define PXG_I860_RESET_OFFSET 0x3c0000 /* i860 stop register */ 88 89 void pxg_attach(struct device *, struct device *, void *); 90 int pxg_intr(void *); 91 int pxg_match(struct device *, struct cfdata *, void *); 92 93 void pxg_init(struct stic_info *); 94 int pxg_ioctl(struct stic_info *, u_long, caddr_t, int, struct proc *); 95 u_int32_t *pxg_pbuf_get(struct stic_info *); 96 int pxg_pbuf_post(struct stic_info *, u_int32_t *); 97 int pxg_probe_planes(struct stic_info *); 98 int pxg_probe_sram(struct stic_info *); 99 100 void pxg_cnattach(tc_addr_t); 101 102 struct pxg_softc { 103 struct device pxg_dv; 104 struct stic_info *pxg_si; 105 }; 106 107 struct cfattach pxg_ca = { 108 sizeof(struct pxg_softc), pxg_match, pxg_attach 109 }; 110 111 static const char *pxg_types[] = { 112 "PMAG-DA ", 113 "PMAG-FA ", 114 "PMAG-FB ", 115 "PMAGB-FA", 116 "PMAGB-FB", 117 }; 118 119 int 120 pxg_match(struct device *parent, struct cfdata *match, void *aux) 121 { 122 struct tc_attach_args *ta; 123 int i; 124 125 ta = aux; 126 127 for (i = 0; i < sizeof(pxg_types) / sizeof(pxg_types[0]); i++) 128 if (strncmp(pxg_types[i], ta->ta_modname, TC_ROM_LLEN) == 0) 129 return (1); 130 131 return (0); 132 } 133 134 void 135 pxg_attach(struct device *parent, struct device *self, void *aux) 136 { 137 struct stic_info *si; 138 struct tc_attach_args *ta; 139 struct pxg_softc *pxg; 140 int console; 141 142 pxg = (struct pxg_softc *)self; 143 ta = (struct tc_attach_args *)aux; 144 145 if (ta->ta_addr == stic_consinfo.si_slotbase) { 146 si = &stic_consinfo; 147 console = 1; 148 } else { 149 if (stic_consinfo.si_slotbase == NULL) 150 si = &stic_consinfo; 151 else { 152 si = malloc(sizeof(*si), M_DEVBUF, M_NOWAIT|M_ZERO); 153 } 154 si->si_slotbase = ta->ta_addr; 155 pxg_init(si); 156 console = 0; 157 } 158 159 pxg->pxg_si = si; 160 si->si_dv = self; 161 tc_intr_establish(parent, ta->ta_cookie, IPL_TTY, pxg_intr, si); 162 163 printf(": %d plane, %dx%d stamp, %dkB SRAM\n", si->si_depth, 164 si->si_stampw, si->si_stamph, (int)si->si_buf_size >> 10); 165 166 stic_attach(self, si, console); 167 168 #ifdef notyet 169 /* Load the co-processor "firmware". */ 170 for (i = 0; i < sizeof(pxg_fwsegs) / sizeof(pxg_fwsegs[0]); i++) 171 pxg_load_fwseg(si, &pxg_fwsegs[i]); 172 173 /* Start the i860. */ 174 si->si_slotbase[PXG_I860_START_OFFSET >> 2] = 1; 175 tc_wmb(); 176 tc_syncbus(); 177 DELAY(40000); 178 #endif 179 } 180 181 void 182 pxg_cnattach(tc_addr_t addr) 183 { 184 struct stic_info *si; 185 186 si = &stic_consinfo; 187 si->si_slotbase = addr; 188 pxg_init(si); 189 stic_cnattach(si); 190 } 191 192 void 193 pxg_init(struct stic_info *si) 194 { 195 volatile u_int32_t *slot; 196 caddr_t kva; 197 198 kva = (caddr_t)si->si_slotbase; 199 200 si->si_vdac = (u_int32_t *)(kva + PXG_VDAC_OFFSET); 201 si->si_vdac_reset = (u_int32_t *)(kva + PXG_VDAC_RESET_OFFSET); 202 si->si_stic = (volatile struct stic_regs *)(kva + PXG_STIC_OFFSET); 203 si->si_stamp = (u_int32_t *)(kva + PXG_STAMP_OFFSET); 204 si->si_buf = (u_int32_t *)(kva + PXG_SRAM_OFFSET); 205 si->si_buf_phys = STIC_KSEG_TO_PHYS(si->si_buf); 206 si->si_buf_size = pxg_probe_sram(si); 207 si->si_disptype = WSDISPLAY_TYPE_PXG; 208 si->si_sxc = (volatile struct stic_xcomm *)si->si_buf; 209 210 si->si_pbuf_get = pxg_pbuf_get; 211 si->si_pbuf_post = pxg_pbuf_post; 212 si->si_ioctl = pxg_ioctl; 213 214 /* Disable the co-processor. */ 215 slot = (volatile u_int32_t *)kva; 216 slot[PXG_I860_RESET_OFFSET >> 2] = 0; 217 tc_wmb(); 218 slot[PXG_HOST_INTR_OFFSET >> 2] = 0; 219 tc_wmb(); 220 tc_syncbus(); 221 DELAY(40000); 222 223 /* XXX Check for a second PixelStamp. */ 224 if (((si->si_stic->sr_modcl & 0x600) >> 9) > 1) 225 si->si_depth = 24; 226 else 227 si->si_depth = pxg_probe_planes(si); 228 229 stic_init(si); 230 } 231 232 int 233 pxg_probe_sram(struct stic_info *si) 234 { 235 volatile u_int32_t *a, *b; 236 237 a = (volatile u_int32_t *)si->si_slotbase + (PXG_SRAM_OFFSET >> 2); 238 b = a + (0x20000 >> 2); 239 *a = 4321; 240 *b = 1234; 241 tc_mb(); 242 return ((*a == *b) ? 0x20000 : 0x40000); 243 } 244 245 int 246 pxg_probe_planes(struct stic_info *si) 247 { 248 volatile u_int32_t *vdac; 249 int id; 250 251 /* 252 * For the visible framebuffer (# 0), we can cheat and use the VDAC 253 * ID. 254 */ 255 vdac = si->si_vdac; 256 vdac[BT459_REG_ADDR_LOW] = (BT459_IREG_ID & 0xff) | 257 ((BT459_IREG_ID & 0xff) << 8) | ((BT459_IREG_ID & 0xff) << 16); 258 vdac[BT459_REG_ADDR_HIGH] = ((BT459_IREG_ID & 0xff00) >> 8) | 259 (BT459_IREG_ID & 0xff00) | ((BT459_IREG_ID & 0xff00) << 8); 260 tc_mb(); 261 id = vdac[BT459_REG_IREG_DATA] & 0x00ffffff; 262 263 /* 3 VDACs */ 264 if (id == 0x004a4a4a) 265 return (24); 266 267 /* 1 VDAC */ 268 if ((id & 0xff0000) == 0x4a0000 || (id & 0x00ff00) == 0x004a00 || 269 (id & 0x0000ff) == 0x00004a) 270 return (8); 271 272 /* XXX Assume 8 planes. */ 273 printf("pxg_probe_planes: invalid VDAC ID %x\n", id); 274 return (8); 275 } 276 277 int 278 pxg_intr(void *cookie) 279 { 280 #ifdef notyet 281 struct stic_info *si; 282 volatile struct stic_regs *sr; 283 volatile u_int32_t *hi; 284 u_int32_t state; 285 int it; 286 287 si = cookie; 288 sr = si->si_stic; 289 state = sr->sr_ipdvint; 290 hi = (volatile u_int32_t *)si->si_slotbase + 291 (PXG_HOST_INTR_OFFSET / sizeof(u_int32_t)); 292 293 /* Clear the interrupt condition */ 294 it = hi[0] & 15; 295 hi[0] = 0; 296 tc_wmb(); 297 hi[2] = 0; 298 tc_wmb(); 299 300 switch (it) { 301 case 3: 302 sr->sr_ipdvint = STIC_INT_V_WE | STIC_INT_V_EN; 303 tc_wmb(); 304 stic_flush(si); 305 break; 306 } 307 #else 308 printf("pxg_intr: how did this happen?\n"); 309 #endif 310 return (1); 311 } 312 313 u_int32_t * 314 pxg_pbuf_get(struct stic_info *si) 315 { 316 u_long off; 317 318 si->si_pbuf_select ^= STIC_PACKET_SIZE; 319 off = si->si_pbuf_select + STIC_XCOMM_SIZE; 320 return ((u_int32_t *)((caddr_t)si->si_buf + off)); 321 } 322 323 int 324 pxg_pbuf_post(struct stic_info *si, u_int32_t *buf) 325 { 326 volatile u_int32_t *poll, junk; 327 volatile struct stic_regs *sr; 328 u_long v; 329 int c; 330 331 sr = si->si_stic; 332 333 /* Get address of poll register for this buffer. */ 334 v = ((u_long)buf - (u_long)si->si_buf) >> 9; 335 poll = (volatile u_int32_t *)((caddr_t)si->si_slotbase + v); 336 337 /* 338 * Read the poll register and make sure the stamp wants to accept 339 * our packet. This read will initiate the DMA. Don't wait for 340 * ever, just in case something's wrong. 341 */ 342 tc_mb(); 343 344 for (c = STAMP_RETRIES; c != 0; c--) { 345 if ((sr->sr_ipdvint & STIC_INT_P) != 0) { 346 sr->sr_ipdvint = STIC_INT_P_WE; 347 tc_wmb(); 348 junk = *poll; 349 return (0); 350 } 351 DELAY(STAMP_DELAY); 352 } 353 354 /* STIC has lost the plot, punish it. */ 355 stic_reset(si); 356 return (-1); 357 } 358 359 int 360 pxg_ioctl(struct stic_info *si, u_long cmd, caddr_t data, int flag, 361 struct proc *p) 362 { 363 struct stic_xinfo *sxi; 364 volatile u_int32_t *ptr; 365 int rv, s; 366 367 switch (cmd) { 368 case STICIO_START860: 369 case STICIO_RESET860: 370 if ((rv = suser(p->p_ucred, &p->p_acflag)) != 0) 371 return (rv); 372 if (si->si_dispmode != WSDISPLAYIO_MODE_MAPPED) 373 return (EBUSY); 374 ptr = (volatile u_int32_t *)si->si_slotbase; 375 break; 376 } 377 378 switch (cmd) { 379 case STICIO_START860: 380 s = spltty(); 381 ptr[PXG_I860_START_OFFSET >> 2] = 1; 382 tc_wmb(); 383 splx(s); 384 rv = 0; 385 break; 386 387 case STICIO_RESET860: 388 s = spltty(); 389 ptr[PXG_I860_RESET_OFFSET >> 2] = 0; 390 tc_wmb(); 391 splx(s); 392 rv = 0; 393 break; 394 395 case STICIO_GXINFO: 396 sxi = (struct stic_xinfo *)data; 397 sxi->sxi_unit = si->si_unit; 398 sxi->sxi_stampw = si->si_stampw; 399 sxi->sxi_stamph = si->si_stamph; 400 sxi->sxi_buf_size = si->si_buf_size; 401 sxi->sxi_buf_phys = 0; 402 sxi->sxi_buf_pktoff = STIC_XCOMM_SIZE; 403 sxi->sxi_buf_pktcnt = 2; 404 sxi->sxi_buf_imgoff = STIC_XCOMM_SIZE + STIC_PACKET_SIZE * 2; 405 rv = 0; 406 break; 407 408 default: 409 rv = EPASSTHROUGH; 410 break; 411 } 412 413 return (rv); 414 } 415 416 #ifdef notyet 417 void 418 pxg_load_fwseg(struct stic_info *si, struct pxg_fwseg *pfs) 419 { 420 const u_int32_t *src; 421 u_int32_t *dst; 422 u_int left, i; 423 424 dst = (u_int32_t *)((caddr_t)si->si_buf + pfs->pfs_addr); 425 src = pfs->pfs_data; 426 427 for (left = pfs->pfs_compsize; left != 0; left -= 4) { 428 if (src[0] == PXGFW_RLE_MAGIC) { 429 for (i = src[2]; i != 0; i--) 430 *dst++ = src[1]; 431 src += 3; 432 } else { 433 *dst++ = src[0]; 434 src++; 435 } 436 } 437 438 if (src == NULL) 439 memset(dst, 0, pfs->pfs_realsize); 440 } 441 #endif 442