1 /* $NetBSD: if_auereg.h,v 1.16 2001/10/10 02:14:17 augustss Exp $ */ 2 /* 3 * Copyright (c) 1997, 1998, 1999 4 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/usb/if_auereg.h,v 1.2 2000/01/08 06:52:36 wpaul Exp $ 34 */ 35 36 /* 37 * Register definitions for ADMtek Pegasus AN986 USB to Ethernet 38 * chip. The Pegasus uses a total of four USB endpoints: the control 39 * endpoint (0), a bulk read endpoint for receiving packets (1), 40 * a bulk write endpoint for sending packets (2) and an interrupt 41 * endpoint for passing RX and TX status (3). Endpoint 0 is used 42 * to read and write the ethernet module's registers. All registers 43 * are 8 bits wide. 44 * 45 * Packet transfer is done in 64 byte chunks. The last chunk in a 46 * transfer is denoted by having a length less that 64 bytes. For 47 * the RX case, the data includes an optional RX status word. 48 */ 49 50 #define AUE_UR_READREG 0xF0 51 #define AUE_UR_WRITEREG 0xF1 52 53 #define AUE_CONFIG_NO 1 54 #define AUE_IFACE_IDX 0 55 56 /* 57 * Note that while the ADMtek technically has four 58 * endpoints, the control endpoint (endpoint 0) is 59 * regarded as special by the USB code and drivers 60 * don't have direct access to it. (We access it 61 * using usbd_do_request() when reading/writing 62 * registers.) Consequently, our endpoint indexes 63 * don't match those in the ADMtek Pegasus manual: 64 * we consider the RX data endpoint to be index 0 65 * and work up from there. 66 */ 67 #define AUE_ENDPT_RX 0x0 68 #define AUE_ENDPT_TX 0x1 69 #define AUE_ENDPT_INTR 0x2 70 #define AUE_ENDPT_MAX 0x3 71 72 #define AUE_CTL0 0x00 73 #define AUE_CTL1 0x01 74 #define AUE_CTL2 0x02 75 #define AUE_MAR0 0x08 76 #define AUE_MAR1 0x09 77 #define AUE_MAR2 0x0A 78 #define AUE_MAR3 0x0B 79 #define AUE_MAR4 0x0C 80 #define AUE_MAR5 0x0D 81 #define AUE_MAR6 0x0E 82 #define AUE_MAR7 0x0F 83 #define AUE_MAR AUE_MAR0 84 #define AUE_PAR0 0x10 85 #define AUE_PAR1 0x11 86 #define AUE_PAR2 0x12 87 #define AUE_PAR3 0x13 88 #define AUE_PAR4 0x14 89 #define AUE_PAR5 0x15 90 #define AUE_PAR AUE_PAR0 91 #define AUE_PAUSE0 0x18 92 #define AUE_PAUSE1 0x19 93 #define AUE_PAUSE AUE_PAUSE0 94 #define AUE_RX_FLOWCTL_CNT 0x1A 95 #define AUE_RX_FLOWCTL_FIFO 0x1B 96 #define AUE_REG_1D 0x1D 97 #define AUE_EE_REG 0x20 98 #define AUE_EE_DATA0 0x21 99 #define AUE_EE_DATA1 0x22 100 #define AUE_EE_DATA AUE_EE_DATA0 101 #define AUE_EE_CTL 0x23 102 #define AUE_PHY_ADDR 0x25 103 #define AUE_PHY_DATA0 0x26 104 #define AUE_PHY_DATA1 0x27 105 #define AUE_PHY_DATA AUE_PHY_DATA0 106 #define AUE_PHY_CTL 0x28 107 #define AUE_USB_STS 0x2A 108 #define AUE_TXSTAT0 0x2B 109 #define AUE_TXSTAT1 0x2C 110 #define AUE_TXSTAT AUE_TXSTAT0 111 #define AUE_RXSTAT 0x2D 112 #define AUE_PKTLOST0 0x2E 113 #define AUE_PKTLOST1 0x2F 114 #define AUE_PKTLOST AUE_PKTLOST0 115 116 #define AUE_REG_7B 0x7B 117 #define AUE_GPIO0 0x7E 118 #define AUE_GPIO1 0x7F 119 #define AUE_REG_81 0x81 120 121 #define AUE_CTL0_INCLUDE_RXCRC 0x01 122 #define AUE_CTL0_ALLMULTI 0x02 123 #define AUE_CTL0_STOP_BACKOFF 0x04 124 #define AUE_CTL0_RXSTAT_APPEND 0x08 125 #define AUE_CTL0_WAKEON_ENB 0x10 126 #define AUE_CTL0_RXPAUSE_ENB 0x20 127 #define AUE_CTL0_RX_ENB 0x40 128 #define AUE_CTL0_TX_ENB 0x80 129 130 #define AUE_CTL1_HOMELAN 0x04 131 #define AUE_CTL1_RESETMAC 0x08 132 #define AUE_CTL1_SPEEDSEL 0x10 /* 0 = 10mbps, 1 = 100mbps */ 133 #define AUE_CTL1_DUPLEX 0x20 /* 0 = half, 1 = full */ 134 #define AUE_CTL1_DELAYHOME 0x40 135 136 #define AUE_CTL2_EP3_CLR 0x01 /* reading EP3 clrs status regs */ 137 #define AUE_CTL2_RX_BADFRAMES 0x02 138 #define AUE_CTL2_RX_PROMISC 0x04 139 #define AUE_CTL2_LOOPBACK 0x08 140 #define AUE_CTL2_EEPROMWR_ENB 0x10 141 #define AUE_CTL2_EEPROM_LOAD 0x20 142 143 #define AUE_EECTL_WRITE 0x01 144 #define AUE_EECTL_READ 0x02 145 #define AUE_EECTL_DONE 0x04 146 147 #define AUE_PHYCTL_PHYREG 0x1F 148 #define AUE_PHYCTL_WRITE 0x20 149 #define AUE_PHYCTL_READ 0x40 150 #define AUE_PHYCTL_DONE 0x80 151 152 #define AUE_USBSTS_SUSPEND 0x01 153 #define AUE_USBSTS_RESUME 0x02 154 155 #define AUE_TXSTAT0_JABTIMO 0x04 156 #define AUE_TXSTAT0_CARLOSS 0x08 157 #define AUE_TXSTAT0_NOCARRIER 0x10 158 #define AUE_TXSTAT0_LATECOLL 0x20 159 #define AUE_TXSTAT0_EXCESSCOLL 0x40 160 #define AUE_TXSTAT0_UNDERRUN 0x80 161 162 #define AUE_TXSTAT1_PKTCNT 0x0F 163 #define AUE_TXSTAT1_FIFO_EMPTY 0x40 164 #define AUE_TXSTAT1_FIFO_FULL 0x80 165 166 #define AUE_RXSTAT_OVERRUN 0x01 167 #define AUE_RXSTAT_PAUSE 0x02 168 169 #define AUE_GPIO_IN0 0x01 170 #define AUE_GPIO_OUT0 0x02 171 #define AUE_GPIO_SEL0 0x04 172 #define AUE_GPIO_IN1 0x08 173 #define AUE_GPIO_OUT1 0x10 174 #define AUE_GPIO_SEL1 0x20 175 176 struct aue_intrpkt { 177 u_int8_t aue_txstat0; 178 u_int8_t aue_txstat1; 179 u_int8_t aue_rxstat; 180 u_int8_t aue_rxlostpkt0; 181 u_int8_t aue_rxlostpkt1; 182 u_int8_t aue_wakeupstat; 183 u_int8_t aue_rsvd; 184 u_int8_t _pad; 185 }; 186 #define AUE_INTR_PKTLEN 8 187 188 struct aue_rxpkt { 189 uWord aue_pktlen; 190 uByte aue_rxstat; 191 }; 192 193 #define AUE_RXSTAT_MCAST 0x01 194 #define AUE_RXSTAT_GIANT 0x02 195 #define AUE_RXSTAT_RUNT 0x04 196 #define AUE_RXSTAT_CRCERR 0x08 197 #define AUE_RXSTAT_DRIBBLE 0x10 198 #define AUE_RXSTAT_MASK 0x1E 199 200 201 /*************** The rest belongs in if_auevar.h *************/ 202 203 #define AUE_TX_LIST_CNT 1 204 #define AUE_RX_LIST_CNT 1 205 206 struct aue_softc; 207 208 struct aue_chain { 209 struct aue_softc *aue_sc; 210 usbd_xfer_handle aue_xfer; 211 char *aue_buf; 212 struct mbuf *aue_mbuf; 213 int aue_idx; 214 }; 215 216 struct aue_cdata { 217 struct aue_chain aue_tx_chain[AUE_TX_LIST_CNT]; 218 struct aue_chain aue_rx_chain[AUE_RX_LIST_CNT]; 219 struct aue_intrpkt aue_ibuf; 220 int aue_tx_prod; 221 int aue_tx_cons; 222 int aue_tx_cnt; 223 int aue_rx_prod; 224 }; 225 226 struct aue_softc { 227 USBBASEDEVICE aue_dev; 228 229 #if defined(__FreeBSD__) 230 struct arpcom arpcom; 231 device_t aue_miibus; 232 #define GET_IFP(sc) (&(sc)->arpcom.ac_if) 233 #define GET_MII(sc) (device_get_softc((sc)->aue_miibus)) 234 #elif defined(__NetBSD__) 235 struct ethercom aue_ec; 236 struct mii_data aue_mii; 237 #if NRND > 0 238 rndsource_element_t rnd_source; 239 #endif 240 #define GET_IFP(sc) (&(sc)->aue_ec.ec_if) 241 #define GET_MII(sc) (&(sc)->aue_mii) 242 #elif defined(__OpenBSD__) 243 struct arpcom arpcom; 244 struct mii_data aue_mii; 245 #if NRND > 0 246 rndsource_element_t rnd_source; 247 #endif 248 #define GET_IFP(sc) (&(sc)->arpcom.ac_if) 249 #define GET_MII(sc) (&(sc)->aue_mii) 250 #endif 251 252 usb_callout_t aue_stat_ch; 253 254 usbd_device_handle aue_udev; 255 usbd_interface_handle aue_iface; 256 u_int16_t aue_vendor; 257 u_int16_t aue_product; 258 int aue_ed[AUE_ENDPT_MAX]; 259 usbd_pipe_handle aue_ep[AUE_ENDPT_MAX]; 260 u_int8_t aue_link; 261 int aue_if_flags; 262 struct aue_cdata aue_cdata; 263 264 u_int16_t aue_flags; 265 266 int aue_refcnt; 267 char aue_dying; 268 char aue_attached; 269 u_int aue_rx_errs; 270 u_int aue_intr_errs; 271 struct timeval aue_rx_notice; 272 273 struct usb_task aue_tick_task; 274 struct usb_task aue_stop_task; 275 276 struct lock aue_mii_lock; 277 278 }; 279 280 #define AUE_TIMEOUT 1000 281 #define ETHER_ALIGN 2 282 #define AUE_BUFSZ 1536 283 #define AUE_MIN_FRAMELEN 60 284 #define AUE_TX_TIMEOUT 10000 /* ms */ 285 #define AUE_INTR_INTERVAL 100 /* ms */ 286