1 /* $NetBSD: if_otusreg.h,v 1.2 2010/11/03 20:03:02 christos Exp $ */ 2 /* $OpenBSD: if_otusreg.h,v 1.6 2009/04/06 18:17:01 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 6 * Copyright (c) 2007-2008 Atheros Communications, Inc. 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* USB Endpoints addresses. */ 22 #define AR_EPT_BULK_TX_NO (UE_DIR_OUT | 1) 23 #define AR_EPT_BULK_RX_NO (UE_DIR_IN | 2) 24 #define AR_EPT_INTR_RX_NO (UE_DIR_IN | 3) 25 #define AR_EPT_INTR_TX_NO (UE_DIR_OUT | 4) 26 27 /* USB Requests. */ 28 #define AR_FW_DOWNLOAD 0x30 29 #define AR_FW_DOWNLOAD_COMPLETE 0x31 30 31 /* Maximum number of writes that can fit in a single FW command is 7. */ 32 #define AR_FW_MAX_WRITES 7 /* 56 bytes */ 33 34 #define AR_FW_INIT_ADDR 0x102800 35 #define AR_FW_MAIN_ADDR 0x200000 36 #define AR_USB_MODE_CTRL 0x1e1108 37 38 /* 39 * AR9170 MAC registers. 40 */ 41 #define AR_MAC_REG_BASE 0x1c3000 42 #define AR_MAC_REG_MAC_ADDR_L (AR_MAC_REG_BASE + 0x610) 43 #define AR_MAC_REG_MAC_ADDR_H (AR_MAC_REG_BASE + 0x614) 44 #define AR_MAC_REG_BSSID_L (AR_MAC_REG_BASE + 0x618) 45 #define AR_MAC_REG_BSSID_H (AR_MAC_REG_BASE + 0x61c) 46 #define AR_MAC_REG_GROUP_HASH_TBL_L (AR_MAC_REG_BASE + 0x624) 47 #define AR_MAC_REG_GROUP_HASH_TBL_H (AR_MAC_REG_BASE + 0x628) 48 #define AR_MAC_REG_BASIC_RATE (AR_MAC_REG_BASE + 0x630) 49 #define AR_MAC_REG_MANDATORY_RATE (AR_MAC_REG_BASE + 0x634) 50 #define AR_MAC_REG_RTS_CTS_RATE (AR_MAC_REG_BASE + 0x638) 51 #define AR_MAC_REG_BACKOFF_PROTECT (AR_MAC_REG_BASE + 0x63c) 52 #define AR_MAC_REG_RX_THRESHOLD (AR_MAC_REG_BASE + 0x640) 53 #define AR_MAC_REG_RX_PE_DELAY (AR_MAC_REG_BASE + 0x64c) 54 #define AR_MAC_REG_DYNAMIC_SIFS_ACK (AR_MAC_REG_BASE + 0x658) 55 #define AR_MAC_REG_SNIFFER (AR_MAC_REG_BASE + 0x674) 56 #define AR_MAC_REG_ACK_EXTENSION (AR_MAC_REG_BASE + 0x690) 57 #define AR_MAC_REG_EIFS_AND_SIFS (AR_MAC_REG_BASE + 0x698) 58 #define AR_MAC_REG_BUSY (AR_MAC_REG_BASE + 0x6e8) 59 #define AR_MAC_REG_BUSY_EXT (AR_MAC_REG_BASE + 0x6ec) 60 #define AR_MAC_REG_SLOT_TIME (AR_MAC_REG_BASE + 0x6f0) 61 #define AR_MAC_REG_AC0_CW (AR_MAC_REG_BASE + 0xb00) 62 #define AR_MAC_REG_AC1_CW (AR_MAC_REG_BASE + 0xb04) 63 #define AR_MAC_REG_AC2_CW (AR_MAC_REG_BASE + 0xb08) 64 #define AR_MAC_REG_AC3_CW (AR_MAC_REG_BASE + 0xb0c) 65 #define AR_MAC_REG_AC4_CW (AR_MAC_REG_BASE + 0xb10) 66 #define AR_MAC_REG_AC1_AC0_AIFS (AR_MAC_REG_BASE + 0xb14) 67 #define AR_MAC_REG_AC3_AC2_AIFS (AR_MAC_REG_BASE + 0xb18) 68 #define AR_MAC_REG_RETRY_MAX (AR_MAC_REG_BASE + 0xb28) 69 #define AR_MAC_REG_TXOP_NOT_ENOUGH_INDICATION \ 70 (AR_MAC_REG_BASE + 0xb30) 71 #define AR_MAC_REG_AC1_AC0_TXOP (AR_MAC_REG_BASE + 0xb44) 72 #define AR_MAC_REG_AC3_AC2_TXOP (AR_MAC_REG_BASE + 0xb48) 73 #define AR_MAC_REG_OFDM_PHY_ERRORS (AR_MAC_REG_BASE + 0xcb4) 74 #define AR_MAC_REG_CCK_PHY_ERRORS (AR_MAC_REG_BASE + 0xcb8) 75 #define AR_MAC_REG_BCN_HT1 (AR_MAC_REG_BASE + 0xda0) 76 77 /* Possible values for register AR_USB_MODE_CTRL. */ 78 #define AR_USB_DS_ENA (1 << 0) 79 #define AR_USB_US_ENA (1 << 1) 80 #define AR_USB_US_PACKET_MODE (1 << 3) 81 #define AR_USB_RX_STREAM_4K (0 << 4) 82 #define AR_USB_RX_STREAM_8K (1 << 4) 83 #define AR_USB_RX_STREAM_16K (2 << 4) 84 #define AR_USB_RX_STREAM_32K (3 << 4) 85 #define AR_USB_TX_STREAM_MODE (1 << 6) 86 87 #define AR_LED0_ON (1 << 0) 88 #define AR_LED1_ON (1 << 1) 89 90 /* 91 * PHY registers. 92 */ 93 #define AR_PHY_BASE 0x1c5800 94 #define AR_PHY(reg) (AR_PHY_BASE + (reg) * 4) 95 #define AR_PHY_TURBO (AR_PHY_BASE + 0x0004) 96 #define AR_PHY_RF_CTL3 (AR_PHY_BASE + 0x0028) 97 #define AR_PHY_RF_CTL4 (AR_PHY_BASE + 0x0034) 98 #define AR_PHY_SETTLING (AR_PHY_BASE + 0x0044) 99 #define AR_PHY_RXGAIN (AR_PHY_BASE + 0x0048) 100 #define AR_PHY_DESIRED_SZ (AR_PHY_BASE + 0x0050) 101 #define AR_PHY_FIND_SIG (AR_PHY_BASE + 0x0058) 102 #define AR_PHY_AGC_CTL1 (AR_PHY_BASE + 0x005c) 103 #define AR_PHY_SFCORR (AR_PHY_BASE + 0x0068) 104 #define AR_PHY_SFCORR_LOW (AR_PHY_BASE + 0x006c) 105 #define AR_PHY_TIMING_CTRL4 (AR_PHY_BASE + 0x0120) 106 #define AR_PHY_TIMING5 (AR_PHY_BASE + 0x0124) 107 #define AR_PHY_POWER_TX_RATE1 (AR_PHY_BASE + 0x0134) 108 #define AR_PHY_POWER_TX_RATE2 (AR_PHY_BASE + 0x0138) 109 #define AR_PHY_POWER_TX_RATE_MAX (AR_PHY_BASE + 0x013c) 110 #define AR_PHY_SWITCH_CHAIN_0 (AR_PHY_BASE + 0x0160) 111 #define AR_PHY_SWITCH_COM (AR_PHY_BASE + 0x0164) 112 #define AR_PHY_HEAVY_CLIP_ENABLE (AR_PHY_BASE + 0x01e0) 113 #define AR_PHY_CCK_DETECT (AR_PHY_BASE + 0x0a08) 114 #define AR_PHY_GAIN_2GHZ (AR_PHY_BASE + 0x0a0c) 115 #define AR_PHY_POWER_TX_RATE3 (AR_PHY_BASE + 0x0a34) 116 #define AR_PHY_POWER_TX_RATE4 (AR_PHY_BASE + 0x0a38) 117 #define AR_PHY_TPCRG1 (AR_PHY_BASE + 0x0a58) 118 #define AR_PHY_POWER_TX_RATE5 (AR_PHY_BASE + 0x0b8c) 119 #define AR_PHY_POWER_TX_RATE6 (AR_PHY_BASE + 0x0b90) 120 #define AR_PHY_POWER_TX_RATE7 (AR_PHY_BASE + 0x0bcc) 121 #define AR_PHY_POWER_TX_RATE8 (AR_PHY_BASE + 0x0bd0) 122 #define AR_PHY_POWER_TX_RATE9 (AR_PHY_BASE + 0x0bd4) 123 #define AR_PHY_CCA (AR_PHY_BASE + 0x3064) 124 125 #define AR_SEEPROM_HW_TYPE_OFFSET 0x1374 126 #define AR_EEPROM_OFFSET 0x1600 127 128 #define AR_BANK4_CHUP (1 << 0) 129 #define AR_BANK4_BMODE_LF_SYNTH_FREQ (1 << 1) 130 #define AR_BANK4_AMODE_REFSEL(x) ((x) << 2) 131 #define AR_BANK4_ADDR(x) ((x) << 5) 132 133 /* Tx descriptor. */ 134 struct ar_tx_head { 135 uint16_t len; 136 uint16_t macctl; 137 #define AR_TX_MAC_RTS (1 << 0) 138 #define AR_TX_MAC_CTS (1 << 1) 139 #define AR_TX_MAC_BACKOFF (1 << 3) 140 #define AR_TX_MAC_NOACK (1 << 2) 141 #define AR_TX_MAC_HW_DUR (1 << 9) 142 #define AR_TX_MAC_QID(qid) ((qid) << 10) 143 #define AR_TX_MAC_RATE_PROBING (1 << 15) 144 145 uint32_t phyctl; 146 /* Modulation type. */ 147 #define AR_TX_PHY_MT_CCK 0 148 #define AR_TX_PHY_MT_OFDM 1 149 #define AR_TX_PHY_MT_HT 2 150 #define AR_TX_PHY_GF (1 << 2) 151 #define AR_TX_PHY_BW_SHIFT 3 152 #define AR_TX_PHY_TPC_SHIFT 9 153 #define AR_TX_PHY_ANTMSK(msk) ((msk) << 15) 154 #define AR_TX_PHY_MCS(mcs) ((mcs) << 18) 155 #define AR_TX_PHY_SHGI (1 << 31) 156 } __packed; 157 158 /* USB Rx stream mode header. */ 159 struct ar_rx_head { 160 uint16_t len; 161 uint16_t tag; 162 #define AR_RX_HEAD_TAG 0x4e00 163 } __packed; 164 165 /* Rx descriptor. */ 166 struct ar_rx_tail { 167 uint8_t rssi_ant[3]; 168 uint8_t rssi_ant_ext[3]; 169 uint8_t rssi; /* Combined RSSI. */ 170 uint8_t evm[2][6]; /* Error Vector Magnitude. */ 171 uint8_t phy_err; 172 uint8_t sa_idx; 173 uint8_t da_idx; 174 uint8_t error; 175 #define AR_RX_ERROR_TIMEOUT (1 << 0) 176 #define AR_RX_ERROR_OVERRUN (1 << 1) 177 #define AR_RX_ERROR_DECRYPT (1 << 2) 178 #define AR_RX_ERROR_FCS (1 << 3) 179 #define AR_RX_ERROR_BAD_RA (1 << 4) 180 #define AR_RX_ERROR_PLCP (1 << 5) 181 #define AR_RX_ERROR_MMIC (1 << 6) 182 183 uint8_t status; 184 /* Modulation type (same as AR_TX_PHY_MT). */ 185 #define AR_RX_STATUS_MT_MASK 0x3 186 #define AR_RX_STATUS_MT_CCK 0 187 #define AR_RX_STATUS_MT_OFDM 1 188 #define AR_RX_STATUS_MT_HT 2 189 #define AR_RX_STATUS_SHPREAMBLE (1 << 3) 190 } __packed; 191 192 #define AR_PLCP_HDR_LEN 12 193 /* Magic PLCP header for firmware notifications through Rx bulk pipe. */ 194 static uint8_t AR_PLCP_HDR_INTR[] = { 195 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 196 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 197 }; 198 199 /* Firmware command/reply header. */ 200 struct ar_cmd_hdr { 201 uint8_t len; 202 uint8_t code; 203 #define AR_CMD_RREG 0x00 204 #define AR_CMD_WREG 0x01 205 #define AR_CMD_RMEM 0x02 206 #define AR_CMD_WMEM 0x03 207 #define AR_CMD_BITAND 0x04 208 #define AR_CMD_BITOR 0x05 209 #define AR_CMD_EKEY 0x28 210 #define AR_CMD_DKEY 0x29 211 #define AR_CMD_FREQUENCY 0x30 212 #define AR_CMD_RF_INIT 0x31 213 #define AR_CMD_SYNTH 0x32 214 #define AR_CMD_FREQ_STRAT 0x33 215 #define AR_CMD_ECHO 0x80 216 #define AR_CMD_TALLY 0x81 217 #define AR_CMD_TALLY_APD 0x82 218 #define AR_CMD_CONFIG 0x83 219 #define AR_CMD_RESET 0x90 220 #define AR_CMD_DKRESET 0x91 221 #define AR_CMD_DKTX_STATUS 0x92 222 #define AR_CMD_FDC 0xa0 223 #define AR_CMD_WREEPROM 0xb0 224 #define AR_CMD_WFLASH AR_CMD_WREEPROM 225 #define AR_CMD_FLASH_ERASE 0xb1 226 #define AR_CMD_FLASH_PROG 0xb2 227 #define AR_CMD_FLASH_CHKSUM 0xb3 228 #define AR_CMD_FLASH_READ 0xb4 229 #define AR_CMD_FW_DL_INIT 0xb5 230 #define AR_CMD_MEM_WREEPROM 0xbb 231 /* Those have the 2 MSB set to 1. */ 232 #define AR_EVT_BEACON 0x00 233 #define AR_EVT_TX_COMP 0x01 234 #define AR_EVT_TBTT 0x02 235 #define AR_EVT_ATIM 0x03 236 237 uint16_t token; /* Driver private data. */ 238 } __packed; 239 240 /* Structure for command AR_CMD_RF_INIT/AR_CMD_FREQUENCY. */ 241 struct ar_cmd_frequency { 242 uint32_t freq; 243 uint32_t dynht2040; 244 uint32_t htena; 245 uint32_t dsc_exp; 246 uint32_t dsc_man; 247 uint32_t dsc_shgi_exp; 248 uint32_t dsc_shgi_man; 249 uint32_t check_loop_count; 250 } __packed; 251 252 /* Firmware reply for command AR_CMD_FREQUENCY. */ 253 struct ar_rsp_frequency { 254 uint32_t status; 255 #define AR_CAL_ERR_AGC (1 << 0) /* AGC cal unfinished. */ 256 #define AR_CAL_ERR_NF (1 << 1) /* Noise cal unfinished. */ 257 #define AR_CAL_ERR_NF_VAL (1 << 2) /* NF value unexpected. */ 258 259 uint32_t nf[3]; /* Noisefloor. */ 260 uint32_t nf_ext[3]; /* Noisefloor ext. */ 261 } __packed; 262 263 /* Structure for command AR_CMD_EKEY. */ 264 struct ar_cmd_ekey { 265 uint16_t uid; /* user ID */ 266 uint16_t kix; 267 uint16_t cipher; 268 #define AR_CIPHER_NONE 0 269 #define AR_CIPHER_WEP64 1 270 #define AR_CIPHER_TKIP 2 271 #define AR_CIPHER_AES 4 272 #define AR_CIPHER_WEP128 5 273 #define AR_CIPHER_WEP256 6 274 #define AR_CIPHER_CENC 7 275 276 uint8_t macaddr[IEEE80211_ADDR_LEN]; 277 uint8_t key[16]; 278 } __packed; 279 280 /* Structure for event AR_EVT_TX_COMP. */ 281 struct ar_evt_tx_comp { 282 uint8_t macaddr[IEEE80211_ADDR_LEN]; 283 uint32_t phy; 284 uint16_t status; 285 #define AR_TX_STATUS_COMP 0 286 #define AR_TX_STATUS_RETRY_COMP 1 287 #define AR_TX_STATUS_FAILED 2 288 } __packed; 289 290 /* 291 * EEPROM. 292 */ 293 /* Possible flags for opCapFlags. */ 294 #define AR5416_OPFLAGS_11A 0x01 295 #define AR5416_OPFLAGS_11G 0x02 296 #define AR5416_OPFLAGS_5G_HT40 0x04 297 #define AR5416_OPFLAGS_2G_HT40 0x08 298 #define AR5416_OPFLAGS_5G_HT20 0x10 299 #define AR5416_OPFLAGS_2G_HT20 0x20 300 301 #define AR5416_NUM_5G_CAL_PIERS 8 302 #define AR5416_NUM_2G_CAL_PIERS 4 303 #define AR5416_NUM_5G_20_TARGET_POWERS 8 304 #define AR5416_NUM_5G_40_TARGET_POWERS 8 305 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3 306 #define AR5416_NUM_2G_20_TARGET_POWERS 4 307 #define AR5416_NUM_2G_40_TARGET_POWERS 4 308 #define AR5416_NUM_CTLS 24 309 #define AR5416_NUM_BAND_EDGES 8 310 #define AR5416_NUM_PD_GAINS 4 311 #define AR5416_PD_GAIN_ICEPTS 5 312 #define AR5416_EEPROM_MODAL_SPURS 5 313 #define AR5416_MAX_CHAINS 2 314 315 typedef struct BaseEepHeader { 316 uint16_t length; 317 uint16_t checksum; 318 uint16_t version; 319 uint8_t opCapFlags; 320 uint8_t eepMisc; 321 uint16_t regDmn[2]; 322 uint8_t macAddr[6]; 323 uint8_t rxMask; 324 uint8_t txMask; 325 uint16_t rfSilent; 326 uint16_t blueToothOptions; 327 uint16_t deviceCap; 328 uint32_t binBuildNumber; 329 uint8_t deviceType; 330 uint8_t futureBase[33]; 331 } __packed BASE_EEP_HEADER; 332 333 typedef struct spurChanStruct { 334 uint16_t spurChan; 335 uint8_t spurRangeLow; 336 uint8_t spurRangeHigh; 337 } __packed SPUR_CHAN; 338 339 typedef struct ModalEepHeader { 340 uint32_t antCtrlChain[AR5416_MAX_CHAINS]; 341 uint32_t antCtrlCommon; 342 int8_t antennaGainCh[AR5416_MAX_CHAINS]; 343 uint8_t switchSettling; 344 uint8_t txRxAttenCh[AR5416_MAX_CHAINS]; 345 uint8_t rxTxMarginCh[AR5416_MAX_CHAINS]; 346 uint8_t adcDesiredSize; 347 int8_t pgaDesiredSize; 348 uint8_t xlnaGainCh[AR5416_MAX_CHAINS]; 349 uint8_t txEndToXpaOff; 350 uint8_t txEndToRxOn; 351 uint8_t txFrameToXpaOn; 352 uint8_t thresh62; 353 uint8_t noiseFloorThreshCh[AR5416_MAX_CHAINS]; 354 uint8_t xpdGain; 355 uint8_t xpd; 356 int8_t iqCalICh[AR5416_MAX_CHAINS]; 357 int8_t iqCalQCh[AR5416_MAX_CHAINS]; 358 uint8_t pdGainOverlap; 359 uint8_t ob; 360 uint8_t db; 361 uint8_t xpaBiasLvl; 362 uint8_t pwrDecreaseFor2Chain; 363 uint8_t pwrDecreaseFor3Chain; 364 uint8_t txFrameToDataStart; 365 uint8_t txFrameToPaOn; 366 uint8_t ht40PowerIncForPdadc; 367 uint8_t bswAtten[AR5416_MAX_CHAINS]; 368 uint8_t bswMargin[AR5416_MAX_CHAINS]; 369 uint8_t swSettleHt40; 370 uint8_t futureModal[22]; 371 SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; 372 } __packed MODAL_EEP_HEADER; 373 374 typedef struct calDataPerFreq { 375 uint8_t pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 376 uint8_t vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 377 } __packed CAL_DATA_PER_FREQ; 378 379 typedef struct CalTargetPowerLegacy { 380 uint8_t bChannel; 381 uint8_t tPow2x[4]; 382 } __packed CAL_TARGET_POWER_LEG; 383 384 typedef struct CalTargetPowerHt { 385 uint8_t bChannel; 386 uint8_t tPow2x[8]; 387 } __packed CAL_TARGET_POWER_HT; 388 389 typedef struct CalCtlEdges { 390 uint8_t bChannel; 391 uint8_t tPowerFlag; 392 } __packed CAL_CTL_EDGES; 393 394 typedef struct CalCtlData { 395 CAL_CTL_EDGES ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; 396 } __packed CAL_CTL_DATA; 397 398 typedef struct ar5416eeprom { 399 BASE_EEP_HEADER baseEepHeader; 400 uint8_t custData[64]; 401 MODAL_EEP_HEADER modalHeader[2]; 402 uint8_t calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; 403 uint8_t calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; 404 CAL_DATA_PER_FREQ calPierData5G[AR5416_MAX_CHAINS] 405 [AR5416_NUM_5G_CAL_PIERS]; 406 CAL_DATA_PER_FREQ calPierData2G[AR5416_MAX_CHAINS] 407 [AR5416_NUM_2G_CAL_PIERS]; 408 CAL_TARGET_POWER_LEG calTPow5G[AR5416_NUM_5G_20_TARGET_POWERS]; 409 CAL_TARGET_POWER_HT calTPow5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; 410 CAL_TARGET_POWER_HT calTPow5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; 411 CAL_TARGET_POWER_LEG calTPowCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; 412 CAL_TARGET_POWER_LEG calTPow2G[AR5416_NUM_2G_20_TARGET_POWERS]; 413 CAL_TARGET_POWER_HT calTPow2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; 414 CAL_TARGET_POWER_HT calTPow2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; 415 uint8_t ctlIndex[AR5416_NUM_CTLS]; 416 CAL_CTL_DATA ctlData[AR5416_NUM_CTLS]; 417 uint8_t padding[3]; 418 } __packed AR5416_EEPROM; 419